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From: Andrew Jeffery <andrew@aj.id.au>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Joel Stanley <joel@jms.id.au>,
	Alexandre Courbot <gnurou@gmail.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Jeremy Kerr <jk@ozlabs.org>,
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs
Date: Thu, 08 Sep 2016 13:28:25 +0930	[thread overview]
Message-ID: <1473307105.10397.23.camel@aj.id.au> (raw)
In-Reply-To: <CACRpkdb2ftH5B5VqKW9rPU=LMeWjrfo9jBTP5DKbNYeZAoMC8Q@mail.gmail.com>

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On Wed, 2016-09-07 at 16:50 +0200, Linus Walleij wrote:
> On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> 
> > 
> > The Aspeed SoCs typically provide more than 200 pins for GPIO and other
> > functions. The signal enabled on a pin is determined on a priority
> > basis, where a given pin can provide a number of different signal types.
> > 
> > In addition to the priority levels, the Aspeed pin controllers describe
> > the signal active on a pin by compound logical expressions involving
> > multiple operators, registers and bits. Some difficulty arises as a
> > pin's function bit masks for each priority level are frequently not the
> > same (i.e. we cannot just flip a bit to change from a high to low
> > priority signal), or even in the same register(s). Some configuration
> > bits affect multiple pins, while in other cases the signals for a bus
> > must each be enabled individually.
> > 
> > Together, these features give rise to some complexity in the
> > implementation. A more complete description of the complexities is
> > provided in the associated header file.
> > 
> > The patch doesn't implement pinctrl/pinmux/pinconf for any particular
> > Aspeed SoC, rather it adds the framework for defining pinmux
> > configurations.
> > 
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> Patch applied! It's not getting better than this through iteration, it is better
> to get the system up and develop inside the mainline tree from now on.
> 
> > 
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1027,6 +1027,7 @@ S:        Maintained
> >  F:     arch/arm/mach-aspeed/
> >  F:     arch/arm/boot/dts/aspeed-*
> >  F:     drivers/*/*aspeed*
> > +F:     drivers/pinctrl/aspeed/
> >  F:     Documentation/devicetree/bindings/*/*aspeed*
> I dropped this hunk of the patch, because:
> 
> (A) I didn't merge the glob patch and

Okay

> (B) the glob covers this driver too, it is a tautology/truism

So experimenting with this my results don't agree - without the hunk
get_maintainer.pl falls back to git and s-o-bs to pick up the Aspeed
maintainer:

With the hunk:

    $ ./scripts/get_maintainer.pl drivers/pinctrl/aspeed/pinctrl-aspeed.c
    Joel Stanley <    joel@jms.id.au    > (maintainer:ARM/ASPEED MACHINE SUPPORT)
    Linus Walleij <    linus.walleij@linaro.org    > (maintainer:PIN CONTROL SUBSYSTEM)
    linux-gpio@vger.kernel.org     (open list:PIN CONTROL SUBSYSTEM)

Without the hunk:

    $ ./scripts/get_maintainer.pl drivers/pinctrl/aspeed/pinctrl-aspeed.c
    Linus Walleij <    linus.walleij@linaro.org    > (maintainer:PIN CONTROL SUBSYSTEM)
    Joel Stanley <    joel@jms.id.au    > (commit_signer:1/1=100%)
    Andrew Jeffery <    andrew@aj.id.au    > (commit_signer:1/1=100%,authored:1/1=100%,added_lines:498/498=100%)
    linux-gpio@vger.kernel.org     (open list:PIN CONTROL SUBSYSTEM)
    linux-kernel@vger.kernel.org     (open list)

So removing git as a fallback Joel isn't listed as a relevant
maintainer despite the glob:

    $ ./scripts/get_maintainer.pl --no-git-fallback drivers/pinctrl/aspeed/pinctrl-aspeed.c
    Linus Walleij <    linus.walleij@linaro.org    > (maintainer:PIN CONTROL SUBSYSTEM)
    linux-gpio@vger.kernel.org     (open list:PIN CONTROL SUBSYSTEM)
    linux-kernel@vger.kernel.org     (open list)

I expect it's the case that the globbing doesn't match directories like
the hunk in question does with its trailing '/'. However, given we will
likely do something different in light of Arnd's suggestion it probably
doesn't matter.

Cheers,

Andrew

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  reply	other threads:[~2016-09-08  3:58 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-30  7:54 [PATCH v3 0/8] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-08-30  7:54 ` [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings Andrew Jeffery
2016-09-07 14:37   ` Linus Walleij
2016-09-07 14:42     ` Arnd Bergmann
2016-08-30  7:54 ` [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
2016-09-07 14:38   ` Linus Walleij
2016-09-07 16:30     ` Lee Jones
2016-09-08  1:03       ` Andrew Jeffery
2016-09-08  1:01     ` Andrew Jeffery
2016-09-08  7:01       ` Lee Jones
2016-08-30  7:54 ` [PATCH v3 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
2016-09-07 14:40   ` Linus Walleij
2016-08-30  7:54 ` [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
2016-09-02 15:00   ` Rob Herring
2016-09-07 14:43   ` Linus Walleij
2016-09-08  1:19     ` Andrew Jeffery
2016-08-30  7:54 ` [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs Andrew Jeffery
2016-09-07 14:50   ` Linus Walleij
2016-09-08  3:58     ` Andrew Jeffery [this message]
2016-08-30  7:54 ` [PATCH v3 6/8] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
2016-09-07 14:53   ` Linus Walleij
2016-08-30  7:54 ` [PATCH v3 7/8] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
2016-09-07 14:54   ` Linus Walleij
2016-08-30  7:54 ` [PATCH v3 8/8] gpio: Add Aspeed driver Andrew Jeffery
2016-09-07 14:59   ` Linus Walleij

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