From: Andrew Jeffery <andrew@aj.id.au>
To: Lee Jones <lee.jones@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Joel Stanley <joel@jms.id.au>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Andrew Jeffery <andrew@aj.id.au>
Subject: [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins
Date: Thu, 3 Nov 2016 01:07:55 +1030 [thread overview]
Message-ID: <1478097481-14895-1-git-send-email-andrew@aj.id.au> (raw)
Hi all,
This is v2 of the series implementing the remainder of the pinmux tables for
the AST2400 and AST2500 SoCs. v1 of the series can be found here:
https://lkml.org/lkml/2016/9/27/309
The first patch, "pinctrl-aspeed-g5: Never set SCU90[6]", is another fix that
should be applied for 4.9. Please let me know if I should send such patches
separately, as the series otherwise targets 4.10.
v2 is based on 4.9-rc2 as requested in feedback on v1.
Cheers,
Andrew
Significant changes since v1:
* Fixes from v1 have been applied, so have been dropped for v2
* A new fix has appeared, "pinctrl-aspeed-g5: Never set SCU90[6]", as noted
above
* New bindings documents for the SoC Display and LPC Host Controllers, driven
by the patch "pinctrl: aspeed: Read and write bits in LPCHC and GFX
controllers"
* The v1 patch "pinctrl: aspeed: Enable capture of off-SCU pinmux state" has
been significantly reworked and is now titled "pinctrl: aspeed: Read and
write bits in LPCHC and GFX controllers"
Andrew Jeffery (6):
pinctrl-aspeed-g5: Never set SCU90[6]
mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers
pinctrl: aspeed-g4: Add mux configuration for all pins
pinctrl: aspeed-g5: Add mux configuration for all pins
.../devicetree/bindings/mfd/aspeed-gfx.txt | 17 +
.../devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 86 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1115 +++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1514 +++++++++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 66 +-
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 33 +-
7 files changed, 2760 insertions(+), 88 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
--
2.7.4
next reply other threads:[~2016-11-02 14:39 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 14:37 Andrew Jeffery [this message]
2016-11-02 14:37 ` [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6] Andrew Jeffery
2016-11-03 22:59 ` Joel Stanley
2016-11-07 9:34 ` Linus Walleij
2016-11-07 22:42 ` Andrew Jeffery
2016-11-07 9:32 ` Linus Walleij
2016-11-02 14:37 ` [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-10 3:19 ` Joel Stanley
2016-11-10 17:40 ` Rob Herring
2016-11-18 18:47 ` Lee Jones
2016-11-02 14:37 ` [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Andrew Jeffery
2016-11-03 23:06 ` Joel Stanley
2016-11-04 3:45 ` Andrew Jeffery
2016-11-18 18:44 ` Lee Jones
2016-11-18 18:45 ` Lee Jones
2016-11-22 3:25 ` Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Andrew Jeffery
2016-11-03 23:24 ` Joel Stanley
2016-11-04 3:59 ` Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-09 23:50 ` Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 5/6] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 6/6] pinctrl: aspeed-g5: " Andrew Jeffery
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