From: Rob Herring <robh@kernel.org>
To: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>,
Lee Jones <lee.jones@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
Date: Thu, 10 Nov 2016 11:40:35 -0600 [thread overview]
Message-ID: <CAL_JsqLN5veD9QHMmEqX5mmX+iHM69O=o+KFauej1QdqEpyUhw@mail.gmail.com> (raw)
In-Reply-To: <CACPK8XeG2WnpNuHUf9VD+mZenWboq-4wei=LOkN4qVR72QbGXQ@mail.gmail.com>
On Wed, Nov 9, 2016 at 9:19 PM, Joel Stanley <joel@jms.id.au> wrote:
> On Thu, Nov 10, 2016 at 4:56 AM, Rob Herring <robh@kernel.org> wrote:
>> On Thu, Nov 03, 2016 at 01:07:57AM +1030, Andrew Jeffery wrote:
>>> The Aspeed SoC Display Controller is presented as a syscon device to
>>> arbitrate access by display and pinmux drivers. Video pinmux
>>> configuration on fifth generation SoCs depends on bits in both the
>>> System Control Unit and the Display Controller.
>>>
>>> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>>> ---
>>> Documentation/devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++++++++++++++++
>>
>> The register space can't be split to 2 nodes?
>
> Do you mean splitting the GFX IP and enable register into two nodes?
>
> We can't. Pinmux needs to check bit 6 and 7 in GFX064, which is in the
> middle the IP block:
>
> GFX060: CRT Control Register I
> GFX064: CRT Control Register II
> GFX068: CRT Status Register
> GFX06C: CRT Misc Setting Register
Okay.
>>> +The Aspeed SoC Display Controller primarily does as its name suggests, but also
>>> +participates in pinmux requests on the g5 SoCs. It is therefore considered a
>>> +syscon device.
>>> +
>>> +Required properties:
>>> +- compatible: "aspeed,ast2500-gfx", "syscon"
>>
>> I think perhaps we should drop the syscon here and the driver should
>> just register as a syscon.
>
> We want the regmap to be present whenever the GFX driver or pinmux is
> loaded. If we register it in pinmux but chose to not build in that
> driver, we lack the regmap. Same for the case where a user builds in
> the GFX driver and not pinmux. I think this means we want the syscon
> compatible string, unless my understanding is wrong?
Right.
Acked-by: Rob Herring <robh@kernel.org>
Rob
next prev parent reply other threads:[~2016-11-10 17:41 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 14:37 [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6] Andrew Jeffery
2016-11-03 22:59 ` Joel Stanley
2016-11-07 9:34 ` Linus Walleij
2016-11-07 22:42 ` Andrew Jeffery
2016-11-07 9:32 ` Linus Walleij
2016-11-02 14:37 ` [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-10 3:19 ` Joel Stanley
2016-11-10 17:40 ` Rob Herring [this message]
2016-11-18 18:47 ` Lee Jones
2016-11-02 14:37 ` [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Andrew Jeffery
2016-11-03 23:06 ` Joel Stanley
2016-11-04 3:45 ` Andrew Jeffery
2016-11-18 18:44 ` Lee Jones
2016-11-18 18:45 ` Lee Jones
2016-11-22 3:25 ` Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Andrew Jeffery
2016-11-03 23:24 ` Joel Stanley
2016-11-04 3:59 ` Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-09 23:50 ` Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 5/6] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 6/6] pinctrl: aspeed-g5: " Andrew Jeffery
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