From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Arnd Bergmann <arnd@arndb.de>
Cc: <linux-pci@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-samsung-soc@vger.kernel.org>,
<linuxppc-dev@lists.ozlabs.org>, <linux-arm-kernel@axis.com>,
<linux-arm-msm@vger.kernel.org>, <nsekhar@ti.com>,
<kishon@ti.com>
Subject: [PATCH 04/37] PCI: dwc: designware: Move the register defines to designware header file
Date: Thu, 12 Jan 2017 15:55:53 +0530 [thread overview]
Message-ID: <1484216786-17292-5-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1484216786-17292-1-git-send-email-kishon@ti.com>
No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to
split the pcie-designware.c file into designware core file and host
specific file.
While at that also fix a checkpatch warning.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 70 ------------------------------------
drivers/pci/dwc/pcie-designware.h | 71 +++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index d68bc7b..0b928dc 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -25,76 +25,6 @@
#include "pcie-designware.h"
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
-/* Parameters for the waiting for iATU enabled routine */
-#define LINK_WAIT_MAX_IATU_RETRIES 5
-#define LINK_WAIT_IATU_MIN 9000
-#define LINK_WAIT_IATU_MAX 10000
-
-/* Synopsys-specific PCIe configuration registers */
-#define PCIE_PORT_LINK_CONTROL 0x710
-#define PORT_LINK_MODE_MASK (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES (0x7 << 16)
-#define PORT_LINK_MODE_8_LANES (0xf << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
-#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
-#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
-
-#define PCIE_MSI_ADDR_LO 0x820
-#define PCIE_MSI_ADDR_HI 0x824
-#define PCIE_MSI_INTR0_ENABLE 0x828
-#define PCIE_MSI_INTR0_MASK 0x82C
-#define PCIE_MSI_INTR0_STATUS 0x830
-
-#define PCIE_ATU_VIEWPORT 0x900
-#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
-#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
-#define PCIE_ATU_CR1 0x904
-#define PCIE_ATU_TYPE_MEM (0x0 << 0)
-#define PCIE_ATU_TYPE_IO (0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
-#define PCIE_ATU_CR2 0x908
-#define PCIE_ATU_ENABLE (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
-#define PCIE_ATU_LOWER_BASE 0x90C
-#define PCIE_ATU_UPPER_BASE 0x910
-#define PCIE_ATU_LIMIT 0x914
-#define PCIE_ATU_LOWER_TARGET 0x918
-#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET 0x91C
-
-/*
- * iATU Unroll-specific register definitions
- * From 4.80 core version the address translation will be made by unroll
- */
-#define PCIE_ATU_UNR_REGION_CTRL1 0x00
-#define PCIE_ATU_UNR_REGION_CTRL2 0x04
-#define PCIE_ATU_UNR_LOWER_BASE 0x08
-#define PCIE_ATU_UNR_UPPER_BASE 0x0C
-#define PCIE_ATU_UNR_LIMIT 0x10
-#define PCIE_ATU_UNR_LOWER_TARGET 0x14
-#define PCIE_ATU_UNR_UPPER_TARGET 0x18
-
-/* Register address builder */
-#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((0x3 << 20) | (region << 9))
-
/* PCIe Port Logic registers */
#define PLR_OFFSET 0x700
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 32f4602..a6cf9262 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -14,6 +14,77 @@
#ifndef _PCIE_DESIGNWARE_H
#define _PCIE_DESIGNWARE_H
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+
+/* Parameters for the waiting for iATU enabled routine */
+#define LINK_WAIT_MAX_IATU_RETRIES 5
+#define LINK_WAIT_IATU_MIN 9000
+#define LINK_WAIT_IATU_MAX 10000
+
+/* Synopsys-specific PCIe configuration registers */
+#define PCIE_PORT_LINK_CONTROL 0x710
+#define PORT_LINK_MODE_MASK (0x3f << 16)
+#define PORT_LINK_MODE_1_LANES (0x1 << 16)
+#define PORT_LINK_MODE_2_LANES (0x3 << 16)
+#define PORT_LINK_MODE_4_LANES (0x7 << 16)
+#define PORT_LINK_MODE_8_LANES (0xf << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
+
+#define PCIE_MSI_ADDR_LO 0x820
+#define PCIE_MSI_ADDR_HI 0x824
+#define PCIE_MSI_INTR0_ENABLE 0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS 0x830
+
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+/*
+ * iATU Unroll-specific register definitions
+ * From 4.80 core version the address translation will be made by unroll
+ */
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
+#define PCIE_ATU_UNR_REGION_CTRL2 0x04
+#define PCIE_ATU_UNR_LOWER_BASE 0x08
+#define PCIE_ATU_UNR_UPPER_BASE 0x0C
+#define PCIE_ATU_UNR_LIMIT 0x10
+#define PCIE_ATU_UNR_LOWER_TARGET 0x14
+#define PCIE_ATU_UNR_UPPER_TARGET 0x18
+
+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
+ ((0x3 << 20) | ((region) << 9))
+
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed,
--
1.7.9.5
next prev parent reply other threads:[~2017-01-12 10:28 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 10:25 [PATCH 00/37] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 01/37] PCI: dwc: dra7xx: Group all host related setup in add_pcie_port Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-01-13 16:34 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 03/37] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
2017-01-12 10:25 ` Kishon Vijay Abraham I [this message]
2017-01-13 16:35 ` [PATCH 04/37] PCI: dwc: designware: Move the register defines to designware header file Joao Pinto
2017-01-12 10:25 ` [PATCH 05/37] PCI: dwc: Add platform_set_drvdata Kishon Vijay Abraham I
2017-01-13 17:16 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write Kishon Vijay Abraham I
2017-01-13 16:36 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init Kishon Vijay Abraham I
2017-01-13 17:22 ` Joao Pinto
2017-01-12 10:25 ` [RFT PATCH 08/37] PCI: dwc: Split *struct pcie_port* into host only and core structures Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Kishon Vijay Abraham I
2017-01-13 17:13 ` Joao Pinto
2017-01-16 5:19 ` Kishon Vijay Abraham I
2017-01-16 10:23 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c Kishon Vijay Abraham I
2017-01-13 16:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I
2017-01-13 16:49 ` Joao Pinto
2017-01-16 5:21 ` Kishon Vijay Abraham I
2017-01-16 10:27 ` Joao Pinto
2017-01-16 11:30 ` Kishon Vijay Abraham I
2017-01-16 13:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 12/37] PCI: dwc: Create a new config symbol to enable pci dwc host Kishon Vijay Abraham I
2017-01-13 17:50 ` Joao Pinto
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 13/37] PCI: dwc: Remove dependency of designware to CONFIG_PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 14/37] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-01-13 18:06 ` Christoph Hellwig
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 15:51 ` Christoph Hellwig
2017-01-12 10:26 ` [PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 18/37] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 19/37] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 20/37] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 21/37] PCI: dwc: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 24/37] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 25/37] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
2017-01-18 21:36 ` Rob Herring
2017-01-12 10:26 ` [PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 27/37] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
2017-01-18 21:45 ` Rob Herring
2017-01-12 10:26 ` [PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
2017-01-18 21:46 ` Rob Herring
2017-02-16 8:33 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 31/37] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
2017-01-24 16:02 ` Christoph Hellwig
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 35/37] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
2017-01-13 17:15 ` Tony Lindgren
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-20 18:28 ` Tony Lindgren
2017-01-12 10:26 ` [PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode Kishon Vijay Abraham I
2017-01-20 18:30 ` Tony Lindgren
2017-02-16 10:00 ` Kishon Vijay Abraham I
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