From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Arnd Bergmann <arnd@arndb.de>,
linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org,
nsekhar@ti.com
Subject: Re: [PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
Date: Wed, 18 Jan 2017 15:45:05 -0600 [thread overview]
Message-ID: <20170118214505.5kcoowi4ooy7eepg@rob-hp-laptop> (raw)
In-Reply-To: <1484216786-17292-29-git-send-email-kishon@ti.com>
On Thu, Jan 12, 2017 at 03:56:17PM +0530, Kishon Vijay Abraham I wrote:
> Add device tree binding documentation for pci dra7xx EP mode.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Documentation/devicetree/bindings/pci/ti-pci.txt | 37 ++++++++++++++++++----
> 1 file changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 60e2516..62f5f59 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -1,17 +1,22 @@
> TI PCI Controllers
>
> PCIe Designware Controller
> - - compatible: Should be "ti,dra7-pcie""
> - - reg : Two register ranges as listed in the reg-names property
> - - reg-names : The first entry must be "ti-conf" for the TI specific registers
> - The second entry must be "rc-dbics" for the designware pcie
> - registers
> - The third entry must be "config" for the PCIe configuration space
> + - compatible: Should be "ti,dra7-pcie" for RC
> + Should be "ti,dra7-pcie-ep" for EP
> - phys : list of PHY specifiers (used by generic PHY framework)
> - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> number of PHYs as specified in *phys* property.
> - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
> where <X> is the instance number of the pcie from the HW spec.
> + - num-lanes as specified in ../designware-pcie.txt
> +
> +HOST MODE
> +=========
> + - reg : Two register ranges as listed in the reg-names property
> + - reg-names : The first entry must be "ti-conf" for the TI specific registers
> + The second entry must be "rc-dbics" for the designware pcie
> + registers
> + The third entry must be "config" for the PCIe configuration space
> - interrupts : Two interrupt entries must be specified. The first one is for
> main interrupt line and the second for MSI interrupt line.
> - #address-cells,
> @@ -19,13 +24,31 @@ PCIe Designware Controller
> #interrupt-cells,
> device_type,
> ranges,
> - num-lanes,
> interrupt-map-mask,
> interrupt-map : as specified in ../designware-pcie.txt
>
> +DEVICE MODE
> +===========
> + - reg : Four register ranges as listed in the reg-names property
> + - reg-names : "ti-conf" for the TI specific registers
> + "ep_dbics" for the standard configuration registers as
> + they are locally accessed within the DIF CS space
> + "ep_dbics2" for the standard configuration registers as
> + they are locally accessed within the DIF CS2 space
> + "addr_space" used to map remote RC address space
> + - interrupts : one interrupt entries must be specified for main interrupt.
> + - num-ib-windows : number of inbound address translation windows
> + - num-ob-windows : number of outbound address translation windows
> +
> Optional Property:
> - gpios : Should be added if a gpio line is required to drive PERST# line
>
> +NOTE: Two dt nodes should be added for each PCI controller; one for host
s/should/may/
Don't define dts source structure here. You could also have 2 files with
each config and just include the right one for each board.
We don't want overlapping memory regions defined in DT and this kind of
violates that, but I guess status is sufficient.
With that,
Acked-by: Rob Herring <robh@kernel.org>
> +mode and another for device mode. So in order for PCI to
> +work in host mode, EP mode dt node should be disabled and in order to PCI to
> +work in EP mode, host mode dt node should be disabled. And host mode and EP
> +mode are mutually exclusive.
> +
> Example:
> axi {
> compatible = "simple-bus";
> --
> 1.7.9.5
>
> --
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next prev parent reply other threads:[~2017-01-18 21:45 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 10:25 [PATCH 00/37] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 01/37] PCI: dwc: dra7xx: Group all host related setup in add_pcie_port Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-01-13 16:34 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 03/37] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 04/37] PCI: dwc: designware: Move the register defines to designware header file Kishon Vijay Abraham I
2017-01-13 16:35 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 05/37] PCI: dwc: Add platform_set_drvdata Kishon Vijay Abraham I
2017-01-13 17:16 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write Kishon Vijay Abraham I
2017-01-13 16:36 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init Kishon Vijay Abraham I
2017-01-13 17:22 ` Joao Pinto
2017-01-12 10:25 ` [RFT PATCH 08/37] PCI: dwc: Split *struct pcie_port* into host only and core structures Kishon Vijay Abraham I
2017-01-12 10:25 ` [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Kishon Vijay Abraham I
2017-01-13 17:13 ` Joao Pinto
2017-01-16 5:19 ` Kishon Vijay Abraham I
2017-01-16 10:23 ` Joao Pinto
2017-01-12 10:25 ` [PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c Kishon Vijay Abraham I
2017-01-13 16:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I
2017-01-13 16:49 ` Joao Pinto
2017-01-16 5:21 ` Kishon Vijay Abraham I
2017-01-16 10:27 ` Joao Pinto
2017-01-16 11:30 ` Kishon Vijay Abraham I
2017-01-16 13:38 ` Joao Pinto
2017-01-12 10:26 ` [PATCH 12/37] PCI: dwc: Create a new config symbol to enable pci dwc host Kishon Vijay Abraham I
2017-01-13 17:50 ` Joao Pinto
2017-01-16 5:22 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 13/37] PCI: dwc: Remove dependency of designware to CONFIG_PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 14/37] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-01-13 18:06 ` Christoph Hellwig
2017-01-16 6:01 ` Kishon Vijay Abraham I
2017-01-16 15:51 ` Christoph Hellwig
2017-01-12 10:26 ` [PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 18/37] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 19/37] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 20/37] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 21/37] PCI: dwc: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 24/37] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 25/37] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
2017-01-18 21:36 ` Rob Herring
2017-01-12 10:26 ` [PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 27/37] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
2017-01-18 21:45 ` Rob Herring [this message]
2017-01-12 10:26 ` [PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
2017-01-18 21:46 ` Rob Herring
2017-02-16 8:33 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 31/37] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
2017-01-24 16:02 ` Christoph Hellwig
2017-01-25 5:40 ` Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 35/37] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-01-12 10:26 ` [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
2017-01-13 17:15 ` Tony Lindgren
2017-01-16 6:05 ` Kishon Vijay Abraham I
2017-01-20 18:28 ` Tony Lindgren
2017-01-12 10:26 ` [PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode Kishon Vijay Abraham I
2017-01-20 18:30 ` Tony Lindgren
2017-02-16 10:00 ` Kishon Vijay Abraham I
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