* [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups
@ 2017-03-09 6:38 Kishon Vijay Abraham I
2017-03-09 6:38 ` [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:38 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon
Resending since it bounced from quite a few lists.
This should be the final set of cleanups/fixes before endpoint
support can be merged.
Keerthy's patch is a general fix in dra7xx driver and is not
directly related to endpoint mode.
This v1 of this series was previously sent with a different
cover letter $subject [1]
Changes from v2:
*) Kconfig changes that was spilled into a patch is removed.
*) In addition to renaming _unroll() to _ob_unroll(), all the
_unroll configurations is also moved a separate function.
Changes from v1:
*) included a patch to rename _unroll() to _ob_unroll() as
similar thing has to be done for inbound window in the case
of EP mode.
*) used 'size_t' instead of 'int' for specifying the size
in read_dbi/write_dbi function arguments.
*) Populate cpu_addr_fixup ops for artpec6 as suggested by
Niklas
This series is based on 4.11-rc1
[1] -> https://lkml.org/lkml/2017/2/16/270
Keerthy (1):
PCI: dwc: dra7xx: Push request_irq call to the bottom of probe
Kishon Vijay Abraham I (6):
PCI: dwc: designware: Add new *ops* for cpu addr fixup
PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
PCI: dwc: artpec6: Populate cpu_addr_fixup ops
PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
PCI: dwc: designware: Move _unroll configurations to a separate
function
drivers/pci/dwc/pci-dra7xx.c | 35 +++----
drivers/pci/dwc/pci-exynos.c | 14 +--
drivers/pci/dwc/pci-imx6.c | 62 +++++++------
drivers/pci/dwc/pci-keystone-dw.c | 16 ++--
drivers/pci/dwc/pcie-armada8k.c | 39 ++++----
drivers/pci/dwc/pcie-artpec6.c | 22 +++--
drivers/pci/dwc/pcie-designware-host.c | 20 ++--
drivers/pci/dwc/pcie-designware.c | 156 +++++++++++++++++++++-----------
drivers/pci/dwc/pcie-designware.h | 13 ++-
drivers/pci/dwc/pcie-hisi.c | 17 ++--
10 files changed, 241 insertions(+), 153 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
@ 2017-03-09 6:38 ` Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
` (5 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:38 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon
Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 3 +++
drivers/pci/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d..14ee7a3 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
{
u32 retries, val;
+ if (pp->ops->cpu_addr_fixup)
+ cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+
if (pci->iatu_unroll_enabled) {
dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b871..8f3dcb2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
};
struct dw_pcie_ops {
+ u64 (*cpu_addr_fixup)(u64 cpu_addr);
u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
int (*link_up)(struct dw_pcie *pcie);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
2017-03-09 6:38 ` [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 3/7] PCI: dwc: artpec6: " Kishon Vijay Abraham I
` (4 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 0984baf..07c45ec 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -88,6 +88,11 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
writel(value, pcie->base + offset);
}
+static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr)
+{
+ return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
+}
+
static int dra7xx_pcie_link_up(struct dw_pcie *pci)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
@@ -152,11 +157,6 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
- pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
- pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
- pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
- pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
-
dw_pcie_setup_rc(pp);
dra7xx_pcie_establish_link(dra7xx);
@@ -329,6 +329,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
}
static const struct dw_pcie_ops dw_pcie_ops = {
+ .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
.link_up = dra7xx_pcie_link_up,
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
2017-03-09 6:38 ` [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
2017-03-09 10:21 ` Niklas Cassel
2017-03-09 6:39 ` [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
` (3 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon, Niklas Cassel
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Cc: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-artpec6.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index fcd3ef8..5b3b3af 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -78,6 +78,11 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
regmap_write(artpec6_pcie->regmap, offset, val);
}
+static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
+{
+ return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
+}
+
static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
{
struct dw_pcie *pci = artpec6_pcie->pci;
@@ -142,11 +147,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
*/
dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
- pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
- pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
- pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
- pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
-
/* setup root complex */
dw_pcie_setup_rc(pp);
@@ -234,6 +234,10 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
return 0;
}
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+};
+
static int artpec6_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
return -ENOMEM;
pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
artpec6_pcie->pci = pci;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
` (2 preceding siblings ...)
2017-03-09 6:39 ` [RESEND PATCH v3 3/7] PCI: dwc: artpec6: " Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
2017-03-09 14:48 ` Niklas Cassel
2017-03-09 6:39 ` [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
` (2 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon, Jingoo Han, Richard Zhu, Lucas Stach,
Murali Karicheri, Thomas Petazzoni, Niklas Cassel,
Jesper Nilsson, Zhou Wang, Gabriele Paoloni
dwc has 2 dbi address space labeled dbics and dbics2. The existing
helper to access dbi address space can access only dbics. However
dbics2 has to be accessed for programming the BAR registers in the
case of EP mode. This is in preparation for adding EP mode support
to dwc driver.
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 10 +++--
drivers/pci/dwc/pci-exynos.c | 10 +++--
drivers/pci/dwc/pci-imx6.c | 62 +++++++++++++++-----------
drivers/pci/dwc/pci-keystone-dw.c | 15 ++++---
drivers/pci/dwc/pcie-armada8k.c | 39 +++++++++-------
drivers/pci/dwc/pcie-artpec6.c | 7 +--
drivers/pci/dwc/pcie-designware-host.c | 20 +++++----
drivers/pci/dwc/pcie-designware.c | 76 ++++++++++++++++++--------------
drivers/pci/dwc/pcie-designware.h | 10 +++--
drivers/pci/dwc/pcie-hisi.c | 17 ++++---
10 files changed, 152 insertions(+), 114 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 07c45ec..3708bd6 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -495,12 +495,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
struct dw_pcie *pci = dra7xx->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
/* clear MSE */
- val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
+ val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
val &= ~PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
+ dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
return 0;
}
@@ -509,12 +510,13 @@ static int dra7xx_pcie_resume(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
struct dw_pcie *pci = dra7xx->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
/* set MSE */
- val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
+ val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
val |= PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
+ dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
return 0;
}
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 993b650..a0d40f7 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -521,23 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
exynos_pcie_msi_init(ep);
}
-static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
+static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg)
{
struct exynos_pcie *ep = to_exynos_pcie(pci);
u32 val;
exynos_pcie_sideband_dbi_r_mode(ep, true);
- val = readl(pci->dbi_base + reg);
+ val = readl(base + reg);
exynos_pcie_sideband_dbi_r_mode(ep, false);
return val;
}
-static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, u32 val)
{
struct exynos_pcie *ep = to_exynos_pcie(pci);
exynos_pcie_sideband_dbi_w_mode(ep, true);
- writel(val, pci->dbi_base + reg);
+ writel(val, base + reg);
exynos_pcie_sideband_dbi_w_mode(ep, false);
}
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 801e46c..85dd901 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -98,12 +98,13 @@ struct imx6_pcie {
static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
u32 max_iterations = 10;
u32 wait_counter = 0;
do {
- val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
wait_counter++;
@@ -119,21 +120,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
int ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -142,6 +144,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 val, phy_ctl;
int ret;
@@ -151,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
/* assert Read signal */
phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
- val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
*data = val & 0xffff;
/* deassert Read signal */
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -169,6 +172,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 var;
int ret;
@@ -179,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
return ret;
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
/* capture data */
var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
@@ -191,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert cap data */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
@@ -200,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* assert wr signal */
var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
/* wait for ack */
ret = pcie_phy_poll_ack(imx6_pcie, 1);
@@ -209,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert wr signal */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
if (ret)
return ret;
- dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
+ dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
return 0;
}
@@ -411,6 +415,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
struct device *dev = pci->dev;
/* check if the link is up or not */
@@ -418,20 +423,22 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
return 0;
dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
return -ETIMEDOUT;
}
static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
struct device *dev = pci->dev;
u32 tmp;
unsigned int retries;
for (retries = 0; retries < 200; retries++) {
- tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_readl_dbi(pci, base,
+ PCIE_LINK_WIDTH_SPEED_CONTROL);
/* Test if the speed change finished. */
if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
return 0;
@@ -454,6 +461,7 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
struct device *dev = pci->dev;
u32 tmp;
int ret;
@@ -463,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* started in Gen2 mode, there is a possibility the devices on the
* bus will not be detected at all. This happens with PCIe switches.
*/
- tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
+ tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
- dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
+ dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
/* Start LTSSM. */
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -478,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
if (imx6_pcie->link_gen == 2) {
/* Allow Gen2 mode after the link is up. */
- tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
+ tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
- dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
+ dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
} else {
dev_info(dev, "Link: Gen2 disabled\n");
}
@@ -490,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* Start Directed Speed Change so the best possible speed both link
* partners support can be negotiated.
*/
- tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
tmp |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+ dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
if (ret) {
@@ -507,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
goto err_reset_phy;
}
- tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
+ tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
return 0;
err_reset_phy:
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
imx6_pcie_reset_phy(imx6_pcie);
return ret;
}
@@ -536,7 +544,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
static int imx6_pcie_link_up(struct dw_pcie *pci)
{
- return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
+ void __iomem *base = pci->dbi_base;
+
+ return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
}
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 6b396f6..7220c04 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -378,6 +378,7 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
struct dw_pcie *pci = ks_pcie->pci;
+ void __iomem *base = pci->dbi_base;
struct pcie_port *pp = &pci->pp;
u32 start = pp->mem->start, end = pp->mem->end;
int i, tr_size;
@@ -385,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
/* Disable BARs for inbound access */
ks_dw_pcie_set_dbi_mode(ks_pcie);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
/* Set outbound translation size per window division */
@@ -482,14 +483,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ void __iomem *base = pci->dbi_base;
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
/* Configure and set up BAR0 */
ks_dw_pcie_set_dbi_mode(ks_pcie);
/* Enable BAR0 */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
@@ -497,7 +499,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
* For BAR0, just setting bus address for inbound writes (MSI) should
* be sufficient. Use physical address to avoid any conflicts.
*/
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
}
/**
@@ -506,8 +508,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
int ks_dw_pcie_link_up(struct dw_pcie *pci)
{
u32 val;
+ void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, DEBUG0);
+ val = dw_pcie_readl_dbi(pci, base, DEBUG0);
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index f110e3b..b2328df 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -73,8 +73,9 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
{
u32 reg;
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
+ void __iomem *base = pci->dbi_base;
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
if ((reg & mask) == mask)
return 1;
@@ -86,47 +87,50 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
{
struct dw_pcie *pci = pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 reg;
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
reg &= ~(PCIE_APP_LTSSM_EN);
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
}
/* Set the device to root complex mode */
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
/* Set the PCIe master AxCache attributes */
- dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
- dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
+ dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
+ ARCACHE_DEFAULT_VALUE);
+ dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
+ AWCACHE_DEFAULT_VALUE);
/* Set the PCIe master AxDomain attributes */
- reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
- reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
/* Enable INT A-D interrupts */
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
if (!dw_pcie_link_up(pci)) {
/* Configuration done. Start LTSSM */
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
reg |= PCIE_APP_LTSSM_EN;
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
}
/* Wait until the link becomes active again */
@@ -147,6 +151,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
{
struct armada8k_pcie *pcie = arg;
struct dw_pcie *pci = pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
/*
@@ -154,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
* PCI device. However, they are also latched into the PCIe
* controller, so we simply discard them.
*/
- val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
+ dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
return IRQ_HANDLED;
}
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5b3b3af..e3ba11c 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -86,6 +86,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
{
struct dw_pcie *pci = artpec6_pcie->pci;
+ void __iomem *base = pci->dbi_base;
struct pcie_port *pp = &pci->pp;
u32 val;
unsigned int retries;
@@ -145,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
* Enable writing to config regs. This is required as the Synopsys
* driver changes the class code. That register needs DBI write enable.
*/
- dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
+ dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
/* setup root complex */
dw_pcie_setup_rc(pp);
@@ -160,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
return 0;
dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
+ dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
return -ETIMEDOUT;
}
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 5ba3349..9df620d 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -566,8 +566,9 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
{
u32 val;
+ void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
if (val == 0xffffffff)
return 1;
@@ -578,31 +579,32 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ void __iomem *base = pci->dbi_base;
dw_pcie_setup(pci);
/* setup RC BARs */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
+ dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
/* setup interrupt pins */
- val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
+ val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
val &= 0xffff00ff;
val |= 0x00000100;
- dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
+ dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
/* setup bus numbers */
- val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
+ val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
val &= 0xff000000;
val |= 0x00010100;
- dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
+ dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
/* setup command register */
- val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
+ val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
+ dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
/*
* If the platform provides ->rd_other_conf, it means the platform
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 14ee7a3..f8eaeea 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -61,75 +61,82 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
return PCIBIOS_SUCCESSFUL;
}
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
+u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
{
if (pci->ops->readl_dbi)
- return pci->ops->readl_dbi(pci, reg);
+ return pci->ops->readl_dbi(pci, base, reg);
- return readl(pci->dbi_base + reg);
+ return readl(base + reg);
}
-void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ u32 val)
{
if (pci->ops->writel_dbi)
- pci->ops->writel_dbi(pci, reg, val);
+ pci->ops->writel_dbi(pci, base, reg, val);
else
- writel(val, pci->dbi_base + reg);
+ writel(val, base + reg);
}
-static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
+static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
+ u32 index, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- return dw_pcie_readl_dbi(pci, offset + reg);
+ return dw_pcie_readl_dbi(pci, base, offset + reg);
}
-static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
- u32 val)
+static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
+ u32 index, u32 reg, u32 val)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- dw_pcie_writel_dbi(pci, offset + reg, val);
+ dw_pcie_writel_dbi(pci, base, offset + reg, val);
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
u64 cpu_addr, u64 pci_addr, u32 size)
{
u32 retries, val;
+ void __iomem *base = pci->dbi_base;
- if (pp->ops->cpu_addr_fixup)
- cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+ if (pci->ops->cpu_addr_fixup)
+ cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
if (pci->iatu_unroll_enabled) {
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
+ dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
lower_32_bits(cpu_addr));
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
+ dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
upper_32_bits(cpu_addr));
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
+ dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
lower_32_bits(cpu_addr + size - 1));
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
+ dw_pcie_writel_unroll(pci, base, index,
+ PCIE_ATU_UNR_LOWER_TARGET,
lower_32_bits(pci_addr));
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
+ dw_pcie_writel_unroll(pci, base, index,
+ PCIE_ATU_UNR_UPPER_TARGET,
upper_32_bits(pci_addr));
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
+ dw_pcie_writel_unroll(pci, base, index,
+ PCIE_ATU_UNR_REGION_CTRL1,
type);
- dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
+ dw_pcie_writel_unroll(pci, base, index,
+ PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
} else {
- dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
PCIE_ATU_REGION_OUTBOUND | index);
- dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
lower_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
upper_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
lower_32_bits(cpu_addr + size - 1));
- dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
lower_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
upper_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
+ dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
}
/*
@@ -138,10 +145,10 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
if (pci->iatu_unroll_enabled)
- val = dw_pcie_readl_unroll(pci, index,
+ val = dw_pcie_readl_unroll(pci, base, index,
PCIE_ATU_UNR_REGION_CTRL2);
else
- val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
if (val == PCIE_ATU_ENABLE)
return;
@@ -188,13 +195,14 @@ void dw_pcie_setup(struct dw_pcie *pci)
u32 lanes;
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
+ void __iomem *base = pci->dbi_base;
ret = of_property_read_u32(np, "num-lanes", &lanes);
if (ret)
lanes = 0;
/* set the number of lanes */
- val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
val &= ~PORT_LINK_MODE_MASK;
switch (lanes) {
case 1:
@@ -213,10 +221,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
return;
}
- dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
+ dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
/* set link width speed control register */
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
switch (lanes) {
case 1:
@@ -232,5 +240,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
break;
}
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 8f3dcb2..fe93f7f 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,8 +144,9 @@ struct pcie_port {
struct dw_pcie_ops {
u64 (*cpu_addr_fixup)(u64 cpu_addr);
- u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
- void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
+ u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
+ void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ u32 val);
int (*link_up)(struct dw_pcie *pcie);
};
@@ -163,8 +164,9 @@ struct dw_pcie {
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
-void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
+u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
+void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index fd66a31..409b54b 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -152,10 +152,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 reg_val;
void *walker = ®_val;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ void __iomem *base = pci->dbi_base;
walker += (where & 0x3);
reg = where & ~0x3;
- reg_val = dw_pcie_readl_dbi(pci, reg);
+ reg_val = dw_pcie_readl_dbi(pci, base, reg);
if (size == 1)
*val = *(u8 __force *) walker;
@@ -177,19 +178,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
u32 reg;
void *walker = ®_val;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ void __iomem *base = pci->dbi_base;
walker += (where & 0x3);
reg = where & ~0x3;
if (size == 4)
- dw_pcie_writel_dbi(pci, reg, val);
+ dw_pcie_writel_dbi(pci, base, reg, val);
else if (size == 2) {
- reg_val = dw_pcie_readl_dbi(pci, reg);
+ reg_val = dw_pcie_readl_dbi(pci, base, reg);
*(u16 __force *) walker = val;
- dw_pcie_writel_dbi(pci, reg, reg_val);
+ dw_pcie_writel_dbi(pci, base, reg, reg_val);
} else if (size == 1) {
- reg_val = dw_pcie_readl_dbi(pci, reg);
+ reg_val = dw_pcie_readl_dbi(pci, base, reg);
*(u8 __force *) walker = val;
- dw_pcie_writel_dbi(pci, reg, reg_val);
+ dw_pcie_writel_dbi(pci, base, reg, reg_val);
} else
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -209,9 +211,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{
struct dw_pcie *pci = hisi_pcie->pci;
+ void __iomem *base = pci->dbi_base;
u32 val;
- val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
+ val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
` (3 preceding siblings ...)
2017-03-09 6:39 ` [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
2017-03-09 14:48 ` Niklas Cassel
2017-03-09 6:39 ` [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I
6 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon, Jingoo Han, Richard Zhu, Lucas Stach,
Murali Karicheri, Thomas Petazzoni, Niklas Cassel,
Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Previously dbi accessors can be used to access data of size 4
bytes. But there might be situations (like accessing
MSI_MESSAGE_CONTROL in order to set/get the number of required
MSI interrupts in EP mode) where dbi accessors must
be used to access data of size 2. This is in preparation for
adding endpoint mode support to designware driver.
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 8 ++--
drivers/pci/dwc/pci-exynos.c | 16 +++----
drivers/pci/dwc/pci-imx6.c | 54 +++++++++++-----------
drivers/pci/dwc/pci-keystone-dw.c | 13 +++---
drivers/pci/dwc/pcie-armada8k.c | 38 ++++++++--------
drivers/pci/dwc/pcie-artpec6.c | 6 +--
drivers/pci/dwc/pcie-designware-host.c | 18 ++++----
drivers/pci/dwc/pcie-designware.c | 77 +++++++++++++++++++-------------
drivers/pci/dwc/pcie-designware.h | 14 +++---
drivers/pci/dwc/pcie-hisi.c | 14 +++---
10 files changed, 138 insertions(+), 120 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 3708bd6..c6fef0a 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -499,9 +499,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
u32 val;
/* clear MSE */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val &= ~PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
return 0;
}
@@ -514,9 +514,9 @@ static int dra7xx_pcie_resume(struct device *dev)
u32 val;
/* set MSE */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val |= PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
return 0;
}
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index a0d40f7..37d6d2b 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -521,25 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
exynos_pcie_msi_init(ep);
}
-static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
- u32 reg)
+static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size)
{
struct exynos_pcie *ep = to_exynos_pcie(pci);
u32 val;
exynos_pcie_sideband_dbi_r_mode(ep, true);
- val = readl(base + reg);
+ dw_pcie_read(base + reg, size, &val);
exynos_pcie_sideband_dbi_r_mode(ep, false);
return val;
}
-static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
- u32 reg, u32 val)
+static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size, u32 val)
{
struct exynos_pcie *ep = to_exynos_pcie(pci);
exynos_pcie_sideband_dbi_w_mode(ep, true);
- writel(val, base + reg);
+ dw_pcie_write(base + reg, size, val);
exynos_pcie_sideband_dbi_w_mode(ep, false);
}
@@ -646,8 +646,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
}
static const struct dw_pcie_ops dw_pcie_ops = {
- .readl_dbi = exynos_pcie_readl_dbi,
- .writel_dbi = exynos_pcie_writel_dbi,
+ .read_dbi = exynos_pcie_read_dbi,
+ .write_dbi = exynos_pcie_write_dbi,
.link_up = exynos_pcie_link_up,
};
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 85dd901..e58ca7a 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -104,7 +104,7 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
u32 wait_counter = 0;
do {
- val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
wait_counter++;
@@ -125,17 +125,17 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
int ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -154,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
/* assert Read signal */
phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, phy_ctl);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
- val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
*data = val & 0xffff;
/* deassert Read signal */
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x00);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -183,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
return ret;
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* capture data */
var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
@@ -195,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert cap data */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
@@ -204,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* assert wr signal */
var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack */
ret = pcie_phy_poll_ack(imx6_pcie, 1);
@@ -213,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert wr signal */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
if (ret)
return ret;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x0);
return 0;
}
@@ -423,8 +423,8 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
return 0;
dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
return -ETIMEDOUT;
}
@@ -437,8 +437,8 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
unsigned int retries;
for (retries = 0; retries < 200; retries++) {
- tmp = dw_pcie_readl_dbi(pci, base,
- PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_read_dbi(pci, base,
+ PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
/* Test if the speed change finished. */
if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
return 0;
@@ -471,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* started in Gen2 mode, there is a possibility the devices on the
* bus will not be detected at all. This happens with PCIe switches.
*/
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
- dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
/* Start LTSSM. */
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -486,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
if (imx6_pcie->link_gen == 2) {
/* Allow Gen2 mode after the link is up. */
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
- dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
} else {
dev_info(dev, "Link: Gen2 disabled\n");
}
@@ -498,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* Start Directed Speed Change so the best possible speed both link
* partners support can be negotiated.
*/
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
tmp |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, tmp);
ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
if (ret) {
@@ -515,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
goto err_reset_phy;
}
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCSR, 0x4);
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
return 0;
err_reset_phy:
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
imx6_pcie_reset_phy(imx6_pcie);
return ret;
}
@@ -546,7 +546,7 @@ static int imx6_pcie_link_up(struct dw_pcie *pci)
{
void __iomem *base = pci->dbi_base;
- return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
+ return dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4) &
PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
}
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 7220c04..8318efe 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -386,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
/* Disable BARs for inbound access */
ks_dw_pcie_set_dbi_mode(ks_pcie);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
/* Set outbound translation size per window division */
@@ -490,8 +490,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
ks_dw_pcie_set_dbi_mode(ks_pcie);
/* Enable BAR0 */
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 1);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, SZ_4K - 1);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
@@ -499,7 +499,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
* For BAR0, just setting bus address for inbound writes (MSI) should
* be sufficient. Use physical address to avoid any conflicts.
*/
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4,
+ ks_pcie->app.start);
}
/**
@@ -510,7 +511,7 @@ int ks_dw_pcie_link_up(struct dw_pcie *pci)
u32 val;
void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, base, DEBUG0);
+ val = dw_pcie_read_dbi(pci, base, DEBUG0, 0x4);
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index b2328df..447d178 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -75,7 +75,7 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
void __iomem *base = pci->dbi_base;
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_STATUS_REG, 0x4);
if ((reg & mask) == mask)
return 1;
@@ -92,45 +92,45 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg &= ~(PCIE_APP_LTSSM_EN);
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
}
/* Set the device to root complex mode */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
/* Set the PCIe master AxCache attributes */
- dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
- ARCACHE_DEFAULT_VALUE);
- dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
- AWCACHE_DEFAULT_VALUE);
+ dw_pcie_write_dbi(pci, base, PCIE_ARCACHE_TRC_REG, 0x4,
+ ARCACHE_DEFAULT_VALUE);
+ dw_pcie_write_dbi(pci, base, PCIE_AWCACHE_TRC_REG, 0x4,
+ AWCACHE_DEFAULT_VALUE);
/* Set the PCIe master AxDomain attributes */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_ARUSER_REG, 0x4);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_ARUSER_REG, 0x4, reg);
- reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_AWUSER_REG, 0x4);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_AWUSER_REG, 0x4, reg);
/* Enable INT A-D interrupts */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4);
reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4, reg);
if (!dw_pcie_link_up(pci)) {
/* Configuration done. Start LTSSM */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg |= PCIE_APP_LTSSM_EN;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
}
/* Wait until the link becomes active again */
@@ -159,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
* PCI device. However, they are also latched into the PCIe
* controller, so we simply discard them.
*/
- val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ val = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4, val);
return IRQ_HANDLED;
}
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index e3ba11c..0829de4 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -146,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
* Enable writing to config regs. This is required as the Synopsys
* driver changes the class code. That register needs DBI write enable.
*/
- dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
+ dw_pcie_write_dbi(pci, base, MISC_CONTROL_1_OFF, 0x4, DBI_RO_WR_EN);
/* setup root complex */
dw_pcie_setup_rc(pp);
@@ -161,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
return 0;
dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
return -ETIMEDOUT;
}
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 9df620d..3150d33 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -568,7 +568,7 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
u32 val;
void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4);
if (val == 0xffffffff)
return 1;
@@ -584,27 +584,27 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_setup(pci);
/* setup RC BARs */
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0x00000004);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0x00000000);
/* setup interrupt pins */
- val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
+ val = dw_pcie_read_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4);
val &= 0xffff00ff;
val |= 0x00000100;
- dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
+ dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, val);
/* setup bus numbers */
- val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
+ val = dw_pcie_read_dbi(pci, base, PCI_PRIMARY_BUS, 0x4);
val &= 0xff000000;
val |= 0x00010100;
- dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
+ dw_pcie_write_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, val);
/* setup command register */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
/*
* If the platform provides ->rd_other_conf, it means the platform
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index f8eaeea..557ee53 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
return PCIBIOS_SUCCESSFUL;
}
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
+u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size)
{
- if (pci->ops->readl_dbi)
- return pci->ops->readl_dbi(pci, base, reg);
+ int ret;
+ u32 val;
+
+ if (pci->ops->read_dbi)
+ return pci->ops->read_dbi(pci, base, reg, size);
- return readl(base + reg);
+ ret = dw_pcie_read(base + reg, size, &val);
+ if (ret)
+ dev_err(pci->dev, "read DBI address failed\n");
+
+ return val;
}
-void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
- u32 val)
+void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size, u32 val)
{
- if (pci->ops->writel_dbi)
- pci->ops->writel_dbi(pci, base, reg, val);
- else
- writel(val, base + reg);
+ int ret;
+
+ if (pci->ops->write_dbi) {
+ pci->ops->write_dbi(pci, base, reg, size, val);
+ return;
+ }
+
+ ret = dw_pcie_write(base + reg, size, val);
+ if (ret)
+ dev_err(pci->dev, "write DBI address failed\n");
}
static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
@@ -83,7 +97,7 @@ static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- return dw_pcie_readl_dbi(pci, base, offset + reg);
+ return dw_pcie_read_dbi(pci, base, offset + reg, 0x4);
}
static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
@@ -91,7 +105,7 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- dw_pcie_writel_dbi(pci, base, offset + reg, val);
+ dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
@@ -123,20 +137,21 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
} else {
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
- PCIE_ATU_REGION_OUTBOUND | index);
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
- lower_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
- upper_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
- lower_32_bits(cpu_addr + size - 1));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
- lower_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
- upper_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
+ PCIE_ATU_REGION_OUTBOUND | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
+ lower_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
+ upper_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
+ lower_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
+ upper_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
+ PCIE_ATU_ENABLE);
}
/*
@@ -148,7 +163,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
val = dw_pcie_readl_unroll(pci, base, index,
PCIE_ATU_UNR_REGION_CTRL2);
else
- val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
+ val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
if (val == PCIE_ATU_ENABLE)
return;
@@ -202,7 +217,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
lanes = 0;
/* set the number of lanes */
- val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4);
val &= ~PORT_LINK_MODE_MASK;
switch (lanes) {
case 1:
@@ -221,10 +236,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
return;
}
- dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, val);
/* set link width speed control register */
- val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
switch (lanes) {
case 1:
@@ -240,5 +255,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
break;
}
- dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, val);
}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index fe93f7f..74df063 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,9 +144,10 @@ struct pcie_port {
struct dw_pcie_ops {
u64 (*cpu_addr_fixup)(u64 cpu_addr);
- u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
- void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
- u32 val);
+ u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ size_t size);
+ void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ size_t size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
};
@@ -164,9 +165,10 @@ struct dw_pcie {
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
-void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
- u32 val);
+u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size);
+void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index 409b54b..cc04381 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -156,7 +156,7 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
walker += (where & 0x3);
reg = where & ~0x3;
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
if (size == 1)
*val = *(u8 __force *) walker;
@@ -183,15 +183,15 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
walker += (where & 0x3);
reg = where & ~0x3;
if (size == 4)
- dw_pcie_writel_dbi(pci, base, reg, val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, val);
else if (size == 2) {
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
*(u16 __force *) walker = val;
- dw_pcie_writel_dbi(pci, base, reg, reg_val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
} else if (size == 1) {
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
*(u8 __force *) walker = val;
- dw_pcie_writel_dbi(pci, base, reg, reg_val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
} else
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -214,7 +214,7 @@ static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
void __iomem *base = pci->dbi_base;
u32 val;
- val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
+ val = dw_pcie_read_dbi(pci, base, PCIE_SYS_STATE4, 0x4);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
` (4 preceding siblings ...)
2017-03-09 6:39 ` [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
2017-03-09 12:25 ` Joao Pinto
2017-03-09 6:39 ` [RESEND PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I
6 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll
to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
functions are used to perform only outbound configurations. Also move
these _unroll configurations to a separate function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 112 ++++++++++++++++++++++---------------
1 file changed, 67 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 557ee53..6657a84 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -92,22 +92,64 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
dev_err(pci->dev, "write DBI address failed\n");
}
-static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
- u32 index, u32 reg)
+static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, void __iomem *base,
+ u32 index, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
return dw_pcie_read_dbi(pci, base, offset + reg, 0x4);
}
-static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
- u32 index, u32 reg, u32 val)
+static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, void __iomem *base,
+ u32 index, u32 reg, u32 val)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
}
+void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type,
+ u64 cpu_addr, u64 pci_addr, u32 size)
+{
+ u32 retries, val;
+ void __iomem *base = pci->dbi_base;
+
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_LOWER_BASE,
+ lower_32_bits(cpu_addr));
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_UPPER_BASE,
+ upper_32_bits(cpu_addr));
+ dw_pcie_writel_ob_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_LOWER_TARGET,
+ lower_32_bits(pci_addr));
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_UPPER_TARGET,
+ upper_32_bits(pci_addr));
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_REGION_CTRL1,
+ type);
+ dw_pcie_writel_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_REGION_CTRL2,
+ PCIE_ATU_ENABLE);
+
+ /*
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
+ */
+ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+ val = dw_pcie_readl_ob_unroll(pci, base, index,
+ PCIE_ATU_UNR_REGION_CTRL2);
+ if (val & PCIE_ATU_ENABLE)
+ return;
+
+ usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ }
+ dev_err(pci->dev, "outbound iATU is not being enabled\n");
+}
+
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
u64 cpu_addr, u64 pci_addr, u32 size)
{
@@ -118,59 +160,39 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
if (pci->iatu_unroll_enabled) {
- dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
- lower_32_bits(cpu_addr));
- dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
- upper_32_bits(cpu_addr));
- dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
- lower_32_bits(cpu_addr + size - 1));
- dw_pcie_writel_unroll(pci, base, index,
- PCIE_ATU_UNR_LOWER_TARGET,
- lower_32_bits(pci_addr));
- dw_pcie_writel_unroll(pci, base, index,
- PCIE_ATU_UNR_UPPER_TARGET,
- upper_32_bits(pci_addr));
- dw_pcie_writel_unroll(pci, base, index,
- PCIE_ATU_UNR_REGION_CTRL1,
- type);
- dw_pcie_writel_unroll(pci, base, index,
- PCIE_ATU_UNR_REGION_CTRL2,
- PCIE_ATU_ENABLE);
- } else {
- dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
- PCIE_ATU_REGION_OUTBOUND | index);
- dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
- lower_32_bits(cpu_addr));
- dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
- upper_32_bits(cpu_addr));
- dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
- lower_32_bits(cpu_addr + size - 1));
- dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
- lower_32_bits(pci_addr));
- dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
- upper_32_bits(pci_addr));
- dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
- dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
- PCIE_ATU_ENABLE);
+ dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
+ pci_addr, size);
+ return;
}
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
+ PCIE_ATU_REGION_OUTBOUND | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
+ lower_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
+ upper_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
+ lower_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
+ upper_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
+ PCIE_ATU_ENABLE);
+
/*
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
- if (pci->iatu_unroll_enabled)
- val = dw_pcie_readl_unroll(pci, base, index,
- PCIE_ATU_UNR_REGION_CTRL2);
- else
- val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
-
+ val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
if (val == PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
}
- dev_err(pci->dev, "iATU is not being enabled\n");
+ dev_err(pci->dev, "outbound iATU is not being enabled\n");
}
int dw_pcie_wait_for_link(struct dw_pcie *pci)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RESEND PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
` (5 preceding siblings ...)
2017-03-09 6:39 ` [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Kishon Vijay Abraham I
@ 2017-03-09 6:39 ` Kishon Vijay Abraham I
6 siblings, 0 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-09 6:39 UTC (permalink / raw)
To: Bjorn Helgaas, Joao Pinto, linux-pci, linux-kernel, linux-omap,
linux-arm-kernel
Cc: nsekhar, kishon, Keerthy
From: Keerthy <j-keerthy@ti.com>
Currently devm_request_irq is being called before base, pci fields
of dra7xx_pcie structure are populated. It is called even before
pm_runtime_enable and pm_runtime_get_sync are called. This will
lead to exceptions if in case an interrupt is triggered before
the all of the above are done. Hence push the devm_request_irq
call to the end of the probe.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index c6fef0a..8c53233 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -410,13 +410,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
return -EINVAL;
}
- ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
- IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
- if (ret) {
- dev_err(dev, "failed to request irq\n");
- return ret;
- }
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
base = devm_ioremap_nocache(dev, res->start, resource_size(res));
if (!base)
@@ -478,6 +471,13 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
if (ret < 0)
goto err_gpio;
+ ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
+ IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
+ if (ret) {
+ dev_err(dev, "failed to request irq\n");
+ goto err_gpio;
+ }
+
return 0;
err_gpio:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops
2017-03-09 6:39 ` [RESEND PATCH v3 3/7] PCI: dwc: artpec6: " Kishon Vijay Abraham I
@ 2017-03-09 10:21 ` Niklas Cassel
0 siblings, 0 replies; 24+ messages in thread
From: Niklas Cassel @ 2017-03-09 10:21 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar
Acked-by: Niklas Cassel <niklas.cassel@axis.com>
On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
> Populate cpu_addr_fixup ops to extract the least 28 bits of the
> corresponding cpu address.
>
> Cc: Niklas Cassel <niklas.cassel@axis.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-artpec6.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
> index fcd3ef8..5b3b3af 100644
> --- a/drivers/pci/dwc/pcie-artpec6.c
> +++ b/drivers/pci/dwc/pcie-artpec6.c
> @@ -78,6 +78,11 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
> regmap_write(artpec6_pcie->regmap, offset, val);
> }
>
> +static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
> +{
> + return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
> +}
> +
> static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> {
> struct dw_pcie *pci = artpec6_pcie->pci;
> @@ -142,11 +147,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> */
> dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>
> - pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
> - pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
> - pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
> - pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
> -
> /* setup root complex */
> dw_pcie_setup_rc(pp);
>
> @@ -234,6 +234,10 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
> return 0;
> }
>
> +static const struct dw_pcie_ops dw_pcie_ops = {
> + .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
> +};
> +
> static int artpec6_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> pci->dev = dev;
> + pci->ops = &dw_pcie_ops;
>
> artpec6_pcie->pci = pci;
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function
2017-03-09 6:39 ` [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Kishon Vijay Abraham I
@ 2017-03-09 12:25 ` Joao Pinto
0 siblings, 0 replies; 24+ messages in thread
From: Joao Pinto @ 2017-03-09 12:25 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar
Às 6:39 AM de 3/9/2017, Kishon Vijay Abraham I escreveu:
> No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll
> to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
> functions are used to perform only outbound configurations. Also move
> these _unroll configurations to a separate function.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 112 ++++++++++++++++++++++---------------
> 1 file changed, 67 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 557ee53..6657a84 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -92,22 +92,64 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> dev_err(pci->dev, "write DBI address failed\n");
> }
>
> -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
> - u32 index, u32 reg)
> +static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, void __iomem *base,
> + u32 index, u32 reg)
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> return dw_pcie_read_dbi(pci, base, offset + reg, 0x4);
> }
>
> -static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
> - u32 index, u32 reg, u32 val)
> +static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, void __iomem *base,
> + u32 index, u32 reg, u32 val)
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> }
>
> +void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type,
> + u64 cpu_addr, u64 pci_addr, u32 size)
> +{
> + u32 retries, val;
> + void __iomem *base = pci->dbi_base;
> +
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_LOWER_BASE,
> + lower_32_bits(cpu_addr));
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_UPPER_BASE,
> + upper_32_bits(cpu_addr));
> + dw_pcie_writel_ob_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
> + lower_32_bits(cpu_addr + size - 1));
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_LOWER_TARGET,
> + lower_32_bits(pci_addr));
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_UPPER_TARGET,
> + upper_32_bits(pci_addr));
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_REGION_CTRL1,
> + type);
> + dw_pcie_writel_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_REGION_CTRL2,
> + PCIE_ATU_ENABLE);
> +
> + /*
> + * Make sure ATU enable takes effect before any subsequent config
> + * and I/O accesses.
> + */
> + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> + val = dw_pcie_readl_ob_unroll(pci, base, index,
> + PCIE_ATU_UNR_REGION_CTRL2);
> + if (val & PCIE_ATU_ENABLE)
> + return;
> +
> + usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> + }
> + dev_err(pci->dev, "outbound iATU is not being enabled\n");
> +}
> +
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> u64 cpu_addr, u64 pci_addr, u32 size)
> {
> @@ -118,59 +160,39 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
>
> if (pci->iatu_unroll_enabled) {
> - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
> - lower_32_bits(cpu_addr));
> - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
> - upper_32_bits(cpu_addr));
> - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
> - lower_32_bits(cpu_addr + size - 1));
> - dw_pcie_writel_unroll(pci, base, index,
> - PCIE_ATU_UNR_LOWER_TARGET,
> - lower_32_bits(pci_addr));
> - dw_pcie_writel_unroll(pci, base, index,
> - PCIE_ATU_UNR_UPPER_TARGET,
> - upper_32_bits(pci_addr));
> - dw_pcie_writel_unroll(pci, base, index,
> - PCIE_ATU_UNR_REGION_CTRL1,
> - type);
> - dw_pcie_writel_unroll(pci, base, index,
> - PCIE_ATU_UNR_REGION_CTRL2,
> - PCIE_ATU_ENABLE);
> - } else {
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
> - PCIE_ATU_REGION_OUTBOUND | index);
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
> - lower_32_bits(cpu_addr));
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
> - upper_32_bits(cpu_addr));
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
> - lower_32_bits(cpu_addr + size - 1));
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
> - lower_32_bits(pci_addr));
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
> - upper_32_bits(pci_addr));
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
> - dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
> - PCIE_ATU_ENABLE);
> + dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
> + pci_addr, size);
> + return;
> }
>
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
> + PCIE_ATU_REGION_OUTBOUND | index);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
> + lower_32_bits(cpu_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
> + upper_32_bits(cpu_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
> + lower_32_bits(cpu_addr + size - 1));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
> + lower_32_bits(pci_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
> + upper_32_bits(pci_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
> + PCIE_ATU_ENABLE);
> +
> /*
> * Make sure ATU enable takes effect before any subsequent config
> * and I/O accesses.
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> - if (pci->iatu_unroll_enabled)
> - val = dw_pcie_readl_unroll(pci, base, index,
> - PCIE_ATU_UNR_REGION_CTRL2);
> - else
> - val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
> -
> + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
> if (val == PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> }
> - dev_err(pci->dev, "iATU is not being enabled\n");
> + dev_err(pci->dev, "outbound iATU is not being enabled\n");
> }
>
> int dw_pcie_wait_for_link(struct dw_pcie *pci)
>
Acked-By: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-09 6:39 ` [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
@ 2017-03-09 14:48 ` Niklas Cassel
2017-03-09 15:05 ` Niklas Cassel
0 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-09 14:48 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
> dwc has 2 dbi address space labeled dbics and dbics2. The existing
> helper to access dbi address space can access only dbics. However
> dbics2 has to be accessed for programming the BAR registers in the
> case of EP mode. This is in preparation for adding EP mode support
> to dwc driver.
Hello Kishon
I don't really like the idea of adding an extra argument to every existing read/write.
Will not a read/write using dbi2 be quite uncommon compared to a read/write
using dbi?
How about something like this:
void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
{
if (pci->ops->writel_dbi)
pci->ops->writel_dbi(pci, base, reg, val);
else
writel(val, base + reg);
}
#define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
#define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
That way we don't have to change every existing read/write.
I'm assuming that synopsys won't add a dbi3 in the next version of the IP :p
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Murali Karicheri <m-karicheri2@ti.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Niklas Cassel <niklas.cassel@axis.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>
> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pci-dra7xx.c | 10 +++--
> drivers/pci/dwc/pci-exynos.c | 10 +++--
> drivers/pci/dwc/pci-imx6.c | 62 +++++++++++++++-----------
> drivers/pci/dwc/pci-keystone-dw.c | 15 ++++---
> drivers/pci/dwc/pcie-armada8k.c | 39 +++++++++-------
> drivers/pci/dwc/pcie-artpec6.c | 7 +--
> drivers/pci/dwc/pcie-designware-host.c | 20 +++++----
> drivers/pci/dwc/pcie-designware.c | 76 ++++++++++++++++++--------------
> drivers/pci/dwc/pcie-designware.h | 10 +++--
> drivers/pci/dwc/pcie-hisi.c | 17 ++++---
> 10 files changed, 152 insertions(+), 114 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index 07c45ec..3708bd6 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -495,12 +495,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
> {
> struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
> struct dw_pcie *pci = dra7xx->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
>
> /* clear MSE */
> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> val &= ~PCI_COMMAND_MEMORY;
> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>
> return 0;
> }
> @@ -509,12 +510,13 @@ static int dra7xx_pcie_resume(struct device *dev)
> {
> struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
> struct dw_pcie *pci = dra7xx->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
>
> /* set MSE */
> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> val |= PCI_COMMAND_MEMORY;
> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>
> return 0;
> }
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index 993b650..a0d40f7 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -521,23 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
> exynos_pcie_msi_init(ep);
> }
>
> -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> +static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg)
> {
> struct exynos_pcie *ep = to_exynos_pcie(pci);
> u32 val;
>
> exynos_pcie_sideband_dbi_r_mode(ep, true);
> - val = readl(pci->dbi_base + reg);
> + val = readl(base + reg);
> exynos_pcie_sideband_dbi_r_mode(ep, false);
> return val;
> }
>
> -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> +static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, u32 val)
> {
> struct exynos_pcie *ep = to_exynos_pcie(pci);
>
> exynos_pcie_sideband_dbi_w_mode(ep, true);
> - writel(val, pci->dbi_base + reg);
> + writel(val, base + reg);
> exynos_pcie_sideband_dbi_w_mode(ep, false);
> }
>
> diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
> index 801e46c..85dd901 100644
> --- a/drivers/pci/dwc/pci-imx6.c
> +++ b/drivers/pci/dwc/pci-imx6.c
> @@ -98,12 +98,13 @@ struct imx6_pcie {
> static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
> u32 max_iterations = 10;
> u32 wait_counter = 0;
>
> do {
> - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
> val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
> wait_counter++;
>
> @@ -119,21 +120,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
> static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
> int ret;
>
> val = addr << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>
> val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> return ret;
>
> val = addr << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>
> return pcie_phy_poll_ack(imx6_pcie, 0);
> }
> @@ -142,6 +144,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
> static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val, phy_ctl;
> int ret;
>
> @@ -151,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
>
> /* assert Read signal */
> phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> return ret;
>
> - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
> *data = val & 0xffff;
>
> /* deassert Read signal */
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
>
> return pcie_phy_poll_ack(imx6_pcie, 0);
> }
> @@ -169,6 +172,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
> static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 var;
> int ret;
>
> @@ -179,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
> return ret;
>
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>
> /* capture data */
> var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> @@ -191,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* deassert cap data */
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>
> /* wait for ack de-assertion */
> ret = pcie_phy_poll_ack(imx6_pcie, 0);
> @@ -200,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* assert wr signal */
> var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>
> /* wait for ack */
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> @@ -209,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* deassert wr signal */
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>
> /* wait for ack de-assertion */
> ret = pcie_phy_poll_ack(imx6_pcie, 0);
> if (ret)
> return ret;
>
> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
>
> return 0;
> }
> @@ -411,6 +415,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> struct device *dev = pci->dev;
>
> /* check if the link is up or not */
> @@ -418,20 +423,22 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
> return 0;
>
> dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
> return -ETIMEDOUT;
> }
>
> static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> struct device *dev = pci->dev;
> u32 tmp;
> unsigned int retries;
>
> for (retries = 0; retries < 200; retries++) {
> - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + tmp = dw_pcie_readl_dbi(pci, base,
> + PCIE_LINK_WIDTH_SPEED_CONTROL);
> /* Test if the speed change finished. */
> if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
> return 0;
> @@ -454,6 +461,7 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
> static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> struct device *dev = pci->dev;
> u32 tmp;
> int ret;
> @@ -463,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> * started in Gen2 mode, there is a possibility the devices on the
> * bus will not be detected at all. This happens with PCIe switches.
> */
> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
> - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
> + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
>
> /* Start LTSSM. */
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> @@ -478,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>
> if (imx6_pcie->link_gen == 2) {
> /* Allow Gen2 mode after the link is up. */
> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
> - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
> + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
> } else {
> dev_info(dev, "Link: Gen2 disabled\n");
> }
> @@ -490,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> * Start Directed Speed Change so the best possible speed both link
> * partners support can be negotiated.
> */
> - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
> tmp |= PORT_LOGIC_SPEED_CHANGE;
> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
> + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
>
> ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
> if (ret) {
> @@ -507,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> goto err_reset_phy;
> }
>
> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
> dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
> return 0;
>
> err_reset_phy:
> dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
> imx6_pcie_reset_phy(imx6_pcie);
> return ret;
> }
> @@ -536,7 +544,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
>
> static int imx6_pcie_link_up(struct dw_pcie *pci)
> {
> - return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
> + void __iomem *base = pci->dbi_base;
> +
> + return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
> PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
> }
>
> diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
> index 6b396f6..7220c04 100644
> --- a/drivers/pci/dwc/pci-keystone-dw.c
> +++ b/drivers/pci/dwc/pci-keystone-dw.c
> @@ -378,6 +378,7 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
> void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
> {
> struct dw_pcie *pci = ks_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> struct pcie_port *pp = &pci->pp;
> u32 start = pp->mem->start, end = pp->mem->end;
> int i, tr_size;
> @@ -385,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>
> /* Disable BARs for inbound access */
> ks_dw_pcie_set_dbi_mode(ks_pcie);
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>
> /* Set outbound translation size per window division */
> @@ -482,14 +483,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + void __iomem *base = pci->dbi_base;
> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>
> /* Configure and set up BAR0 */
> ks_dw_pcie_set_dbi_mode(ks_pcie);
>
> /* Enable BAR0 */
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
>
> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>
> @@ -497,7 +499,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> * For BAR0, just setting bus address for inbound writes (MSI) should
> * be sufficient. Use physical address to avoid any conflicts.
> */
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
> }
>
> /**
> @@ -506,8 +508,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> int ks_dw_pcie_link_up(struct dw_pcie *pci)
> {
> u32 val;
> + void __iomem *base = pci->dbi_base;
>
> - val = dw_pcie_readl_dbi(pci, DEBUG0);
> + val = dw_pcie_readl_dbi(pci, base, DEBUG0);
> return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
> }
>
> diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
> index f110e3b..b2328df 100644
> --- a/drivers/pci/dwc/pcie-armada8k.c
> +++ b/drivers/pci/dwc/pcie-armada8k.c
> @@ -73,8 +73,9 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
> {
> u32 reg;
> u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
> + void __iomem *base = pci->dbi_base;
>
> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
>
> if ((reg & mask) == mask)
> return 1;
> @@ -86,47 +87,50 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
> static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
> {
> struct dw_pcie *pci = pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 reg;
>
> if (!dw_pcie_link_up(pci)) {
> /* Disable LTSSM state machine to enable configuration */
> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> reg &= ~(PCIE_APP_LTSSM_EN);
> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
> }
>
> /* Set the device to root complex mode */
> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
> reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
>
> /* Set the PCIe master AxCache attributes */
> - dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
> - dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
> + dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
> + ARCACHE_DEFAULT_VALUE);
> + dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
> + AWCACHE_DEFAULT_VALUE);
>
> /* Set the PCIe master AxDomain attributes */
> - reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
> - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
>
> - reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
> - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
>
> /* Enable INT A-D interrupts */
> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
> reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
> PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
>
> if (!dw_pcie_link_up(pci)) {
> /* Configuration done. Start LTSSM */
> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> reg |= PCIE_APP_LTSSM_EN;
> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
> }
>
> /* Wait until the link becomes active again */
> @@ -147,6 +151,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
> {
> struct armada8k_pcie *pcie = arg;
> struct dw_pcie *pci = pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
>
> /*
> @@ -154,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
> * PCI device. However, they are also latched into the PCIe
> * controller, so we simply discard them.
> */
> - val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
>
> return IRQ_HANDLED;
> }
> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
> index 5b3b3af..e3ba11c 100644
> --- a/drivers/pci/dwc/pcie-artpec6.c
> +++ b/drivers/pci/dwc/pcie-artpec6.c
> @@ -86,6 +86,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
> static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> {
> struct dw_pcie *pci = artpec6_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> struct pcie_port *pp = &pci->pp;
> u32 val;
> unsigned int retries;
> @@ -145,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> * Enable writing to config regs. This is required as the Synopsys
> * driver changes the class code. That register needs DBI write enable.
> */
> - dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
> + dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>
> /* setup root complex */
> dw_pcie_setup_rc(pp);
> @@ -160,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> return 0;
>
> dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
>
> return -ETIMEDOUT;
> }
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index 5ba3349..9df620d 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -566,8 +566,9 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
> {
> u32 val;
> + void __iomem *base = pci->dbi_base;
>
> - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
> if (val == 0xffffffff)
> return 1;
>
> @@ -578,31 +579,32 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> {
> u32 val;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + void __iomem *base = pci->dbi_base;
>
> dw_pcie_setup(pci);
>
> /* setup RC BARs */
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
>
> /* setup interrupt pins */
> - val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
> + val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
> val &= 0xffff00ff;
> val |= 0x00000100;
> - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
> + dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
>
> /* setup bus numbers */
> - val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
> + val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
> val &= 0xff000000;
> val |= 0x00010100;
> - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
> + dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
>
> /* setup command register */
> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> val &= 0xffff0000;
> val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>
> /*
> * If the platform provides ->rd_other_conf, it means the platform
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 14ee7a3..f8eaeea 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -61,75 +61,82 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
> return PCIBIOS_SUCCESSFUL;
> }
>
> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
> {
> if (pci->ops->readl_dbi)
> - return pci->ops->readl_dbi(pci, reg);
> + return pci->ops->readl_dbi(pci, base, reg);
>
> - return readl(pci->dbi_base + reg);
> + return readl(base + reg);
> }
>
> -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + u32 val)
> {
> if (pci->ops->writel_dbi)
> - pci->ops->writel_dbi(pci, reg, val);
> + pci->ops->writel_dbi(pci, base, reg, val);
> else
> - writel(val, pci->dbi_base + reg);
> + writel(val, base + reg);
> }
>
> -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
> +static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
> + u32 index, u32 reg)
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> - return dw_pcie_readl_dbi(pci, offset + reg);
> + return dw_pcie_readl_dbi(pci, base, offset + reg);
> }
>
> -static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
> - u32 val)
> +static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
> + u32 index, u32 reg, u32 val)
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> - dw_pcie_writel_dbi(pci, offset + reg, val);
> + dw_pcie_writel_dbi(pci, base, offset + reg, val);
> }
>
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> u64 cpu_addr, u64 pci_addr, u32 size)
> {
> u32 retries, val;
> + void __iomem *base = pci->dbi_base;
>
> - if (pp->ops->cpu_addr_fixup)
> - cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
> + if (pci->ops->cpu_addr_fixup)
> + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
>
> if (pci->iatu_unroll_enabled) {
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
> lower_32_bits(cpu_addr));
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
> upper_32_bits(cpu_addr));
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
> lower_32_bits(cpu_addr + size - 1));
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
> + dw_pcie_writel_unroll(pci, base, index,
> + PCIE_ATU_UNR_LOWER_TARGET,
> lower_32_bits(pci_addr));
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
> + dw_pcie_writel_unroll(pci, base, index,
> + PCIE_ATU_UNR_UPPER_TARGET,
> upper_32_bits(pci_addr));
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> + dw_pcie_writel_unroll(pci, base, index,
> + PCIE_ATU_UNR_REGION_CTRL1,
> type);
> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
> + dw_pcie_writel_unroll(pci, base, index,
> + PCIE_ATU_UNR_REGION_CTRL2,
> PCIE_ATU_ENABLE);
> } else {
> - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
> PCIE_ATU_REGION_OUTBOUND | index);
> - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
> lower_32_bits(cpu_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
> upper_32_bits(cpu_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
> lower_32_bits(cpu_addr + size - 1));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
> lower_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
> upper_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> }
>
> /*
> @@ -138,10 +145,10 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> if (pci->iatu_unroll_enabled)
> - val = dw_pcie_readl_unroll(pci, index,
> + val = dw_pcie_readl_unroll(pci, base, index,
> PCIE_ATU_UNR_REGION_CTRL2);
> else
> - val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
>
> if (val == PCIE_ATU_ENABLE)
> return;
> @@ -188,13 +195,14 @@ void dw_pcie_setup(struct dw_pcie *pci)
> u32 lanes;
> struct device *dev = pci->dev;
> struct device_node *np = dev->of_node;
> + void __iomem *base = pci->dbi_base;
>
> ret = of_property_read_u32(np, "num-lanes", &lanes);
> if (ret)
> lanes = 0;
>
> /* set the number of lanes */
> - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
> val &= ~PORT_LINK_MODE_MASK;
> switch (lanes) {
> case 1:
> @@ -213,10 +221,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
> dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
> return;
> }
> - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> + dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
>
> /* set link width speed control register */
> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
> val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> switch (lanes) {
> case 1:
> @@ -232,5 +240,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> break;
> }
> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> }
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index 8f3dcb2..fe93f7f 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -144,8 +144,9 @@ struct pcie_port {
>
> struct dw_pcie_ops {
> u64 (*cpu_addr_fixup)(u64 cpu_addr);
> - u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
> - void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
> + u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
> + void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> + u32 val);
> int (*link_up)(struct dw_pcie *pcie);
> };
>
> @@ -163,8 +164,9 @@ struct dw_pcie {
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>
> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
> -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + u32 val);
> int dw_pcie_link_up(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
> index fd66a31..409b54b 100644
> --- a/drivers/pci/dwc/pcie-hisi.c
> +++ b/drivers/pci/dwc/pcie-hisi.c
> @@ -152,10 +152,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
> u32 reg_val;
> void *walker = ®_val;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + void __iomem *base = pci->dbi_base;
>
> walker += (where & 0x3);
> reg = where & ~0x3;
> - reg_val = dw_pcie_readl_dbi(pci, reg);
> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
>
> if (size == 1)
> *val = *(u8 __force *) walker;
> @@ -177,19 +178,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
> u32 reg;
> void *walker = ®_val;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + void __iomem *base = pci->dbi_base;
>
> walker += (where & 0x3);
> reg = where & ~0x3;
> if (size == 4)
> - dw_pcie_writel_dbi(pci, reg, val);
> + dw_pcie_writel_dbi(pci, base, reg, val);
> else if (size == 2) {
> - reg_val = dw_pcie_readl_dbi(pci, reg);
> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
> *(u16 __force *) walker = val;
> - dw_pcie_writel_dbi(pci, reg, reg_val);
> + dw_pcie_writel_dbi(pci, base, reg, reg_val);
> } else if (size == 1) {
> - reg_val = dw_pcie_readl_dbi(pci, reg);
> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
> *(u8 __force *) walker = val;
> - dw_pcie_writel_dbi(pci, reg, reg_val);
> + dw_pcie_writel_dbi(pci, base, reg, reg_val);
> } else
> return PCIBIOS_BAD_REGISTER_NUMBER;
>
> @@ -209,9 +211,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
> static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
> {
> struct dw_pcie *pci = hisi_pcie->pci;
> + void __iomem *base = pci->dbi_base;
> u32 val;
>
> - val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
> + val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
>
> return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
> }
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-09 6:39 ` [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
@ 2017-03-09 14:48 ` Niklas Cassel
2017-03-10 12:04 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-09 14:48 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
> Previously dbi accessors can be used to access data of size 4
> bytes. But there might be situations (like accessing
> MSI_MESSAGE_CONTROL in order to set/get the number of required
> MSI interrupts in EP mode) where dbi accessors must
> be used to access data of size 2. This is in preparation for
> adding endpoint mode support to designware driver.
Hello Kishon
I don't really like the idea of adding an extra argument to every existing read/write.
Will not a read/write of length != 32 be quite uncommon compared to
a read/write of length == 32?
How about adding some defines to pcie-designware.h:
#define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val)
#define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4)
That way we don't have to change every existing read/write.
Is there a reason why we can't just do:
val = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL);
<shifting+masking the bits we need to get/set>
dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val);
Or are we going to be doing read/writes of length != 32 so often that
you think that it's cleaner to have this abstraction?
>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Murali Karicheri <m-karicheri2@ti.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Niklas Cassel <niklas.cassel@axis.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>
> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pci-dra7xx.c | 8 ++--
> drivers/pci/dwc/pci-exynos.c | 16 +++----
> drivers/pci/dwc/pci-imx6.c | 54 +++++++++++-----------
> drivers/pci/dwc/pci-keystone-dw.c | 13 +++---
> drivers/pci/dwc/pcie-armada8k.c | 38 ++++++++--------
> drivers/pci/dwc/pcie-artpec6.c | 6 +--
> drivers/pci/dwc/pcie-designware-host.c | 18 ++++----
> drivers/pci/dwc/pcie-designware.c | 77 +++++++++++++++++++-------------
> drivers/pci/dwc/pcie-designware.h | 14 +++---
> drivers/pci/dwc/pcie-hisi.c | 14 +++---
> 10 files changed, 138 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index 3708bd6..c6fef0a 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -499,9 +499,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
> u32 val;
>
> /* clear MSE */
> - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
> val &= ~PCI_COMMAND_MEMORY;
> - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
> + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
>
> return 0;
> }
> @@ -514,9 +514,9 @@ static int dra7xx_pcie_resume(struct device *dev)
> u32 val;
>
> /* set MSE */
> - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
> val |= PCI_COMMAND_MEMORY;
> - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
> + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
>
> return 0;
> }
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index a0d40f7..37d6d2b 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -521,25 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
> exynos_pcie_msi_init(ep);
> }
>
> -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
> - u32 reg)
> +static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> {
> struct exynos_pcie *ep = to_exynos_pcie(pci);
> u32 val;
>
> exynos_pcie_sideband_dbi_r_mode(ep, true);
> - val = readl(base + reg);
> + dw_pcie_read(base + reg, size, &val);
> exynos_pcie_sideband_dbi_r_mode(ep, false);
> return val;
> }
>
> -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
> - u32 reg, u32 val)
> +static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> {
> struct exynos_pcie *ep = to_exynos_pcie(pci);
>
> exynos_pcie_sideband_dbi_w_mode(ep, true);
> - writel(val, base + reg);
> + dw_pcie_write(base + reg, size, val);
> exynos_pcie_sideband_dbi_w_mode(ep, false);
> }
>
> @@ -646,8 +646,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
> }
>
> static const struct dw_pcie_ops dw_pcie_ops = {
> - .readl_dbi = exynos_pcie_readl_dbi,
> - .writel_dbi = exynos_pcie_writel_dbi,
> + .read_dbi = exynos_pcie_read_dbi,
> + .write_dbi = exynos_pcie_write_dbi,
> .link_up = exynos_pcie_link_up,
> };
>
> diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
> index 85dd901..e58ca7a 100644
> --- a/drivers/pci/dwc/pci-imx6.c
> +++ b/drivers/pci/dwc/pci-imx6.c
> @@ -104,7 +104,7 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
> u32 wait_counter = 0;
>
> do {
> - val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
> + val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
> val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
> wait_counter++;
>
> @@ -125,17 +125,17 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
> int ret;
>
> val = addr << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
>
> val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> return ret;
>
> val = addr << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
>
> return pcie_phy_poll_ack(imx6_pcie, 0);
> }
> @@ -154,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
>
> /* assert Read signal */
> phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, phy_ctl);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> return ret;
>
> - val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
> + val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
> *data = val & 0xffff;
>
> /* deassert Read signal */
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x00);
>
> return pcie_phy_poll_ack(imx6_pcie, 0);
> }
> @@ -183,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
> return ret;
>
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
>
> /* capture data */
> var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
>
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> if (ret)
> @@ -195,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* deassert cap data */
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
>
> /* wait for ack de-assertion */
> ret = pcie_phy_poll_ack(imx6_pcie, 0);
> @@ -204,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* assert wr signal */
> var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
>
> /* wait for ack */
> ret = pcie_phy_poll_ack(imx6_pcie, 1);
> @@ -213,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>
> /* deassert wr signal */
> var = data << PCIE_PHY_CTRL_DATA_LOC;
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
>
> /* wait for ack de-assertion */
> ret = pcie_phy_poll_ack(imx6_pcie, 0);
> if (ret)
> return ret;
>
> - dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
> + dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x0);
>
> return 0;
> }
> @@ -423,8 +423,8 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
> return 0;
>
> dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
> return -ETIMEDOUT;
> }
>
> @@ -437,8 +437,8 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
> unsigned int retries;
>
> for (retries = 0; retries < 200; retries++) {
> - tmp = dw_pcie_readl_dbi(pci, base,
> - PCIE_LINK_WIDTH_SPEED_CONTROL);
> + tmp = dw_pcie_read_dbi(pci, base,
> + PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
> /* Test if the speed change finished. */
> if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
> return 0;
> @@ -471,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> * started in Gen2 mode, there is a possibility the devices on the
> * bus will not be detected at all. This happens with PCIe switches.
> */
> - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
> + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
> - dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
> + dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
>
> /* Start LTSSM. */
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> @@ -486,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>
> if (imx6_pcie->link_gen == 2) {
> /* Allow Gen2 mode after the link is up. */
> - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
> + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
> - dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
> + dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
> } else {
> dev_info(dev, "Link: Gen2 disabled\n");
> }
> @@ -498,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> * Start Directed Speed Change so the best possible speed both link
> * partners support can be negotiated.
> */
> - tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + tmp = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
> tmp |= PORT_LOGIC_SPEED_CHANGE;
> - dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
> + dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, tmp);
>
> ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
> if (ret) {
> @@ -515,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> goto err_reset_phy;
> }
>
> - tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
> + tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCSR, 0x4);
> dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
> return 0;
>
> err_reset_phy:
> dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
> imx6_pcie_reset_phy(imx6_pcie);
> return ret;
> }
> @@ -546,7 +546,7 @@ static int imx6_pcie_link_up(struct dw_pcie *pci)
> {
> void __iomem *base = pci->dbi_base;
>
> - return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
> + return dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4) &
> PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
> }
>
> diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
> index 7220c04..8318efe 100644
> --- a/drivers/pci/dwc/pci-keystone-dw.c
> +++ b/drivers/pci/dwc/pci-keystone-dw.c
> @@ -386,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>
> /* Disable BARs for inbound access */
> ks_dw_pcie_set_dbi_mode(ks_pcie);
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0);
> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>
> /* Set outbound translation size per window division */
> @@ -490,8 +490,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> ks_dw_pcie_set_dbi_mode(ks_pcie);
>
> /* Enable BAR0 */
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 1);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, SZ_4K - 1);
>
> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>
> @@ -499,7 +499,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
> * For BAR0, just setting bus address for inbound writes (MSI) should
> * be sufficient. Use physical address to avoid any conflicts.
> */
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4,
> + ks_pcie->app.start);
> }
>
> /**
> @@ -510,7 +511,7 @@ int ks_dw_pcie_link_up(struct dw_pcie *pci)
> u32 val;
> void __iomem *base = pci->dbi_base;
>
> - val = dw_pcie_readl_dbi(pci, base, DEBUG0);
> + val = dw_pcie_read_dbi(pci, base, DEBUG0, 0x4);
> return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
> }
>
> diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
> index b2328df..447d178 100644
> --- a/drivers/pci/dwc/pcie-armada8k.c
> +++ b/drivers/pci/dwc/pcie-armada8k.c
> @@ -75,7 +75,7 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
> u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
> void __iomem *base = pci->dbi_base;
>
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_STATUS_REG, 0x4);
>
> if ((reg & mask) == mask)
> return 1;
> @@ -92,45 +92,45 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
>
> if (!dw_pcie_link_up(pci)) {
> /* Disable LTSSM state machine to enable configuration */
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
> reg &= ~(PCIE_APP_LTSSM_EN);
> - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
> }
>
> /* Set the device to root complex mode */
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
> reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
> reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
> - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
>
> /* Set the PCIe master AxCache attributes */
> - dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
> - ARCACHE_DEFAULT_VALUE);
> - dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
> - AWCACHE_DEFAULT_VALUE);
> + dw_pcie_write_dbi(pci, base, PCIE_ARCACHE_TRC_REG, 0x4,
> + ARCACHE_DEFAULT_VALUE);
> + dw_pcie_write_dbi(pci, base, PCIE_AWCACHE_TRC_REG, 0x4,
> + AWCACHE_DEFAULT_VALUE);
>
> /* Set the PCIe master AxDomain attributes */
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_ARUSER_REG, 0x4);
> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
> - dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_ARUSER_REG, 0x4, reg);
>
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_AWUSER_REG, 0x4);
> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
> - dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_AWUSER_REG, 0x4, reg);
>
> /* Enable INT A-D interrupts */
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4);
> reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
> PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
> - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4, reg);
>
> if (!dw_pcie_link_up(pci)) {
> /* Configuration done. Start LTSSM */
> - reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
> + reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
> reg |= PCIE_APP_LTSSM_EN;
> - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
> + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
> }
>
> /* Wait until the link becomes active again */
> @@ -159,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
> * PCI device. However, they are also latched into the PCIe
> * controller, so we simply discard them.
> */
> - val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
> - dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
> + val = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4);
> + dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4, val);
>
> return IRQ_HANDLED;
> }
> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
> index e3ba11c..0829de4 100644
> --- a/drivers/pci/dwc/pcie-artpec6.c
> +++ b/drivers/pci/dwc/pcie-artpec6.c
> @@ -146,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> * Enable writing to config regs. This is required as the Synopsys
> * driver changes the class code. That register needs DBI write enable.
> */
> - dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
> + dw_pcie_write_dbi(pci, base, MISC_CONTROL_1_OFF, 0x4, DBI_RO_WR_EN);
>
> /* setup root complex */
> dw_pcie_setup_rc(pp);
> @@ -161,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
> return 0;
>
> dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
> - dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
> + dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
>
> return -ETIMEDOUT;
> }
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index 9df620d..3150d33 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -568,7 +568,7 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
> u32 val;
> void __iomem *base = pci->dbi_base;
>
> - val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
> + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4);
> if (val == 0xffffffff)
> return 1;
>
> @@ -584,27 +584,27 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> dw_pcie_setup(pci);
>
> /* setup RC BARs */
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
> - dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0x00000004);
> + dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0x00000000);
>
> /* setup interrupt pins */
> - val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
> + val = dw_pcie_read_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4);
> val &= 0xffff00ff;
> val |= 0x00000100;
> - dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, val);
>
> /* setup bus numbers */
> - val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
> + val = dw_pcie_read_dbi(pci, base, PCI_PRIMARY_BUS, 0x4);
> val &= 0xff000000;
> val |= 0x00010100;
> - dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
> + dw_pcie_write_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, val);
>
> /* setup command register */
> - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
> + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
> val &= 0xffff0000;
> val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
> + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
>
> /*
> * If the platform provides ->rd_other_conf, it means the platform
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index f8eaeea..557ee53 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
> return PCIBIOS_SUCCESSFUL;
> }
>
> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
> +u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + size_t size)
> {
> - if (pci->ops->readl_dbi)
> - return pci->ops->readl_dbi(pci, base, reg);
> + int ret;
> + u32 val;
> +
> + if (pci->ops->read_dbi)
> + return pci->ops->read_dbi(pci, base, reg, size);
>
> - return readl(base + reg);
> + ret = dw_pcie_read(base + reg, size, &val);
> + if (ret)
> + dev_err(pci->dev, "read DBI address failed\n");
> +
> + return val;
> }
>
> -void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> - u32 val)
> +void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + size_t size, u32 val)
> {
> - if (pci->ops->writel_dbi)
> - pci->ops->writel_dbi(pci, base, reg, val);
> - else
> - writel(val, base + reg);
> + int ret;
> +
> + if (pci->ops->write_dbi) {
> + pci->ops->write_dbi(pci, base, reg, size, val);
> + return;
> + }
> +
> + ret = dw_pcie_write(base + reg, size, val);
> + if (ret)
> + dev_err(pci->dev, "write DBI address failed\n");
> }
>
> static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
> @@ -83,7 +97,7 @@ static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> - return dw_pcie_readl_dbi(pci, base, offset + reg);
> + return dw_pcie_read_dbi(pci, base, offset + reg, 0x4);
> }
>
> static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
> @@ -91,7 +105,7 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>
> - dw_pcie_writel_dbi(pci, base, offset + reg, val);
> + dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> }
>
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> @@ -123,20 +137,21 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> PCIE_ATU_UNR_REGION_CTRL2,
> PCIE_ATU_ENABLE);
> } else {
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
> - PCIE_ATU_REGION_OUTBOUND | index);
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
> - lower_32_bits(cpu_addr));
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
> - upper_32_bits(cpu_addr));
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
> - lower_32_bits(cpu_addr + size - 1));
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
> - lower_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
> - upper_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
> - dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
> + PCIE_ATU_REGION_OUTBOUND | index);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
> + lower_32_bits(cpu_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
> + upper_32_bits(cpu_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
> + lower_32_bits(cpu_addr + size - 1));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
> + lower_32_bits(pci_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
> + upper_32_bits(pci_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
> + PCIE_ATU_ENABLE);
> }
>
> /*
> @@ -148,7 +163,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> val = dw_pcie_readl_unroll(pci, base, index,
> PCIE_ATU_UNR_REGION_CTRL2);
> else
> - val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
> + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
>
> if (val == PCIE_ATU_ENABLE)
> return;
> @@ -202,7 +217,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> lanes = 0;
>
> /* set the number of lanes */
> - val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
> + val = dw_pcie_read_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4);
> val &= ~PORT_LINK_MODE_MASK;
> switch (lanes) {
> case 1:
> @@ -221,10 +236,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
> dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
> return;
> }
> - dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
> + dw_pcie_write_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, val);
>
> /* set link width speed control register */
> - val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
> val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> switch (lanes) {
> case 1:
> @@ -240,5 +255,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> break;
> }
> - dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> + dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, val);
> }
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index fe93f7f..74df063 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -144,9 +144,10 @@ struct pcie_port {
>
> struct dw_pcie_ops {
> u64 (*cpu_addr_fixup)(u64 cpu_addr);
> - u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
> - void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> - u32 val);
> + u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> + size_t size);
> + void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> + size_t size, u32 val);
> int (*link_up)(struct dw_pcie *pcie);
> };
>
> @@ -164,9 +165,10 @@ struct dw_pcie {
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>
> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
> -void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> - u32 val);
> +u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + size_t size);
> +void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> + size_t size, u32 val);
> int dw_pcie_link_up(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
> index 409b54b..cc04381 100644
> --- a/drivers/pci/dwc/pcie-hisi.c
> +++ b/drivers/pci/dwc/pcie-hisi.c
> @@ -156,7 +156,7 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
>
> walker += (where & 0x3);
> reg = where & ~0x3;
> - reg_val = dw_pcie_readl_dbi(pci, base, reg);
> + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
>
> if (size == 1)
> *val = *(u8 __force *) walker;
> @@ -183,15 +183,15 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
> walker += (where & 0x3);
> reg = where & ~0x3;
> if (size == 4)
> - dw_pcie_writel_dbi(pci, base, reg, val);
> + dw_pcie_write_dbi(pci, base, reg, 0x4, val);
> else if (size == 2) {
> - reg_val = dw_pcie_readl_dbi(pci, base, reg);
> + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
> *(u16 __force *) walker = val;
> - dw_pcie_writel_dbi(pci, base, reg, reg_val);
> + dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
> } else if (size == 1) {
> - reg_val = dw_pcie_readl_dbi(pci, base, reg);
> + reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
> *(u8 __force *) walker = val;
> - dw_pcie_writel_dbi(pci, base, reg, reg_val);
> + dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
> } else
> return PCIBIOS_BAD_REGISTER_NUMBER;
>
> @@ -214,7 +214,7 @@ static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
> void __iomem *base = pci->dbi_base;
> u32 val;
>
> - val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
> + val = dw_pcie_read_dbi(pci, base, PCIE_SYS_STATE4, 0x4);
>
> return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
> }
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-09 14:48 ` Niklas Cassel
@ 2017-03-09 15:05 ` Niklas Cassel
2017-03-10 11:36 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-09 15:05 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/09/2017 03:48 PM, Niklas Cassel wrote:
> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>> helper to access dbi address space can access only dbics. However
>> dbics2 has to be accessed for programming the BAR registers in the
>> case of EP mode. This is in preparation for adding EP mode support
>> to dwc driver.
> Hello Kishon
>
> I don't really like the idea of adding an extra argument to every existing read/write.
> Will not a read/write using dbi2 be quite uncommon compared to a read/write
> using dbi?
>
> How about something like this:
>
> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
> {
> if (pci->ops->writel_dbi)
> pci->ops->writel_dbi(pci, base, reg, val);
> else
> writel(val, base + reg);
> }
>
> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
so we can return an error if pci->dbi_base2 == NULL.
>
> That way we don't have to change every existing read/write.
> I'm assuming that synopsys won't add a dbi3 in the next version of the IP :p
>
>> Cc: Jingoo Han <jingoohan1@gmail.com>
>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>> Cc: Lucas Stach <l.stach@pengutronix.de>
>> Cc: Murali Karicheri <m-karicheri2@ti.com>
>> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Cc: Niklas Cassel <niklas.cassel@axis.com>
>> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
>> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
>> Cc: Zhou Wang <wangzhou1@hisilicon.com>
>> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
>> Acked-by: Joao Pinto <jpinto@synopsys.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/pci-dra7xx.c | 10 +++--
>> drivers/pci/dwc/pci-exynos.c | 10 +++--
>> drivers/pci/dwc/pci-imx6.c | 62 +++++++++++++++-----------
>> drivers/pci/dwc/pci-keystone-dw.c | 15 ++++---
>> drivers/pci/dwc/pcie-armada8k.c | 39 +++++++++-------
>> drivers/pci/dwc/pcie-artpec6.c | 7 +--
>> drivers/pci/dwc/pcie-designware-host.c | 20 +++++----
>> drivers/pci/dwc/pcie-designware.c | 76 ++++++++++++++++++--------------
>> drivers/pci/dwc/pcie-designware.h | 10 +++--
>> drivers/pci/dwc/pcie-hisi.c | 17 ++++---
>> 10 files changed, 152 insertions(+), 114 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
>> index 07c45ec..3708bd6 100644
>> --- a/drivers/pci/dwc/pci-dra7xx.c
>> +++ b/drivers/pci/dwc/pci-dra7xx.c
>> @@ -495,12 +495,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
>> {
>> struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
>> struct dw_pcie *pci = dra7xx->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>>
>> /* clear MSE */
>> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
>> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
>> val &= ~PCI_COMMAND_MEMORY;
>> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>>
>> return 0;
>> }
>> @@ -509,12 +510,13 @@ static int dra7xx_pcie_resume(struct device *dev)
>> {
>> struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
>> struct dw_pcie *pci = dra7xx->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>>
>> /* set MSE */
>> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
>> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
>> val |= PCI_COMMAND_MEMORY;
>> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>>
>> return 0;
>> }
>> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
>> index 993b650..a0d40f7 100644
>> --- a/drivers/pci/dwc/pci-exynos.c
>> +++ b/drivers/pci/dwc/pci-exynos.c
>> @@ -521,23 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
>> exynos_pcie_msi_init(ep);
>> }
>>
>> -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
>> +static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
>> + u32 reg)
>> {
>> struct exynos_pcie *ep = to_exynos_pcie(pci);
>> u32 val;
>>
>> exynos_pcie_sideband_dbi_r_mode(ep, true);
>> - val = readl(pci->dbi_base + reg);
>> + val = readl(base + reg);
>> exynos_pcie_sideband_dbi_r_mode(ep, false);
>> return val;
>> }
>>
>> -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
>> +static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
>> + u32 reg, u32 val)
>> {
>> struct exynos_pcie *ep = to_exynos_pcie(pci);
>>
>> exynos_pcie_sideband_dbi_w_mode(ep, true);
>> - writel(val, pci->dbi_base + reg);
>> + writel(val, base + reg);
>> exynos_pcie_sideband_dbi_w_mode(ep, false);
>> }
>>
>> diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
>> index 801e46c..85dd901 100644
>> --- a/drivers/pci/dwc/pci-imx6.c
>> +++ b/drivers/pci/dwc/pci-imx6.c
>> @@ -98,12 +98,13 @@ struct imx6_pcie {
>> static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>> u32 max_iterations = 10;
>> u32 wait_counter = 0;
>>
>> do {
>> - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
>> val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
>> wait_counter++;
>>
>> @@ -119,21 +120,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
>> static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>> int ret;
>>
>> val = addr << PCIE_PHY_CTRL_DATA_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>>
>> val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>>
>> ret = pcie_phy_poll_ack(imx6_pcie, 1);
>> if (ret)
>> return ret;
>>
>> val = addr << PCIE_PHY_CTRL_DATA_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
>>
>> return pcie_phy_poll_ack(imx6_pcie, 0);
>> }
>> @@ -142,6 +144,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
>> static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val, phy_ctl;
>> int ret;
>>
>> @@ -151,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
>>
>> /* assert Read signal */
>> phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
>>
>> ret = pcie_phy_poll_ack(imx6_pcie, 1);
>> if (ret)
>> return ret;
>>
>> - val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
>> *data = val & 0xffff;
>>
>> /* deassert Read signal */
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
>>
>> return pcie_phy_poll_ack(imx6_pcie, 0);
>> }
>> @@ -169,6 +172,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
>> static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 var;
>> int ret;
>>
>> @@ -179,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>> return ret;
>>
>> var = data << PCIE_PHY_CTRL_DATA_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>>
>> /* capture data */
>> var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>>
>> ret = pcie_phy_poll_ack(imx6_pcie, 1);
>> if (ret)
>> @@ -191,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>>
>> /* deassert cap data */
>> var = data << PCIE_PHY_CTRL_DATA_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>>
>> /* wait for ack de-assertion */
>> ret = pcie_phy_poll_ack(imx6_pcie, 0);
>> @@ -200,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>>
>> /* assert wr signal */
>> var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>>
>> /* wait for ack */
>> ret = pcie_phy_poll_ack(imx6_pcie, 1);
>> @@ -209,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
>>
>> /* deassert wr signal */
>> var = data << PCIE_PHY_CTRL_DATA_LOC;
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
>>
>> /* wait for ack de-assertion */
>> ret = pcie_phy_poll_ack(imx6_pcie, 0);
>> if (ret)
>> return ret;
>>
>> - dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
>>
>> return 0;
>> }
>> @@ -411,6 +415,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
>> static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> struct device *dev = pci->dev;
>>
>> /* check if the link is up or not */
>> @@ -418,20 +423,22 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
>> return 0;
>>
>> dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
>> return -ETIMEDOUT;
>> }
>>
>> static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> struct device *dev = pci->dev;
>> u32 tmp;
>> unsigned int retries;
>>
>> for (retries = 0; retries < 200; retries++) {
>> - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> + tmp = dw_pcie_readl_dbi(pci, base,
>> + PCIE_LINK_WIDTH_SPEED_CONTROL);
>> /* Test if the speed change finished. */
>> if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
>> return 0;
>> @@ -454,6 +461,7 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
>> static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>> {
>> struct dw_pcie *pci = imx6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> struct device *dev = pci->dev;
>> u32 tmp;
>> int ret;
>> @@ -463,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>> * started in Gen2 mode, there is a possibility the devices on the
>> * bus will not be detected at all. This happens with PCIe switches.
>> */
>> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
>> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
>> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
>> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
>> - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
>> + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
>>
>> /* Start LTSSM. */
>> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
>> @@ -478,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>>
>> if (imx6_pcie->link_gen == 2) {
>> /* Allow Gen2 mode after the link is up. */
>> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
>> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
>> tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
>> tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
>> - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
>> + dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
>> } else {
>> dev_info(dev, "Link: Gen2 disabled\n");
>> }
>> @@ -490,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>> * Start Directed Speed Change so the best possible speed both link
>> * partners support can be negotiated.
>> */
>> - tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> tmp |= PORT_LOGIC_SPEED_CHANGE;
>> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
>> + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
>>
>> ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
>> if (ret) {
>> @@ -507,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>> goto err_reset_phy;
>> }
>>
>> - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
>> + tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
>> dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
>> return 0;
>>
>> err_reset_phy:
>> dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
>> imx6_pcie_reset_phy(imx6_pcie);
>> return ret;
>> }
>> @@ -536,7 +544,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
>>
>> static int imx6_pcie_link_up(struct dw_pcie *pci)
>> {
>> - return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
>> + void __iomem *base = pci->dbi_base;
>> +
>> + return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
>> PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
>> }
>>
>> diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
>> index 6b396f6..7220c04 100644
>> --- a/drivers/pci/dwc/pci-keystone-dw.c
>> +++ b/drivers/pci/dwc/pci-keystone-dw.c
>> @@ -378,6 +378,7 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
>> void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>> {
>> struct dw_pcie *pci = ks_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> struct pcie_port *pp = &pci->pp;
>> u32 start = pp->mem->start, end = pp->mem->end;
>> int i, tr_size;
>> @@ -385,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>>
>> /* Disable BARs for inbound access */
>> ks_dw_pcie_set_dbi_mode(ks_pcie);
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
>> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>>
>> /* Set outbound translation size per window division */
>> @@ -482,14 +483,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>> void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + void __iomem *base = pci->dbi_base;
>> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>>
>> /* Configure and set up BAR0 */
>> ks_dw_pcie_set_dbi_mode(ks_pcie);
>>
>> /* Enable BAR0 */
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
>>
>> ks_dw_pcie_clear_dbi_mode(ks_pcie);
>>
>> @@ -497,7 +499,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
>> * For BAR0, just setting bus address for inbound writes (MSI) should
>> * be sufficient. Use physical address to avoid any conflicts.
>> */
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
>> }
>>
>> /**
>> @@ -506,8 +508,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
>> int ks_dw_pcie_link_up(struct dw_pcie *pci)
>> {
>> u32 val;
>> + void __iomem *base = pci->dbi_base;
>>
>> - val = dw_pcie_readl_dbi(pci, DEBUG0);
>> + val = dw_pcie_readl_dbi(pci, base, DEBUG0);
>> return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
>> }
>>
>> diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
>> index f110e3b..b2328df 100644
>> --- a/drivers/pci/dwc/pcie-armada8k.c
>> +++ b/drivers/pci/dwc/pcie-armada8k.c
>> @@ -73,8 +73,9 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
>> {
>> u32 reg;
>> u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
>> + void __iomem *base = pci->dbi_base;
>>
>> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
>>
>> if ((reg & mask) == mask)
>> return 1;
>> @@ -86,47 +87,50 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
>> static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
>> {
>> struct dw_pcie *pci = pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 reg;
>>
>> if (!dw_pcie_link_up(pci)) {
>> /* Disable LTSSM state machine to enable configuration */
>> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
>> reg &= ~(PCIE_APP_LTSSM_EN);
>> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
>> }
>>
>> /* Set the device to root complex mode */
>> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
>> reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
>> reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
>> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
>>
>> /* Set the PCIe master AxCache attributes */
>> - dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
>> - dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
>> + dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
>> + ARCACHE_DEFAULT_VALUE);
>> + dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
>> + AWCACHE_DEFAULT_VALUE);
>>
>> /* Set the PCIe master AxDomain attributes */
>> - reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
>> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
>> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
>> - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
>>
>> - reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
>> reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
>> reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
>> - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
>>
>> /* Enable INT A-D interrupts */
>> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
>> reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
>> PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
>> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
>>
>> if (!dw_pcie_link_up(pci)) {
>> /* Configuration done. Start LTSSM */
>> - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
>> + reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
>> reg |= PCIE_APP_LTSSM_EN;
>> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
>> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
>> }
>>
>> /* Wait until the link becomes active again */
>> @@ -147,6 +151,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
>> {
>> struct armada8k_pcie *pcie = arg;
>> struct dw_pcie *pci = pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>>
>> /*
>> @@ -154,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
>> * PCI device. However, they are also latched into the PCIe
>> * controller, so we simply discard them.
>> */
>> - val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
>> - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
>> + dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
>>
>> return IRQ_HANDLED;
>> }
>> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
>> index 5b3b3af..e3ba11c 100644
>> --- a/drivers/pci/dwc/pcie-artpec6.c
>> +++ b/drivers/pci/dwc/pcie-artpec6.c
>> @@ -86,6 +86,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
>> static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
>> {
>> struct dw_pcie *pci = artpec6_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> struct pcie_port *pp = &pci->pp;
>> u32 val;
>> unsigned int retries;
>> @@ -145,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
>> * Enable writing to config regs. This is required as the Synopsys
>> * driver changes the class code. That register needs DBI write enable.
>> */
>> - dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>> + dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>>
>> /* setup root complex */
>> dw_pcie_setup_rc(pp);
>> @@ -160,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
>> return 0;
>>
>> dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
>> - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
>> + dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
>>
>> return -ETIMEDOUT;
>> }
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
>> index 5ba3349..9df620d 100644
>> --- a/drivers/pci/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/dwc/pcie-designware-host.c
>> @@ -566,8 +566,9 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>> static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
>> {
>> u32 val;
>> + void __iomem *base = pci->dbi_base;
>>
>> - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
>> if (val == 0xffffffff)
>> return 1;
>>
>> @@ -578,31 +579,32 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>> {
>> u32 val;
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + void __iomem *base = pci->dbi_base;
>>
>> dw_pcie_setup(pci);
>>
>> /* setup RC BARs */
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
>> - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
>> + dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
>>
>> /* setup interrupt pins */
>> - val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
>> + val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
>> val &= 0xffff00ff;
>> val |= 0x00000100;
>> - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
>> + dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
>>
>> /* setup bus numbers */
>> - val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
>> + val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
>> val &= 0xff000000;
>> val |= 0x00010100;
>> - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
>> + dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
>>
>> /* setup command register */
>> - val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
>> + val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
>> val &= 0xffff0000;
>> val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
>> PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
>> - dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>> + dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
>>
>> /*
>> * If the platform provides ->rd_other_conf, it means the platform
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
>> index 14ee7a3..f8eaeea 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -61,75 +61,82 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
>> return PCIBIOS_SUCCESSFUL;
>> }
>>
>> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
>> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
>> {
>> if (pci->ops->readl_dbi)
>> - return pci->ops->readl_dbi(pci, reg);
>> + return pci->ops->readl_dbi(pci, base, reg);
>>
>> - return readl(pci->dbi_base + reg);
>> + return readl(base + reg);
>> }
>>
>> -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
>> +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
>> + u32 val)
>> {
>> if (pci->ops->writel_dbi)
>> - pci->ops->writel_dbi(pci, reg, val);
>> + pci->ops->writel_dbi(pci, base, reg, val);
>> else
>> - writel(val, pci->dbi_base + reg);
>> + writel(val, base + reg);
>> }
>>
>> -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
>> +static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
>> + u32 index, u32 reg)
>> {
>> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>>
>> - return dw_pcie_readl_dbi(pci, offset + reg);
>> + return dw_pcie_readl_dbi(pci, base, offset + reg);
>> }
>>
>> -static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
>> - u32 val)
>> +static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
>> + u32 index, u32 reg, u32 val)
>> {
>> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
>>
>> - dw_pcie_writel_dbi(pci, offset + reg, val);
>> + dw_pcie_writel_dbi(pci, base, offset + reg, val);
>> }
>>
>> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
>> u64 cpu_addr, u64 pci_addr, u32 size)
>> {
>> u32 retries, val;
>> + void __iomem *base = pci->dbi_base;
>>
>> - if (pp->ops->cpu_addr_fixup)
>> - cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
>> + if (pci->ops->cpu_addr_fixup)
>> + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
>>
>> if (pci->iatu_unroll_enabled) {
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
>> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
>> lower_32_bits(cpu_addr));
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
>> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
>> upper_32_bits(cpu_addr));
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
>> + dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
>> lower_32_bits(cpu_addr + size - 1));
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
>> + dw_pcie_writel_unroll(pci, base, index,
>> + PCIE_ATU_UNR_LOWER_TARGET,
>> lower_32_bits(pci_addr));
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
>> + dw_pcie_writel_unroll(pci, base, index,
>> + PCIE_ATU_UNR_UPPER_TARGET,
>> upper_32_bits(pci_addr));
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
>> + dw_pcie_writel_unroll(pci, base, index,
>> + PCIE_ATU_UNR_REGION_CTRL1,
>> type);
>> - dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
>> + dw_pcie_writel_unroll(pci, base, index,
>> + PCIE_ATU_UNR_REGION_CTRL2,
>> PCIE_ATU_ENABLE);
>> } else {
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
>> PCIE_ATU_REGION_OUTBOUND | index);
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
>> lower_32_bits(cpu_addr));
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
>> upper_32_bits(cpu_addr));
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
>> lower_32_bits(cpu_addr + size - 1));
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
>> lower_32_bits(pci_addr));
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
>> upper_32_bits(pci_addr));
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
>> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
>> + dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>> }
>>
>> /*
>> @@ -138,10 +145,10 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
>> */
>> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
>> if (pci->iatu_unroll_enabled)
>> - val = dw_pcie_readl_unroll(pci, index,
>> + val = dw_pcie_readl_unroll(pci, base, index,
>> PCIE_ATU_UNR_REGION_CTRL2);
>> else
>> - val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
>>
>> if (val == PCIE_ATU_ENABLE)
>> return;
>> @@ -188,13 +195,14 @@ void dw_pcie_setup(struct dw_pcie *pci)
>> u32 lanes;
>> struct device *dev = pci->dev;
>> struct device_node *np = dev->of_node;
>> + void __iomem *base = pci->dbi_base;
>>
>> ret = of_property_read_u32(np, "num-lanes", &lanes);
>> if (ret)
>> lanes = 0;
>>
>> /* set the number of lanes */
>> - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
>> val &= ~PORT_LINK_MODE_MASK;
>> switch (lanes) {
>> case 1:
>> @@ -213,10 +221,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
>> dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
>> return;
>> }
>> - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
>> + dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
>>
>> /* set link width speed control register */
>> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
>> val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
>> switch (lanes) {
>> case 1:
>> @@ -232,5 +240,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
>> val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
>> break;
>> }
>> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
>> + dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
>> }
>> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
>> index 8f3dcb2..fe93f7f 100644
>> --- a/drivers/pci/dwc/pcie-designware.h
>> +++ b/drivers/pci/dwc/pcie-designware.h
>> @@ -144,8 +144,9 @@ struct pcie_port {
>>
>> struct dw_pcie_ops {
>> u64 (*cpu_addr_fixup)(u64 cpu_addr);
>> - u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
>> - void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
>> + u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
>> + void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
>> + u32 val);
>> int (*link_up)(struct dw_pcie *pcie);
>> };
>>
>> @@ -163,8 +164,9 @@ struct dw_pcie {
>> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
>> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>>
>> -u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
>> -void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
>> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
>> +void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
>> + u32 val);
>> int dw_pcie_link_up(struct dw_pcie *pci);
>> int dw_pcie_wait_for_link(struct dw_pcie *pci);
>> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>> diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
>> index fd66a31..409b54b 100644
>> --- a/drivers/pci/dwc/pcie-hisi.c
>> +++ b/drivers/pci/dwc/pcie-hisi.c
>> @@ -152,10 +152,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
>> u32 reg_val;
>> void *walker = ®_val;
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + void __iomem *base = pci->dbi_base;
>>
>> walker += (where & 0x3);
>> reg = where & ~0x3;
>> - reg_val = dw_pcie_readl_dbi(pci, reg);
>> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
>>
>> if (size == 1)
>> *val = *(u8 __force *) walker;
>> @@ -177,19 +178,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
>> u32 reg;
>> void *walker = ®_val;
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + void __iomem *base = pci->dbi_base;
>>
>> walker += (where & 0x3);
>> reg = where & ~0x3;
>> if (size == 4)
>> - dw_pcie_writel_dbi(pci, reg, val);
>> + dw_pcie_writel_dbi(pci, base, reg, val);
>> else if (size == 2) {
>> - reg_val = dw_pcie_readl_dbi(pci, reg);
>> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
>> *(u16 __force *) walker = val;
>> - dw_pcie_writel_dbi(pci, reg, reg_val);
>> + dw_pcie_writel_dbi(pci, base, reg, reg_val);
>> } else if (size == 1) {
>> - reg_val = dw_pcie_readl_dbi(pci, reg);
>> + reg_val = dw_pcie_readl_dbi(pci, base, reg);
>> *(u8 __force *) walker = val;
>> - dw_pcie_writel_dbi(pci, reg, reg_val);
>> + dw_pcie_writel_dbi(pci, base, reg, reg_val);
>> } else
>> return PCIBIOS_BAD_REGISTER_NUMBER;
>>
>> @@ -209,9 +211,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
>> static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
>> {
>> struct dw_pcie *pci = hisi_pcie->pci;
>> + void __iomem *base = pci->dbi_base;
>> u32 val;
>>
>> - val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
>> + val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
>>
>> return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
>> }
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-09 15:05 ` Niklas Cassel
@ 2017-03-10 11:36 ` Kishon Vijay Abraham I
2017-03-10 12:23 ` Niklas Cassel
` (2 more replies)
0 siblings, 3 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-10 11:36 UTC (permalink / raw)
To: Niklas Cassel, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Hi,
On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>
>
> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>> helper to access dbi address space can access only dbics. However
>>> dbics2 has to be accessed for programming the BAR registers in the
>>> case of EP mode. This is in preparation for adding EP mode support
>>> to dwc driver.
>> Hello Kishon
>>
>> I don't really like the idea of adding an extra argument to every existing read/write.
>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>> using dbi?
>>
>> How about something like this:
>>
>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>> {
>> if (pci->ops->writel_dbi)
>> pci->ops->writel_dbi(pci, base, reg, val);
>> else
>> writel(val, base + reg);
>> }
>>
>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>
> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
> so we can return an error if pci->dbi_base2 == NULL.
Should we return an error? We don't return error for dbi_base either. I think
it should be sufficient to return errors while populating dbi_base or
dbi_base2. Otherwise it's a bug and should result in abort. Joao?
Thanks
Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-09 14:48 ` Niklas Cassel
@ 2017-03-10 12:04 ` Kishon Vijay Abraham I
2017-03-10 12:56 ` Niklas Cassel
0 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-10 12:04 UTC (permalink / raw)
To: Niklas Cassel, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Hi,
On Thursday 09 March 2017 08:18 PM, Niklas Cassel wrote:
> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>> Previously dbi accessors can be used to access data of size 4
>> bytes. But there might be situations (like accessing
>> MSI_MESSAGE_CONTROL in order to set/get the number of required
>> MSI interrupts in EP mode) where dbi accessors must
>> be used to access data of size 2. This is in preparation for
>> adding endpoint mode support to designware driver.
>
> Hello Kishon
>
> I don't really like the idea of adding an extra argument to every existing read/write.
> Will not a read/write of length != 32 be quite uncommon compared to
> a read/write of length == 32?
>
> How about adding some defines to pcie-designware.h:
>
> #define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val)
> #define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4)
>
> That way we don't have to change every existing read/write.
>
>
>
> Is there a reason why we can't just do:
>
> vial = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL);
MSI_MESSAGE_CONTROL is 0x52 (MSI capability offset + 2). I'm not sure if we can
do a readl that crosses the alignment boundary in all platforms. The other
option is to readl from "MSI capability offset + 0" and extract the last 16
bits. I felt this is more clear since we are interested only in the
MSI_MESSAGE_CONTROL.
> <shifting+masking the bits we need to get/set>
> dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val);
>
> Or are we going to be doing read/writes of length != 32 so often that
> you think that it's cleaner to have this abstraction?
it's used mainly for accessing configuration space header fields. Even the pci
core uses *pci_read_config_word* for accessing such fields.
Thanks
Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 11:36 ` Kishon Vijay Abraham I
@ 2017-03-10 12:23 ` Niklas Cassel
2017-03-10 12:30 ` Joao Pinto
2017-03-10 12:31 ` Niklas Cassel
2 siblings, 0 replies; 24+ messages in thread
From: Niklas Cassel @ 2017-03-10 12:23 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>
>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>> helper to access dbi address space can access only dbics. However
>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>> case of EP mode. This is in preparation for adding EP mode support
>>>> to dwc driver.
>>> Hello Kishon
>>>
>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>> using dbi?
>>>
>>> How about something like this:
>>>
>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>> {
>>> if (pci->ops->writel_dbi)
>>> pci->ops->writel_dbi(pci, base, reg, val);x‘W¡R\x7f
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 11:36 ` Kishon Vijay Abraham I
2017-03-10 12:23 ` Niklas Cassel
@ 2017-03-10 12:30 ` Joao Pinto
2017-03-10 12:31 ` Niklas Cassel
2 siblings, 0 replies; 24+ messages in thread
From: Joao Pinto @ 2017-03-10 12:30 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Niklas Cassel, Bjorn Helgaas, Joao Pinto,
linux-pci, linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Às 11:36 AM de 3/10/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>
>>
>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>> helper to access dbi address space can access only dbics. However
>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>> case of EP mode. This is in preparation for adding EP mode support
>>>> to dwc driver.
>>> Hello Kishon
>>>
>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>> using dbi?
>>>
>>> How about something like this:
>>>
>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>> {
>>> if (pci->ops->writel_dbi)
>>> pci->ops->writel_dbi(pci, base, reg, val);
>>> else
>>> writel(val, base + reg);
>>> }
>>>
>>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>>
>> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
>> so we can return an error if pci->dbi_base2 == NULL.
>
> Should we return an error? We don't return error for dbi_base either. I think
> it should be sufficient to return errors while populating dbi_base or
> dbi_base2. Otherwise it's a bug and should result in abort. Joao?
I agree with Kishon.
Thanks,
Joao
>
> Thanks
> Kishon
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 11:36 ` Kishon Vijay Abraham I
2017-03-10 12:23 ` Niklas Cassel
2017-03-10 12:30 ` Joao Pinto
@ 2017-03-10 12:31 ` Niklas Cassel
2017-03-10 12:56 ` Kishon Vijay Abraham I
2 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-10 12:31 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>
>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>> helper to access dbi address space can access only dbics. However
>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>> case of EP mode. This is in preparation for adding EP mode support
>>>> to dwc driver.
>>> Hello Kishon
>>>
>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>> using dbi?
>>>
>>> How about something like this:
>>>
>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>> {
>>> if (pci->ops->writel_dbi)
>>> pci->ops->writel_dbi(pci, base, reg, val);
>>> else
>>> writel(val, base + reg);
>>> }
>>>
>>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
>> so we can return an error if pci->dbi_base2 == NULL.
> Should we return an error? We don't return error for dbi_base either. I think
> it should be sufficient to return errors while populating dbi_base or
> dbi_base2. Otherwise it's a bug and should result in abort. Joao?
Sorry for previous empty email.
What I meant to write:
Right now we do error checking for dbi_base in platform specific code
and in pcie-designware-host.c:dw_pcie_host_init.
For dbi_base2, you've added error checking in platform specific code
(pci-dra7xx.c), but I don't see any error checking in your patch proposal
pcie-designware-ep.c:dw_pcie_ep_init.
If you add error checking in dw_pcie_ep_init, then I agree,
we don't need any error checking in dw_pcie_writel_dbi2.
>
> Thanks
> Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-10 12:04 ` Kishon Vijay Abraham I
@ 2017-03-10 12:56 ` Niklas Cassel
2017-03-10 13:04 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-10 12:56 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/10/2017 01:04 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 09 March 2017 08:18 PM, Niklas Cassel wrote:
>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>> Previously dbi accessors can be used to access data of size 4
>>> bytes. But there might be situations (like accessing
>>> MSI_MESSAGE_CONTROL in order to set/get the number of required
>>> MSI interrupts in EP mode) where dbi accessors must
>>> be used to access data of size 2. This is in preparation for
>>> adding endpoint mode support to designware driver.
>> Hello Kishon
>>
>> I don't really like the idea of adding an extra argument to every existing read/write.
>> Will not a read/write of length != 32 be quite uncommon compared to
>> a read/write of length == 32?
>>
>> How about adding some defines to pcie-designware.h:
>>
>> #define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val)
>> #define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4)
>>
>> That way we don't have to change every existing read/write.
>>
>>
>>
>> Is there a reason why we can't just do:
>>
>> vial = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL);
> MSI_MESSAGE_CONTROL is 0x52 (MSI capability offset + 2). I'm not sure if we can
> do a readl that crosses the alignment boundary in all platforms. The other
> option is to readl from "MSI capability offset + 0" and extract the last 16
> bits. I felt this is more clear since we are interested only in the
> MSI_MESSAGE_CONTROL.
>
>> <shifting+masking the bits we need to get/set>
>> dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val);
>>
>> Or are we going to be doing read/writes of length != 32 so often that
>> you think that it's cleaner to have this abstraction?
> it's used mainly for accessing configuration space header fields. Even the pci
> core uses *pci_read_config_word* for accessing such fields.
I see. Adding an extra size argument is a good thing then,
since it's consistent with the pci generic code.
However, I still think that having defines for writel/readl is a
good thing :)
>
> Thanks
> Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 12:31 ` Niklas Cassel
@ 2017-03-10 12:56 ` Kishon Vijay Abraham I
2017-03-10 15:47 ` Niklas Cassel
0 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-10 12:56 UTC (permalink / raw)
To: Niklas Cassel, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Hi Niklas,
On Friday 10 March 2017 06:01 PM, Niklas Cassel wrote:
> On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>>
>>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>>> helper to access dbi address space can access only dbics. However
>>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>>> case of EP mode. This is in preparation for adding EP mode support
>>>>> to dwc driver.
>>>> Hello Kishon
>>>>
>>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>>> using dbi?
>>>>
>>>> How about something like this:
>>>>
>>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>>> {
>>>> if (pci->ops->writel_dbi)
>>>> pci->ops->writel_dbi(pci, base, reg, val);
>>>> else
>>>> writel(val, base + reg);
>>>> }
>>>>
>>>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>>>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>>> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
>>> so we can return an error if pci->dbi_base2 == NULL.
>> Should we return an error? We don't return error for dbi_base either. I think
>> it should be sufficient to return errors while populating dbi_base or
>> dbi_base2. Otherwise it's a bug and should result in abort. Joao?
>
> Sorry for previous empty email.
>
>
> What I meant to write:
>
> Right now we do error checking for dbi_base in platform specific code
> and in pcie-designware-host.c:dw_pcie_host_init.
it's been done in dw_pcie_host_init not as an error checking but since it's
*optional* for certain platforms to populate dbi_base (i.e where dbi_base is
mapped to configuration space), host_init takes care of assigning dbi_base to
configuration space address.
Thanks
Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-10 12:56 ` Niklas Cassel
@ 2017-03-10 13:04 ` Kishon Vijay Abraham I
2017-03-10 14:59 ` Niklas Cassel
0 siblings, 1 reply; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-10 13:04 UTC (permalink / raw)
To: Niklas Cassel, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Hi,
On Friday 10 March 2017 06:26 PM, Niklas Cassel wrote:
> On 03/10/2017 01:04 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 09 March 2017 08:18 PM, Niklas Cassel wrote:
>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>> Previously dbi accessors can be used to access data of size 4
>>>> bytes. But there might be situations (like accessing
>>>> MSI_MESSAGE_CONTROL in order to set/get the number of required
>>>> MSI interrupts in EP mode) where dbi accessors must
>>>> be used to access data of size 2. This is in preparation for
>>>> adding endpoint mode support to designware driver.
>>> Hello Kishon
>>>
>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>> Will not a read/write of length != 32 be quite uncommon compared to
>>> a read/write of length == 32?
>>>
>>> How about adding some defines to pcie-designware.h:
>>>
>>> #define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val)
>>> #define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4)
>>>
>>> That way we don't have to change every existing read/write.
>>>
>>>
>>>
>>> Is there a reason why we can't just do:
>>>
>>> vial = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL);
>> MSI_MESSAGE_CONTROL is 0x52 (MSI capability offset + 2). I'm not sure if we can
>> do a readl that crosses the alignment boundary in all platforms. The other
>> option is to readl from "MSI capability offset + 0" and extract the last 16
>> bits. I felt this is more clear since we are interested only in the
>> MSI_MESSAGE_CONTROL.
>>
>>> <shifting+masking the bits we need to get/set>
>>> dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val);
>>>
>>> Or are we going to be doing read/writes of length != 32 so often that
>>> you think that it's cleaner to have this abstraction?
>> it's used mainly for accessing configuration space header fields. Even the pci
>> core uses *pci_read_config_word* for accessing such fields.
>
> I see. Adding an extra size argument is a good thing then,
> since it's consistent with the pci generic code.
>
> However, I still think that having defines for writel/readl is a
> good thing :)
sure, having defines is fine. How about something like below (readl, readw: to
differentiate 4byte and 2 byte access?)
#define dw_pcie_readl_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x4)
#define dw_pcie_readw_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x2)
Thanks
Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
2017-03-10 13:04 ` Kishon Vijay Abraham I
@ 2017-03-10 14:59 ` Niklas Cassel
0 siblings, 0 replies; 24+ messages in thread
From: Niklas Cassel @ 2017-03-10 14:59 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/10/2017 02:04 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 10 March 2017 06:26 PM, Niklas Cassel wrote:
>> On 03/10/2017 01:04 PM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Thursday 09 March 2017 08:18 PM, Niklas Cassel wrote:
>>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>>> Previously dbi accessors can be used to access data of size 4
>>>>> bytes. But there might be situations (like accessing
>>>>> MSI_MESSAGE_CONTROL in order to set/get the number of required
>>>>> MSI interrupts in EP mode) where dbi accessors must
>>>>> be used to access data of size 2. This is in preparation for
>>>>> adding endpoint mode support to designware driver.
>>>> Hello Kishon
>>>>
>>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>>> Will not a read/write of length != 32 be quite uncommon compared to
>>>> a read/write of length == 32?
>>>>
>>>> How about adding some defines to pcie-designware.h:
>>>>
>>>> #define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val)
>>>> #define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4)
>>>>
>>>> That way we don't have to change every existing read/write.
>>>>
>>>>
>>>>
>>>> Is there a reason why we can't just do:
>>>>
>>>> vial = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL);
>>> MSI_MESSAGE_CONTROL is 0x52 (MSI capability offset + 2). I'm not sure if we can
>>> do a readl that crosses the alignment boundary in all platforms. The other
>>> option is to readl from "MSI capability offset + 0" and extract the last 16
>>> bits. I felt this is more clear since we are interested only in the
>>> MSI_MESSAGE_CONTROL.
>>>
>>>> <shifting+masking the bits we need to get/set>
>>>> dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val);
>>>>
>>>> Or are we going to be doing read/writes of length != 32 so often that
>>>> you think that it's cleaner to have this abstraction?
>>> it's used mainly for accessing configuration space header fields. Even the pci
>>> core uses *pci_read_config_word* for accessing such fields.
>> I see. Adding an extra size argument is a good thing then,
>> since it's consistent with the pci generic code.
>>
>> However, I still think that having defines for writel/readl is a
>> good thing :)
> sure, having defines is fine. How about something like below (readl, readw: to
> differentiate 4byte and 2 byte access?)
>
> #define dw_pcie_readl_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x4)
> #define dw_pcie_readw_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x2)
Looks good to me.
But if we add readw, we might as well add readb :P
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 12:56 ` Kishon Vijay Abraham I
@ 2017-03-10 15:47 ` Niklas Cassel
2017-03-13 5:30 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 24+ messages in thread
From: Niklas Cassel @ 2017-03-10 15:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
On 03/10/2017 01:56 PM, Kishon Vijay Abraham I wrote:
> Hi Niklas,
>
> On Friday 10 March 2017 06:01 PM, Niklas Cassel wrote:
>> On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>>>> helper to access dbi address space can access only dbics. However
>>>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>>>> case of EP mode. This is in preparation for adding EP mode support
>>>>>> to dwc driver.
>>>>> Hello Kishon
>>>>>
>>>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>>>> using dbi?
>>>>>
>>>>> How about something like this:
>>>>>
>>>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>>>> {
>>>>> if (pci->ops->writel_dbi)
>>>>> pci->ops->writel_dbi(pci, base, reg, val);
>>>>> else
>>>>> writel(val, base + reg);
>>>>> }
>>>>>
>>>>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>>>>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>>>> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
>>>> so we can return an error if pci->dbi_base2 == NULL.
>>> Should we return an error? We don't return error for dbi_base either. I think
>>> it should be sufficient to return errors while populating dbi_base or
>>> dbi_base2. Otherwise it's a bug and should result in abort. Joao?
>> Sorry for previous empty email.
>>
>>
>> What I meant to write:
>>
>> Right now we do error checking for dbi_base in platform specific code
>> and in pcie-designware-host.c:dw_pcie_host_init.
> it's been done in dw_pcie_host_init not as an error checking but since it's
> *optional* for certain platforms to populate dbi_base (i.e where dbi_base is
> mapped to configuration space), host_init takes care of assigning dbi_base to
> configuration space address.
What I'm afraid of is that we might get a NULL ptr dereference
when using dw_pcie_writel_dbi2, if platform specific code has
not populated dbi_base2.
Having a NULL check in generic code is just a fail safe if some
platform specific code failed to NULL check.
The code in dw_pcie_host_init might have been written just
to populate dbi_base when dbi is mapped to config space,
but the end result is that if platform specific code did not
populate dbi_base (and did not populate pp->cfg),
we will return -ENOMEM.
Which means that we can never get a NULL ptr dereference
when using dw_pcie_writel_dbi.
It might be a good idea to have a NULL check in generic code,
just as a fail safe, also for dw_pcie_ep_init.
That way we know that we will not get a NULL ptr dereference
when using dw_pcie_writel_dbi2.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
2017-03-10 15:47 ` Niklas Cassel
@ 2017-03-13 5:30 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 24+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-13 5:30 UTC (permalink / raw)
To: Niklas Cassel, Bjorn Helgaas, Joao Pinto, linux-pci,
linux-kernel, linux-omap, linux-arm-kernel
Cc: nsekhar, Jingoo Han, Richard Zhu, Lucas Stach, Murali Karicheri,
Thomas Petazzoni, Jesper Nilsson, Zhou Wang, Gabriele Paoloni
Hi Niklas,
On Friday 10 March 2017 09:17 PM, Niklas Cassel wrote:
>
>
> On 03/10/2017 01:56 PM, Kishon Vijay Abraham I wrote:
>> Hi Niklas,
>>
>> On Friday 10 March 2017 06:01 PM, Niklas Cassel wrote:
>>> On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
>>>> Hi,
>>>>
>>>> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>>>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>>>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
>>>>>>> dwc has 2 dbi address space labeled dbics and dbics2. The existing
>>>>>>> helper to access dbi address space can access only dbics. However
>>>>>>> dbics2 has to be accessed for programming the BAR registers in the
>>>>>>> case of EP mode. This is in preparation for adding EP mode support
>>>>>>> to dwc driver.
>>>>>> Hello Kishon
>>>>>>
>>>>>> I don't really like the idea of adding an extra argument to every existing read/write.
>>>>>> Will not a read/write using dbi2 be quite uncommon compared to a read/write
>>>>>> using dbi?
>>>>>>
>>>>>> How about something like this:
>>>>>>
>>>>>> void __dw_pcie_writel(struct dw_pcie *pci, void __iomem *base, u32 reg, u32 val)
>>>>>> {
>>>>>> if (pci->ops->writel_dbi)
>>>>>> pci->ops->writel_dbi(pci, base, reg, val);
>>>>>> else
>>>>>> writel(val, base + reg);
>>>>>> }
>>>>>>
>>>>>> #define dw_pcie_writel_dbi(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base, reg, val)
>>>>>> #define dw_pcie_writel_dbi2(pci, reg, val) __dw_pcie_writel(pci, pci->dbi_base2, reg, val)
>>>>> Perhaps make dw_pcie_writel_dbi2 a function rather than a define,
>>>>> so we can return an error if pci->dbi_base2 == NULL.
>>>> Should we return an error? We don't return error for dbi_base either. I think
>>>> it should be sufficient to return errors while populating dbi_base or
>>>> dbi_base2. Otherwise it's a bug and should result in abort. Joao?
>>> Sorry for previous empty email.
>>>
>>>
>>> What I meant to write:
>>>
>>> Right now we do error checking for dbi_base in platform specific code
>>> and in pcie-designware-host.c:dw_pcie_host_init.
>> it's been done in dw_pcie_host_init not as an error checking but since it's
>> *optional* for certain platforms to populate dbi_base (i.e where dbi_base is
>> mapped to configuration space), host_init takes care of assigning dbi_base to
>> configuration space address.
>
> What I'm afraid of is that we might get a NULL ptr dereference
> when using dw_pcie_writel_dbi2, if platform specific code has
> not populated dbi_base2.
>
> Having a NULL check in generic code is just a fail safe if some
> platform specific code failed to NULL check.
>
> The code in dw_pcie_host_init might have been written just
> to populate dbi_base when dbi is mapped to config space,
> but the end result is that if platform specific code did not
> populate dbi_base (and did not populate pp->cfg),
> we will return -ENOMEM.
> Which means that we can never get a NULL ptr dereference
> when using dw_pcie_writel_dbi.
>
> It might be a good idea to have a NULL check in generic code,
> just as a fail safe, also for dw_pcie_ep_init.
> That way we know that we will not get a NULL ptr dereference
> when using dw_pcie_writel_dbi2.
All right, will add it then.
Thanks
Kishon
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2017-03-13 5:33 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-09 6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
2017-03-09 6:38 ` [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 3/7] PCI: dwc: artpec6: " Kishon Vijay Abraham I
2017-03-09 10:21 ` Niklas Cassel
2017-03-09 6:39 ` [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
2017-03-09 14:48 ` Niklas Cassel
2017-03-09 15:05 ` Niklas Cassel
2017-03-10 11:36 ` Kishon Vijay Abraham I
2017-03-10 12:23 ` Niklas Cassel
2017-03-10 12:30 ` Joao Pinto
2017-03-10 12:31 ` Niklas Cassel
2017-03-10 12:56 ` Kishon Vijay Abraham I
2017-03-10 15:47 ` Niklas Cassel
2017-03-13 5:30 ` Kishon Vijay Abraham I
2017-03-09 6:39 ` [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
2017-03-09 14:48 ` Niklas Cassel
2017-03-10 12:04 ` Kishon Vijay Abraham I
2017-03-10 12:56 ` Niklas Cassel
2017-03-10 13:04 ` Kishon Vijay Abraham I
2017-03-10 14:59 ` Niklas Cassel
2017-03-09 6:39 ` [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Kishon Vijay Abraham I
2017-03-09 12:25 ` Joao Pinto
2017-03-09 6:39 ` [RESEND PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I
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