From: Jacopo Mondi <jacopo+renesas@jmondi.org>
To: linus.walleij@linaro.org, geert+renesas@glider.be,
laurent.pinchart@ideasonboard.com, chris.brandt@renesas.com,
robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk
Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 04/10] dt-bindings: pinctrl: Add RZ/A1 bindings doc
Date: Thu, 27 Apr 2017 10:19:48 +0200 [thread overview]
Message-ID: <1493281194-5200-5-git-send-email-jacopo+renesas@jmondi.org> (raw)
In-Reply-To: <1493281194-5200-1-git-send-email-jacopo+renesas@jmondi.org>
Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
controller.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
.../bindings/pinctrl/renesas,rza1-pinctrl.txt | 219 +++++++++++++++++++++
1 file changed, 219 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
new file mode 100644
index 0000000..5a1106d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -0,0 +1,219 @@
+Renesas RZ/A1 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
+named "Ports" in the hardware reference manual.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis
+writing configuration values to per-port register sets.
+Each "port" features up to 16 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+-------------------
+
+Required properties:
+ - compatible
+ this shall be "renesas,r7s72100-ports".
+
+ - reg
+ address base and length of the memory area where the pin controller
+ hardware is mapped to.
+
+Example:
+Pin controller node for RZ/A1H SoC (r7s72100)
+
+pinctrl: pin-controller@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ reg = <0xfcfe3000 0x4230>;
+};
+
+Sub-nodes
+---------
+
+The child nodes of the pin controller node describe a pin multiplexing
+function or a GPIO controller alternatively.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ A single sub-node may define several pin configurations.
+ Some alternate functions require special pin configuration flags to be
+ supplied along with the alternate function configuration number.
+ When the hardware reference manual specifies a pin function to be either
+ "bi-directional" or "software IO driven", use the generic properties from
+ the <include/linux/pinctrl/pinconf_generic.h> header file to instruct the
+ pin controller to perform the desired pin configuration operations.
+ Please refer to pinctrl-bindings.txt to get to know more on generic
+ pin properties usage.
+
+ The allowed generic formats for a pin multiplexing sub-node are the
+ following ones:
+
+ node-1 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ node-2 {
+ sub-node-1 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ sub-node-2 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ ...
+
+ sub-node-n {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+ };
+
+ Use the second format when pins part of the same logical group need to have
+ different generic pin configuration flags applied.
+
+ Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
+ of the most external one.
+
+ Eg.
+
+ client-1 {
+ ...
+ pinctrl-0 = <&node-1>;
+ ...
+ };
+
+ client-2 {
+ ...
+ pinctrl-0 = <&node-2>;
+ ...
+ };
+
+ Required properties:
+ - pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+ <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 16 + PIN) | MUX_FUNC << 16)
+
+ Optional generic properties:
+ - bi-directional:
+ for pins requiring bi-directional operations.
+ - input-enable:
+ for pins requiring software driven IO input operations.
+ - output-enable:
+ for pins requiring software driven IO output operations.
+
+ The hardware reference manual specifies when a pin has to be configured to
+ work in bi-directional mode and when the IO direction has to be specified
+ by software.
+
+ Example:
+ A serial communication interface with a TX output pin and an RX input pin.
+
+ &pinctrl {
+ scif2_pins: serial2 {
+ pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
+ };
+ };
+
+ Pin #0 on port #3 is configured as alternate function #6.
+ Pin #2 on port #3 is configured as alternate function #4.
+
+ Example 2:
+ I2c master: both SDA and SCL pins need bi-directional operations
+
+ &pinctrl {
+ i2c2_pins: i2c2 {
+ pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
+ bi-directional;
+ };
+ };
+
+ Pin #4 on port #1 is configured as alternate function #1.
+ Pin #5 on port #1 is configured as alternate function #1.
+ Both need to work in bi-directional mode.
+
+ Example 3:
+ Multi-function timer input and output compare pins.
+ Configure TIOC0A as software driven input and TIOC0B as software driven
+ output.
+
+ &pinctrl {
+ tioc0_pins: tioc0 {
+ tioc0_input_pins {
+ pinumx = <RZA1_PINMUX(4, 0, 2)>;
+ input-enable;
+ };
+
+ tioc0_output_pins {
+ pinmux = <RZA1_PINMUX(4, 1, 1)>;
+ output-enable;
+ };
+ };
+ };
+
+
+ &tioc0 {
+ ...
+ pinctrl-0 = <&tioc0_pins>;
+ ...
+ };
+
+ Pin #0 on port #4 is configured as alternate function #2 with IO direction
+ specified by software as input.
+ Pin #1 on port #4 is configured as alternate function #1 with IO direction
+ specified by software as output.
+
+- GPIO controller sub-nodes:
+ Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
+ Different SoCs have different numbers of available pins per port, but
+ generally speaking, each of them can be configured in GPIO ("port") mode
+ on this hardware.
+ Describe GPIO controllers using sub-nodes with the following properties.
+
+ Required properties:
+ - gpio-controller
+ empty property as defined by the GPIO bindings documentation.
+ - #gpio-cells
+ number of cells required to identify and configure a GPIO.
+ Shall be 2.
+ - gpio-ranges
+ Describes a GPIO controller specifying its specific pin base, the pin
+ base in the global pin numbering space, and the number of controlled
+ pins, as defined by the GPIO bindings documentation. Refer to
+ Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
+ description.
+
+ Example:
+ A GPIO controller node, controlling 16 pins indexed from 0.
+ The GPIO controller base in the global pin indexing space is pin 48, thus
+ pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
+ indexing space.
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ A device node willing to use pins controlled by this GPIO controller, shall
+ refer to it as follows:
+
+ led1 {
+ gpios = <&port3 10 GPIO_ACTIVE_LOW>;
+ };
--
2.7.4
next prev parent reply other threads:[~2017-04-27 8:21 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-27 8:19 [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller Jacopo Mondi
2017-04-27 8:19 ` [PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable Jacopo Mondi
2017-04-27 14:56 ` Andy Shevchenko
2017-04-28 8:32 ` Linus Walleij
2017-04-28 10:09 ` Geert Uytterhoeven
2017-05-07 7:50 ` Linus Walleij
2017-04-28 12:07 ` Chris Brandt
2017-04-28 12:15 ` Andy Shevchenko
2017-04-28 13:18 ` Chris Brandt
2017-04-28 14:53 ` Andy Shevchenko
2017-04-28 15:16 ` Chris Brandt
2017-04-28 15:37 ` Andy Shevchenko
2017-04-28 16:46 ` Chris Brandt
2017-05-07 7:52 ` Linus Walleij
2017-05-08 16:01 ` jmondi
2017-05-08 16:08 ` Andy Shevchenko
2017-05-08 17:02 ` Chris Brandt
2017-05-08 18:26 ` Andy Shevchenko
2017-05-08 20:05 ` Chris Brandt
2017-05-08 17:25 ` jmondi
2017-05-08 17:47 ` Andy Shevchenko
2017-05-09 9:55 ` jmondi
2017-05-08 21:19 ` Linus Walleij
2017-05-09 10:54 ` Geert Uytterhoeven
2017-05-12 9:00 ` Linus Walleij
2017-05-12 9:04 ` Linus Walleij
2017-05-12 11:11 ` Geert Uytterhoeven
2017-05-12 12:13 ` Chris Brandt
2017-05-12 12:25 ` Geert Uytterhoeven
2017-05-12 12:57 ` Chris Brandt
2017-05-12 11:44 ` Chris Brandt
2017-05-23 10:08 ` Dong Aisheng
2017-05-23 18:37 ` jmondi
2017-05-29 8:45 ` Linus Walleij
2017-05-29 10:42 ` jmondi
2017-05-30 14:12 ` Chris Brandt
2017-06-09 7:26 ` Dong Aisheng
2017-06-09 7:50 ` jmondi
2017-06-11 21:45 ` Linus Walleij
2017-06-12 9:44 ` jmondi
2017-06-13 6:25 ` Dong Aisheng
2017-06-15 11:11 ` jmondi
2017-06-19 15:43 ` Dong Aisheng
2017-04-27 8:19 ` [PATCH v5 02/10] pinctrl: generic: Add macros to unpack properties Jacopo Mondi
2017-04-27 8:37 ` Geert Uytterhoeven
2017-04-28 8:16 ` Linus Walleij
2017-04-28 10:06 ` Geert Uytterhoeven
2017-04-28 12:49 ` jmondi
2017-04-28 16:23 ` Andy Shevchenko
2017-04-27 8:19 ` [PATCH v5 03/10] pinctrl: Renesas RZ/A1 pin and gpio controller Jacopo Mondi
2017-04-27 8:37 ` Geert Uytterhoeven
2017-04-27 8:19 ` Jacopo Mondi [this message]
2017-04-27 8:37 ` [PATCH v5 04/10] dt-bindings: pinctrl: Add RZ/A1 bindings doc Geert Uytterhoeven
2017-04-28 21:03 ` Rob Herring
2017-04-27 8:19 ` [PATCH v5 05/10] arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header Jacopo Mondi
2017-04-27 8:38 ` Geert Uytterhoeven
2017-04-28 5:19 ` Simon Horman
2017-04-27 8:19 ` [PATCH v5 06/10] arm: dts: r7s72100: Add pin controller node Jacopo Mondi
2017-04-27 8:19 ` [PATCH v5 07/10] arm: dts: genmai: Add SCIF2 pin group Jacopo Mondi
2017-04-28 5:21 ` Simon Horman
2017-04-27 8:19 ` [PATCH v5 08/10] arm: dts: genmai: Add RIIC2 " Jacopo Mondi
2017-04-27 8:19 ` [PATCH v5 09/10] arm: dts: genmai: Add user led device nodes Jacopo Mondi
2017-04-27 8:19 ` [PATCH v5 10/10] arm: dts: genmai: Add ethernet pin group Jacopo Mondi
2017-04-27 9:56 ` Geert Uytterhoeven
2017-04-27 10:48 ` Chris Brandt
2017-04-28 5:22 ` Simon Horman
2017-04-28 7:18 ` Geert Uytterhoeven
2017-04-28 14:48 ` Chris Brandt
2017-05-05 12:06 ` Linus Walleij
2017-05-05 12:20 ` Geert Uytterhoeven
2017-05-05 12:45 ` Chris Brandt
2017-05-11 13:48 ` Linus Walleij
2017-04-28 8:49 ` Linus Walleij
2017-04-28 13:50 ` Chris Brandt
2017-04-27 8:42 ` [PATCH v5 00/10] Renesas RZ/A1 pin and gpio controller Geert Uytterhoeven
2017-04-28 5:22 ` Simon Horman
2017-04-28 7:24 ` jmondi
2017-04-28 7:30 ` Geert Uytterhoeven
2017-04-28 7:31 ` Simon Horman
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