[PATCH 0/6] some fixups for Mediatek cpufreq driver

[PATCH 0/6] some fixups for Mediatek cpufreq driver

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

Hi,

The purpose of the series is
- (patch 1 to 3) to fix up current Mediatek cpufreq driver
can't work with the latest tree since one required CPU clock muxer missing
would cause the driver getting the resource fails when driver probe gets
called.
- (patch 4) to enable cpufreq feature on MT2701/MT7623 platform.
- (patch 5 to 6) to update the binding document to reflect
latest driver logic and add more examples guiding people how to apply for
Mediatek cpufreq driver.

Sean Wang (6):
  clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
  clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
  clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
  cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC
  dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to
    proper place
  dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document

 .../devicetree/bindings/clock/mt8173-cpu-dvfs.txt  |  83 -------
 .../bindings/cpufreq/cpufreq-mediatek.txt          | 247 +++++++++++++++++++++
 drivers/clk/mediatek/Makefile                      |   2 +-
 drivers/clk/mediatek/clk-cpumux.c                  | 120 ++++++++++
 drivers/clk/mediatek/clk-cpumux.h                  |  30 +++
 drivers/clk/mediatek/clk-mt2701.c                  |   8 +
 drivers/clk/mediatek/clk-mt8173.c                  |  23 ++
 drivers/cpufreq/Kconfig.arm                        |   4 +-
 drivers/cpufreq/mt8173-cpufreq.c                   |   2 +
 include/dt-bindings/clock/mt2701-clk.h             |   3 +-
 include/dt-bindings/clock/mt8173-clk.h             |   4 +-
 11 files changed, 438 insertions(+), 88 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
 create mode 100644 drivers/clk/mediatek/clk-cpumux.c
 create mode 100644 drivers/clk/mediatek/clk-cpumux.h

-- 
2.7.4

[PATCH 1/6] clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 drivers/clk/mediatek/Makefile     |   2 +-
 drivers/clk/mediatek/clk-cpumux.c | 120 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-cpumux.h |  30 ++++++++++
 3 files changed, 151 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/mediatek/clk-cpumux.c
 create mode 100644 drivers/clk/mediatek/clk-cpumux.h

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5c3afb8..2a755b5 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,4 @@
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
 obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
 obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
new file mode 100644
index 0000000..edd8e69
--- /dev/null
+++ b/drivers/clk/mediatek/clk-cpumux.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-cpumux.h"
+
+static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
+{
+	return container_of(_hw, struct mtk_clk_cpumux, hw);
+}
+
+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
+{
+	struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
+	int num_parents = clk_hw_get_num_parents(hw);
+	unsigned int val;
+
+	regmap_read(mux->regmap, mux->reg, &val);
+
+	val >>= mux->shift;
+	val &= mux->mask;
+
+	if (val >= num_parents)
+		return -EINVAL;
+
+	return val;
+}
+
+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
+	u32 mask, val;
+
+	val = index << mux->shift;
+	mask = mux->mask << mux->shift;
+
+	return regmap_update_bits(mux->regmap, mux->reg, mask, val);
+}
+
+static const struct clk_ops clk_cpumux_ops = {
+	.get_parent = clk_cpumux_get_parent,
+	.set_parent = clk_cpumux_set_parent,
+};
+
+static struct clk __init *
+mtk_clk_register_cpumux(const struct mtk_composite *mux,
+			struct regmap *regmap)
+{
+	struct mtk_clk_cpumux *cpumux;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
+	if (!cpumux)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = mux->name;
+	init.ops = &clk_cpumux_ops;
+	init.parent_names = mux->parent_names;
+	init.num_parents = mux->num_parents;
+	init.flags = mux->flags;
+
+	cpumux->reg = mux->mux_reg;
+	cpumux->shift = mux->mux_shift;
+	cpumux->mask = BIT(mux->mux_width) - 1;
+	cpumux->regmap = regmap;
+	cpumux->hw.init = &init;
+
+	clk = clk_register(NULL, &cpumux->hw);
+	if (IS_ERR(clk))
+		kfree(cpumux);
+
+	return clk;
+}
+
+int __init mtk_clk_register_cpumuxes(struct device_node *node,
+				     const struct mtk_composite *clks, int num,
+				     struct clk_onecell_data *clk_data)
+{
+	int i;
+	struct clk *clk;
+	struct regmap *regmap;
+
+	regmap = syscon_node_to_regmap(node);
+	if (IS_ERR(regmap)) {
+		pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
+		       PTR_ERR(regmap));
+		return PTR_ERR(regmap);
+	}
+
+	for (i = 0; i < num; i++) {
+		const struct mtk_composite *mux = &clks[i];
+
+		clk = mtk_clk_register_cpumux(mux, regmap);
+		if (IS_ERR(clk)) {
+			pr_err("Failed to register clk %s: %ld\n",
+			       mux->name, PTR_ERR(clk));
+			continue;
+		}
+
+		clk_data->clks[mux->id] = clk;
+	}
+
+	return 0;
+}
diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
new file mode 100644
index 0000000..dddaad5
--- /dev/null
+++ b/drivers/clk/mediatek/clk-cpumux.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DRV_CLK_CPUMUX_H
+#define __DRV_CLK_CPUMUX_H
+
+struct mtk_clk_cpumux {
+	struct clk_hw	hw;
+	struct regmap	*regmap;
+	u32		reg;
+	u32		mask;
+	u8		shift;
+};
+
+int mtk_clk_register_cpumuxes(struct device_node *node,
+			      const struct mtk_composite *clks, int num,
+			      struct clk_onecell_data *clk_data);
+
+#endif /* __DRV_CLK_CPUMUX_H */
-- 
2.7.4

[PATCH 2/6] clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701.c      | 8 ++++++++
 include/dt-bindings/clock/mt2701-clk.h | 3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 6f26e6a..9598889 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -20,6 +20,7 @@
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
+#include "clk-cpumux.h"
 
 #include <dt-bindings/clock/mt2701-clk.h>
 
@@ -493,6 +494,10 @@ static const char * const cpu_parents[] = {
 	"mmpll"
 };
 
+static const struct mtk_composite cpu_muxes[] __initconst = {
+	MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
+};
+
 static const struct mtk_composite top_muxes[] = {
 	MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 		0x0040, 0, 3, 7, CLK_IS_CRITICAL),
@@ -759,6 +764,9 @@ static void mtk_infrasys_init_early(struct device_node *node)
 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 						infra_clk_data);
 
+	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+				  infra_clk_data);
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 2062c67..551f760 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -221,7 +221,8 @@
 #define CLK_INFRA_PMICWRAP			17
 #define CLK_INFRA_DDCCI				18
 #define CLK_INFRA_CLK_13M			19
-#define CLK_INFRA_NR				20
+#define CLK_INFRA_CPUSEL                        20
+#define CLK_INFRA_NR				21
 
 /* PERICFG */
 
-- 
2.7.4

[PATCH 3/6] clk: mediatek: export cpu multiplexer clock for MT8173 SoCs

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c      | 23 +++++++++++++++++++++++
 include/dt-bindings/clock/mt8173-clk.h |  4 +++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 0ac3aee..96c292c 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -18,6 +18,7 @@
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
+#include "clk-cpumux.h"
 
 #include <dt-bindings/clock/mt8173-clk.h>
 
@@ -525,6 +526,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
 	"apll2_div5"
 };
 
+static const char * const ca53_parents[] __initconst = {
+	"clk26m",
+	"armca7pll",
+	"mainpll",
+	"univpll"
+};
+
+static const char * const ca57_parents[] __initconst = {
+	"clk26m",
+	"armca15pll",
+	"mainpll",
+	"univpll"
+};
+
+static const struct mtk_composite cpu_muxes[] __initconst = {
+	MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
+	MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
+};
+
 static const struct mtk_composite top_muxes[] __initconst = {
 	/* CLK_CFG_0 */
 	MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
@@ -948,6 +968,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
 						clk_data);
 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 
+	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+				  clk_data);
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 6094bf7..8aea623 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -193,7 +193,9 @@
 #define CLK_INFRA_PMICSPI		10
 #define CLK_INFRA_PMICWRAP		11
 #define CLK_INFRA_CLK_13M		12
-#define CLK_INFRA_NR_CLK		13
+#define CLK_INFRA_CA53SEL               13
+#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_NR_CLK                15
 
 /* PERI_SYS */
 
-- 
2.7.4

[PATCH 4/6] cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

MT2701/MT7623 is an 32-bit ARMv7 based quad-core (4 * Cortex-A7) with
single cluster and this hardware is also compatible with the existing
driver through enabling CPU frequency feature with operating-points-v2
bindings.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 drivers/cpufreq/Kconfig.arm      | 4 ++--
 drivers/cpufreq/mt8173-cpufreq.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 74ed7e9..68b387a 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -90,11 +90,11 @@ config ARM_KIRKWOOD_CPUFREQ
 config ARM_MT8173_CPUFREQ
 	tristate "Mediatek MT8173 CPUFreq support"
 	depends on ARCH_MEDIATEK && REGULATOR
-	depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
+	depends on (ARM || ARM64) || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
 	depends on !CPU_THERMAL || THERMAL
 	select PM_OPP
 	help
-	  This adds the CPUFreq driver support for Mediatek MT8173 SoC.
+	  This adds the CPUFreq driver support for Mediatek SoCs.
 
 config ARM_OMAP2PLUS_CPUFREQ
 	bool "TI OMAP2+"
diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c
index fd1886f..481ec77 100644
--- a/drivers/cpufreq/mt8173-cpufreq.c
+++ b/drivers/cpufreq/mt8173-cpufreq.c
@@ -575,6 +575,8 @@ static struct platform_driver mt8173_cpufreq_platdrv = {
 
 /* List of machines supported by this driver */
 static const struct of_device_id mt8173_cpufreq_machines[] __initconst = {
+	{ .compatible = "mediatek,mt2701", },
+	{ .compatible = "mediatek,mt7623", },
 	{ .compatible = "mediatek,mt817x", },
 	{ .compatible = "mediatek,mt8173", },
 	{ .compatible = "mediatek,mt8176", },
-- 
2.7.4

[PATCH 5/6] dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to proper place

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

The old place is Documentation/devicetree/bindings/clock/ that would
let people hard to find how to use Mediatek cpufreq driver, so moving
it to the new place as other cpufreq dirvers are done would be better.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 .../devicetree/bindings/clock/mt8173-cpu-dvfs.txt  | 83 ----------------------
 .../bindings/cpufreq/cpufreq-mediatek.txt          | 83 ++++++++++++++++++++++
 2 files changed, 83 insertions(+), 83 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

diff --git a/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt b/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
deleted file mode 100644
index 52b457c..0000000
--- a/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
-
-Required properties:
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-- clock-names: Should contain the following:
-	"cpu"		- The multiplexer for clock input of CPU cluster.
-	"intermediate"	- A parent of "cpu" clock which is used as "intermediate" clock
-			  source (usually MAINPLL) when the original CPU PLL is under
-			  transition and not stable yet.
-	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
-	generic clock consumer properties.
-- proc-supply: Regulator for Vproc of CPU cluster.
-
-Optional properties:
-- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
-	       needs to do "voltage tracking" to step by step scale up/down Vproc and
-	       Vsram to fit SoC specific needs. When absent, the voltage scaling
-	       flow is handled by hardware, hence no software "voltage tracking" is
-	       needed.
-
-Example:
---------
-	cpu0: cpu@0 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a53";
-		reg = <0x000>;
-		enable-method = "psci";
-		cpu-idle-states = <&CPU_SLEEP_0>;
-		clocks = <&infracfg CLK_INFRA_CA53SEL>,
-			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-		clock-names = "cpu", "intermediate";
-	};
-
-	cpu1: cpu@1 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a53";
-		reg = <0x001>;
-		enable-method = "psci";
-		cpu-idle-states = <&CPU_SLEEP_0>;
-		clocks = <&infracfg CLK_INFRA_CA53SEL>,
-			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-		clock-names = "cpu", "intermediate";
-	};
-
-	cpu2: cpu@100 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a57";
-		reg = <0x100>;
-		enable-method = "psci";
-		cpu-idle-states = <&CPU_SLEEP_0>;
-		clocks = <&infracfg CLK_INFRA_CA57SEL>,
-			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-		clock-names = "cpu", "intermediate";
-	};
-
-	cpu3: cpu@101 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a57";
-		reg = <0x101>;
-		enable-method = "psci";
-		cpu-idle-states = <&CPU_SLEEP_0>;
-		clocks = <&infracfg CLK_INFRA_CA57SEL>,
-			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-		clock-names = "cpu", "intermediate";
-	};
-
-	&cpu0 {
-		proc-supply = <&mt6397_vpca15_reg>;
-	};
-
-	&cpu1 {
-		proc-supply = <&mt6397_vpca15_reg>;
-	};
-
-	&cpu2 {
-		proc-supply = <&da9211_vcpu_reg>;
-		sram-supply = <&mt6397_vsramca7_reg>;
-	};
-
-	&cpu3 {
-		proc-supply = <&da9211_vcpu_reg>;
-		sram-supply = <&mt6397_vsramca7_reg>;
-	};
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
new file mode 100644
index 0000000..52b457c
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -0,0 +1,83 @@
+Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+	"cpu"		- The multiplexer for clock input of CPU cluster.
+	"intermediate"	- A parent of "cpu" clock which is used as "intermediate" clock
+			  source (usually MAINPLL) when the original CPU PLL is under
+			  transition and not stable yet.
+	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+	generic clock consumer properties.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+	       needs to do "voltage tracking" to step by step scale up/down Vproc and
+	       Vsram to fit SoC specific needs. When absent, the voltage scaling
+	       flow is handled by hardware, hence no software "voltage tracking" is
+	       needed.
+
+Example:
+--------
+	cpu0: cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x000>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_SLEEP_0>;
+		clocks = <&infracfg CLK_INFRA_CA53SEL>,
+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
+		clock-names = "cpu", "intermediate";
+	};
+
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x001>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_SLEEP_0>;
+		clocks = <&infracfg CLK_INFRA_CA53SEL>,
+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
+		clock-names = "cpu", "intermediate";
+	};
+
+	cpu2: cpu@100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x100>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_SLEEP_0>;
+		clocks = <&infracfg CLK_INFRA_CA57SEL>,
+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
+		clock-names = "cpu", "intermediate";
+	};
+
+	cpu3: cpu@101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x101>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_SLEEP_0>;
+		clocks = <&infracfg CLK_INFRA_CA57SEL>,
+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
+		clock-names = "cpu", "intermediate";
+	};
+
+	&cpu0 {
+		proc-supply = <&mt6397_vpca15_reg>;
+	};
+
+	&cpu1 {
+		proc-supply = <&mt6397_vpca15_reg>;
+	};
+
+	&cpu2 {
+		proc-supply = <&da9211_vcpu_reg>;
+		sram-supply = <&mt6397_vsramca7_reg>;
+	};
+
+	&cpu3 {
+		proc-supply = <&da9211_vcpu_reg>;
+		sram-supply = <&mt6397_vsramca7_reg>;
+	};
-- 
2.7.4

[PATCH 6/6] dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

Update binding document to reflect the lastest driver logic and
add more examples guiding people how to use Mediatek cpufreq driver.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 .../bindings/cpufreq/cpufreq-mediatek.txt          | 170 ++++++++++++++++++++-
 1 file changed, 167 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
index 52b457c..0703927 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -1,4 +1,5 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+Binding for Mediatek's CPUFreq driver
+=====================================
 
 Required properties:
 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
@@ -9,6 +10,8 @@ Required properties:
 			  transition and not stable yet.
 	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
 	generic clock consumer properties.
+- operating-points-v2: Pleaser refer to Documentation/devicetree/bindings/opp/opp.txt
+	for detail.
 - proc-supply: Regulator for Vproc of CPU cluster.
 
 Optional properties:
@@ -17,9 +20,166 @@ Optional properties:
 	       Vsram to fit SoC specific needs. When absent, the voltage scaling
 	       flow is handled by hardware, hence no software "voltage tracking" is
 	       needed.
+- #cooling-cells:
+- cooling-min-level:
+- cooling-max-level:
+	Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
+	for detail.
+
+Example 1 (MT7623 SoC):
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@598000000 {
+			opp-hz = /bits/ 64 <598000000>;
+			opp-microvolt = <1050000>;
+		};
+
+		opp@747500000 {
+			opp-hz = /bits/ 64 <747500000>;
+			opp-microvolt = <1050000>;
+		};
+
+		opp@1040000000 {
+			opp-hz = /bits/ 64 <1040000000>;
+			opp-microvolt = <1150000>;
+		};
+
+		opp@1196000000 {
+			opp-hz = /bits/ 64 <1196000000>;
+			opp-microvolt = <1200000>;
+		};
+
+		opp@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1300000>;
+		};
+	};
+
+	cpu0: cpu@0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x0>;
+		clocks = <&infracfg CLK_INFRA_CPUSEL>,
+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
+		clock-names = "cpu", "intermediate";
+		operating-points-v2 = <&cpu_opp_table>;
+		#cooling-cells = <2>;
+		cooling-min-level = <0>;
+		cooling-max-level = <7>;
+	};
+	cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x1>;
+		operating-points-v2 = <&cpu_opp_table>;
+	};
+	cpu@2 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x2>;
+		operating-points-v2 = <&cpu_opp_table>;
+	};
+	cpu@3 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x3>;
+		operating-points-v2 = <&cpu_opp_table>;
+	};
+
+Example 2 (MT8173 SoC):
+	cpu_opp_table_a: opp_table_a {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@507000000 {
+			opp-hz = /bits/ 64 <507000000>;
+			opp-microvolt = <859000>;
+		};
+
+		opp@702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-microvolt = <908000>;
+		};
+
+		opp@1001000000 {
+			opp-hz = /bits/ 64 <1001000000>;
+			opp-microvolt = <983000>;
+		};
+
+		opp@1105000000 {
+			opp-hz = /bits/ 64 <1105000000>;
+			opp-microvolt = <1009000>;
+		};
+
+		opp@1183000000 {
+			opp-hz = /bits/ 64 <1183000000>;
+			opp-microvolt = <1028000>;
+		};
+
+		opp@1404000000 {
+			opp-hz = /bits/ 64 <1404000000>;
+			opp-microvolt = <1083000>;
+		};
+
+		opp@1508000000 {
+			opp-hz = /bits/ 64 <1508000000>;
+			opp-microvolt = <1109000>;
+		};
+
+		opp@1573000000 {
+			opp-hz = /bits/ 64 <1573000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
+
+	cpu_opp_table_b: opp_table_b {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@507000000 {
+			opp-hz = /bits/ 64 <507000000>;
+			opp-microvolt = <828000>;
+		};
+
+		opp@702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-microvolt = <867000>;
+		};
+
+		opp@1001000000 {
+			opp-hz = /bits/ 64 <1001000000>;
+			opp-microvolt = <927000>;
+		};
+
+		opp@1209000000 {
+			opp-hz = /bits/ 64 <1209000000>;
+			opp-microvolt = <968000>;
+		};
+
+		opp@1404000000 {
+			opp-hz = /bits/ 64 <1007000000>;
+			opp-microvolt = <1028000>;
+		};
+
+		opp@1612000000 {
+			opp-hz = /bits/ 64 <1612000000>;
+			opp-microvolt = <1049000>;
+		};
+
+		opp@1807000000 {
+			opp-hz = /bits/ 64 <1807000000>;
+			opp-microvolt = <1089000>;
+		};
+
+		opp@1989000000 {
+			opp-hz = /bits/ 64 <1989000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
 
-Example:
---------
 	cpu0: cpu@0 {
 		device_type = "cpu";
 		compatible = "arm,cortex-a53";
@@ -29,6 +189,7 @@ Example:
 		clocks = <&infracfg CLK_INFRA_CA53SEL>,
 			 <&apmixedsys CLK_APMIXED_MAINPLL>;
 		clock-names = "cpu", "intermediate";
+		operating-points-v2 = <&cpu_opp_table_a>;
 	};
 
 	cpu1: cpu@1 {
@@ -40,6 +201,7 @@ Example:
 		clocks = <&infracfg CLK_INFRA_CA53SEL>,
 			 <&apmixedsys CLK_APMIXED_MAINPLL>;
 		clock-names = "cpu", "intermediate";
+		operating-points-v2 = <&cpu_opp_table_a>;
 	};
 
 	cpu2: cpu@100 {
@@ -51,6 +213,7 @@ Example:
 		clocks = <&infracfg CLK_INFRA_CA57SEL>,
 			 <&apmixedsys CLK_APMIXED_MAINPLL>;
 		clock-names = "cpu", "intermediate";
+		operating-points-v2 = <&cpu_opp_table_b>;
 	};
 
 	cpu3: cpu@101 {
@@ -62,6 +225,7 @@ Example:
 		clocks = <&infracfg CLK_INFRA_CA57SEL>,
 			 <&apmixedsys CLK_APMIXED_MAINPLL>;
 		clock-names = "cpu", "intermediate";
+		operating-points-v2 = <&cpu_opp_table_b>;
 	};
 
 	&cpu0 {
-- 
2.7.4

Re: [PATCH 4/6] cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC

[Jean Delvare]

Hi Sean,

On Fri, 5 May 2017 23:26:12 +0800, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> MT2701/MT7623 is an 32-bit ARMv7 based quad-core (4 * Cortex-A7) with
> single cluster and this hardware is also compatible with the existing
> driver through enabling CPU frequency feature with operating-points-v2
> bindings.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>  drivers/cpufreq/Kconfig.arm      | 4 ++--
>  drivers/cpufreq/mt8173-cpufreq.c | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 74ed7e9..68b387a 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -90,11 +90,11 @@ config ARM_KIRKWOOD_CPUFREQ
>  config ARM_MT8173_CPUFREQ
>  	tristate "Mediatek MT8173 CPUFreq support"
>  	depends on ARCH_MEDIATEK && REGULATOR
> -	depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
> +	depends on (ARM || ARM64) || (ARM_CPU_TOPOLOGY && COMPILE_TEST)

Parentheses not needed. I am also curious if ARM_CPU_TOPOLOGY can
actually be set when neither ARM nor ARM64 is. I suspect not, and then
the above can be simplified to just:

	depends on ARM || ARM64

>  	depends on !CPU_THERMAL || THERMAL
>  	select PM_OPP
>  	help
> -	  This adds the CPUFreq driver support for Mediatek MT8173 SoC.
> +	  This adds the CPUFreq driver support for Mediatek SoCs.

If this driver actually support all Mediatek SoCs, the menu entry
itself should be updated to drop "MT8173".

>  
>  config ARM_OMAP2PLUS_CPUFREQ
>  	bool "TI OMAP2+"
> diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c
> index fd1886f..481ec77 100644
> --- a/drivers/cpufreq/mt8173-cpufreq.c
> +++ b/drivers/cpufreq/mt8173-cpufreq.c
> @@ -575,6 +575,8 @@ static struct platform_driver mt8173_cpufreq_platdrv = {
>  
>  /* List of machines supported by this driver */
>  static const struct of_device_id mt8173_cpufreq_machines[] __initconst = {
> +	{ .compatible = "mediatek,mt2701", },
> +	{ .compatible = "mediatek,mt7623", },
>  	{ .compatible = "mediatek,mt817x", },
>  	{ .compatible = "mediatek,mt8173", },
>  	{ .compatible = "mediatek,mt8176", },


-- 
Jean Delvare
SUSE L3 Support

Re: [PATCH 5/6] dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to proper place

[Viresh Kumar]

On 05-05-17, 23:26, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> The old place is Documentation/devicetree/bindings/clock/ that would
> let people hard to find how to use Mediatek cpufreq driver, so moving
> it to the new place as other cpufreq dirvers are done would be better.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>  .../devicetree/bindings/clock/mt8173-cpu-dvfs.txt  | 83 ----------------------
>  .../bindings/cpufreq/cpufreq-mediatek.txt          | 83 ++++++++++++++++++++++
>  2 files changed, 83 insertions(+), 83 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
>  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

Please generate patches with:

git format-patch -C -M --thread=shallow

You would be required to resend this patch at least to let us see what has
changed.

-- 
viresh

Re: [PATCH 6/6] dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document

[Viresh Kumar]

On 05-05-17, 23:26, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> Update binding document to reflect the lastest driver logic and

The bindings don't follow the drivers but its the other way around. Don't
mention anything about the drivers in the bindings patches.

> add more examples guiding people how to use Mediatek cpufreq driver.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>  .../bindings/cpufreq/cpufreq-mediatek.txt          | 170 ++++++++++++++++++++-
>  1 file changed, 167 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> index 52b457c..0703927 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> @@ -1,4 +1,5 @@
> -Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
> +Binding for Mediatek's CPUFreq driver
> +=====================================
>  
>  Required properties:
>  - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
> @@ -9,6 +10,8 @@ Required properties:
>  			  transition and not stable yet.
>  	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
>  	generic clock consumer properties.
> +- operating-points-v2: Pleaser refer to Documentation/devicetree/bindings/opp/opp.txt
> +	for detail.
>  - proc-supply: Regulator for Vproc of CPU cluster.
>  
>  Optional properties:
> @@ -17,9 +20,166 @@ Optional properties:
>  	       Vsram to fit SoC specific needs. When absent, the voltage scaling
>  	       flow is handled by hardware, hence no software "voltage tracking" is
>  	       needed.
> +- #cooling-cells:
> +- cooling-min-level:
> +- cooling-max-level:
> +	Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
> +	for detail.
> +
> +Example 1 (MT7623 SoC):
> +
> +	cpu_opp_table: opp_table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@598000000 {

s/opp@/opp-/

-- 
viresh

Re: [PATCH 4/6] cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC

[Sean Wang]

Hi Jean,

Appreciate your reviewing and suggestion. I added my comment inline.

On Sat, 2017-05-06 at 10:00 +0200, Jean Delvare wrote:
> Hi Sean,
> 
> On Fri, 5 May 2017 23:26:12 +0800, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > MT2701/MT7623 is an 32-bit ARMv7 based quad-core (4 * Cortex-A7) with
> > single cluster and this hardware is also compatible with the existing
> > driver through enabling CPU frequency feature with operating-points-v2
> > bindings.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> >  drivers/cpufreq/Kconfig.arm      | 4 ++--
> >  drivers/cpufreq/mt8173-cpufreq.c | 2 ++
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index 74ed7e9..68b387a 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -90,11 +90,11 @@ config ARM_KIRKWOOD_CPUFREQ
> >  config ARM_MT8173_CPUFREQ
> >  	tristate "Mediatek MT8173 CPUFreq support"
> >  	depends on ARCH_MEDIATEK && REGULATOR
> > -	depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
> > +	depends on (ARM || ARM64) || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
> 
> Parentheses not needed. I am also curious if ARM_CPU_TOPOLOGY can
> actually be set when neither ARM nor ARM64 is. I suspect not, and then
> the above can be simplified to just:
> 

I agree with you and I will look into more whether ARM_CPU_TOPOLOGY can
be removed safely since I can't make fully sure here and then update
those into the next version.

> 	depends on ARM || ARM64
> 
> >  	depends on !CPU_THERMAL || THERMAL
> >  	select PM_OPP
> >  	help
> > -	  This adds the CPUFreq driver support for Mediatek MT8173 SoC.
> > +	  This adds the CPUFreq driver support for Mediatek SoCs.
> 
> If this driver actually support all Mediatek SoCs, the menu entry
> itself should be updated to drop "MT8173".
> 

I will drop MT8173 wording because the driver also works for those
Mediatek SoCs not belonged to MT817x series.

In fact, the driver should also be extended and being more generic to
support more Mediatek SoCs in the future.

> >  
> >  config ARM_OMAP2PLUS_CPUFREQ
> >  	bool "TI OMAP2+"
> > diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c
> > index fd1886f..481ec77 100644
> > --- a/drivers/cpufreq/mt8173-cpufreq.c
> > +++ b/drivers/cpufreq/mt8173-cpufreq.c
> > @@ -575,6 +575,8 @@ static struct platform_driver mt8173_cpufreq_platdrv = {
> >  
> >  /* List of machines supported by this driver */
> >  static const struct of_device_id mt8173_cpufreq_machines[] __initconst = {
> > +	{ .compatible = "mediatek,mt2701", },
> > +	{ .compatible = "mediatek,mt7623", },
> >  	{ .compatible = "mediatek,mt817x", },
> >  	{ .compatible = "mediatek,mt8173", },
> >  	{ .compatible = "mediatek,mt8176", },
> 
> 

Re: [PATCH 5/6] dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to proper place

[Sean Wang]

On Mon, 2017-05-08 at 09:48 +0530, Viresh Kumar wrote:
> On 05-05-17, 23:26, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > The old place is Documentation/devicetree/bindings/clock/ that would
> > let people hard to find how to use Mediatek cpufreq driver, so moving
> > it to the new place as other cpufreq dirvers are done would be better.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> >  .../devicetree/bindings/clock/mt8173-cpu-dvfs.txt  | 83 ----------------------
> >  .../bindings/cpufreq/cpufreq-mediatek.txt          | 83 ++++++++++++++++++++++
> >  2 files changed, 83 insertions(+), 83 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
> >  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> 
> Please generate patches with:
> 
> git format-patch -C -M --thread=shallow
> 
> You would be required to resend this patch at least to let us see what has
> changed.
> 

Hi Viresh,

Okay, I will do it with you provided command again. 

What I did for the patch is just "git mv
Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt"
and no any changing data in the content.

thanks for your feedback

	Sean

Re: [PATCH 6/6] dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document

[Sean Wang]

On Mon, 2017-05-08 at 09:50 +0530, Viresh Kumar wrote:
> On 05-05-17, 23:26, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > Update binding document to reflect the lastest driver logic and
> 
> The bindings don't follow the drivers but its the other way around. Don't
> mention anything about the drivers in the bindings patches.


Okay. I made a mistake: DT bindings shouldn't reference drivers and they
are OS-agnostic. I will correct them with the principle. 

Thanks for your patience and guidance 


> > add more examples guiding people how to use Mediatek cpufreq driver.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> >  .../bindings/cpufreq/cpufreq-mediatek.txt          | 170 ++++++++++++++++++++-
> >  1 file changed, 167 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> > index 52b457c..0703927 100644
> > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> > @@ -1,4 +1,5 @@
> > -Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
> > +Binding for Mediatek's CPUFreq driver
> > +=====================================
> >  
> >  Required properties:
> >  - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
> > @@ -9,6 +10,8 @@ Required properties:
> >  			  transition and not stable yet.
> >  	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
> >  	generic clock consumer properties.
> > +- operating-points-v2: Pleaser refer to Documentation/devicetree/bindings/opp/opp.txt
> > +	for detail.
> >  - proc-supply: Regulator for Vproc of CPU cluster.
> >  
> >  Optional properties:
> > @@ -17,9 +20,166 @@ Optional properties:
> >  	       Vsram to fit SoC specific needs. When absent, the voltage scaling
> >  	       flow is handled by hardware, hence no software "voltage tracking" is
> >  	       needed.
> > +- #cooling-cells:
> > +- cooling-min-level:
> > +- cooling-max-level:
> > +	Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
> > +	for detail.
> > +
> > +Example 1 (MT7623 SoC):
> > +
> > +	cpu_opp_table: opp_table {
> > +		compatible = "operating-points-v2";
> > +		opp-shared;
> > +
> > +		opp@598000000 {
> 
> s/opp@/opp-/

I have referred to other dt-binding as examples where they also use opp@
as the prefix word.  e.g bindings/cpufreq/ti-cpufreq.txt did it.

Or I misunderstand something you pointed out here ?












> 

Re: [PATCH 6/6] dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document

[Viresh Kumar]

On 08-05-17, 14:58, Sean Wang wrote:
> > > +		opp@598000000 {
> > 
> > s/opp@/opp-/
> 
> I have referred to other dt-binding as examples where they also use opp@
> as the prefix word.  e.g bindings/cpufreq/ti-cpufreq.txt did it.
> 
> Or I misunderstand something you pointed out here ?

Its on the way:

https://marc.info/?l=linux-kernel&m=149266711829469&w=2

-- 
viresh

Re: [PATCH 5/6] dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to proper place

[Viresh Kumar]

On 08-05-17, 14:19, Sean Wang wrote:
> Okay, I will do it with you provided command again. 
> 
> What I did for the patch is just "git mv
> Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
> Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt"
> and no any changing data in the content.

I was quite sure that you have done exactly that, but then we are
supposed to review and make sure you haven't done any mistakes.

That's where those options would make our life easier. Look at the
patch created by that command and you wouldn't see any diff at all.

-- 
viresh

Re: [PATCH 1/6] clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work

[Sean Wang]

Hi Michael and Stephen


Just a gentle ping on this one :)


Cheers, Sean


On Fri, 2017-05-05 at 23:26 +0800, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> This patch adds CPU multiplexer clocks which are essential for Mediatek
> cpufreq driver. It would use the CPU clock multiplexer to switch to the
> intermediate clock source temporarily and then wait for the primary clock
> changing getting stable.
> 
> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>  drivers/clk/mediatek/Makefile     |   2 +-
>  drivers/clk/mediatek/clk-cpumux.c | 120 ++++++++++++++++++++++++++++++++++++++
>  drivers/clk/mediatek/clk-cpumux.h |  30 ++++++++++
>  3 files changed, 151 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/mediatek/clk-cpumux.c
>  create mode 100644 drivers/clk/mediatek/clk-cpumux.h
> 
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 5c3afb8..2a755b5 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,4 +1,4 @@
> -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
> +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
>  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
>  obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
>  obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
> diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
> new file mode 100644
> index 0000000..edd8e69
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-cpumux.c
> @@ -0,0 +1,120 @@
> +/*
> + * Copyright (c) 2015 Linaro Ltd.
> + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/slab.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-cpumux.h"
> +
> +static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
> +{
> +	return container_of(_hw, struct mtk_clk_cpumux, hw);
> +}
> +
> +static u8 clk_cpumux_get_parent(struct clk_hw *hw)
> +{
> +	struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
> +	int num_parents = clk_hw_get_num_parents(hw);
> +	unsigned int val;
> +
> +	regmap_read(mux->regmap, mux->reg, &val);
> +
> +	val >>= mux->shift;
> +	val &= mux->mask;
> +
> +	if (val >= num_parents)
> +		return -EINVAL;
> +
> +	return val;
> +}
> +
> +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
> +	u32 mask, val;
> +
> +	val = index << mux->shift;
> +	mask = mux->mask << mux->shift;
> +
> +	return regmap_update_bits(mux->regmap, mux->reg, mask, val);
> +}
> +
> +static const struct clk_ops clk_cpumux_ops = {
> +	.get_parent = clk_cpumux_get_parent,
> +	.set_parent = clk_cpumux_set_parent,
> +};
> +
> +static struct clk __init *
> +mtk_clk_register_cpumux(const struct mtk_composite *mux,
> +			struct regmap *regmap)
> +{
> +	struct mtk_clk_cpumux *cpumux;
> +	struct clk *clk;
> +	struct clk_init_data init;
> +
> +	cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
> +	if (!cpumux)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = mux->name;
> +	init.ops = &clk_cpumux_ops;
> +	init.parent_names = mux->parent_names;
> +	init.num_parents = mux->num_parents;
> +	init.flags = mux->flags;
> +
> +	cpumux->reg = mux->mux_reg;
> +	cpumux->shift = mux->mux_shift;
> +	cpumux->mask = BIT(mux->mux_width) - 1;
> +	cpumux->regmap = regmap;
> +	cpumux->hw.init = &init;
> +
> +	clk = clk_register(NULL, &cpumux->hw);
> +	if (IS_ERR(clk))
> +		kfree(cpumux);
> +
> +	return clk;
> +}
> +
> +int __init mtk_clk_register_cpumuxes(struct device_node *node,
> +				     const struct mtk_composite *clks, int num,
> +				     struct clk_onecell_data *clk_data)
> +{
> +	int i;
> +	struct clk *clk;
> +	struct regmap *regmap;
> +
> +	regmap = syscon_node_to_regmap(node);
> +	if (IS_ERR(regmap)) {
> +		pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
> +		       PTR_ERR(regmap));
> +		return PTR_ERR(regmap);
> +	}
> +
> +	for (i = 0; i < num; i++) {
> +		const struct mtk_composite *mux = &clks[i];
> +
> +		clk = mtk_clk_register_cpumux(mux, regmap);
> +		if (IS_ERR(clk)) {
> +			pr_err("Failed to register clk %s: %ld\n",
> +			       mux->name, PTR_ERR(clk));
> +			continue;
> +		}
> +
> +		clk_data->clks[mux->id] = clk;
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
> new file mode 100644
> index 0000000..dddaad5
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-cpumux.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright (c) 2015 Linaro Ltd.
> + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __DRV_CLK_CPUMUX_H
> +#define __DRV_CLK_CPUMUX_H
> +
> +struct mtk_clk_cpumux {
> +	struct clk_hw	hw;
> +	struct regmap	*regmap;
> +	u32		reg;
> +	u32		mask;
> +	u8		shift;
> +};
> +
> +int mtk_clk_register_cpumuxes(struct device_node *node,
> +			      const struct mtk_composite *clks, int num,
> +			      struct clk_onecell_data *clk_data);
> +
> +#endif /* __DRV_CLK_CPUMUX_H */

Re: [PATCH 1/6] clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work

[Stephen Boyd]

On 05/05, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> This patch adds CPU multiplexer clocks which are essential for Mediatek
> cpufreq driver. It would use the CPU clock multiplexer to switch to the
> intermediate clock source temporarily and then wait for the primary clock
> changing getting stable.
> 
> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/6] clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs

[Stephen Boyd]

On 05/05, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
> up cpufreq driver fails at acquiring intermediate clock source when driver
> probe is called.
> 
> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 3/6] clk: mediatek: export cpu multiplexer clock for MT8173 SoCs

[Stephen Boyd]

On 05/05, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
> cpufreq driver fails at acquiring intermediate clock source when driver
> probe is called.
> 
> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project