* [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller
@ 2017-07-20 5:34 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
v3:
PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incoporate Stan's feedback:-
- Add SoC Wrapper and Synopsys Core IP versions
v2:
dt-bindings: phy: qmp: Add output-clock-names
Added Rob H's Ack
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Removed example
Added IPQ8074 specific details
phy: qcom-qmp: Fix phy pipe clock name
Added Vivek's Ack
phy: qcom-qmp: Handle unavailable registers
No changes
phy: qcom-qmp: Add support for IPQ8074
No changes
PCI: dwc: qcom: Use block IP version for operations
Added new patch to use block IP version instead of v1, v2...
dt-bindings: pci: qcom: Add support for IPQ8074
Removed example
Added IPQ8074 specific details
PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Incorporated Bjorn's feedback:-
- Removed reset names, helper function to assert/deassert, helper
function to R/M/W register.
- Renamed sys_noc clock as iface clock
- Added deinit if phy power on fails
v1:
Add definitions required to enable QMP phy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (8):
dt-bindings: phy: qmp: Add output-clock-names
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
phy: qcom-qmp: Fix phy pipe clock name
phy: qcom-qmp: Handle unavailable registers
phy: qcom-qmp: Add support for IPQ8074
PCI: dwc: qcom: Use block IP version for operations
dt-bindings: pci: qcom: Add support for IPQ8074
PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
.../devicetree/bindings/pci/qcom,pcie.txt | 23 ++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 11 +
drivers/pci/dwc/pcie-qcom.c | 378 +++++++++++++++++----
drivers/phy/qualcomm/phy-qcom-qmp.c | 186 ++++++++--
4 files changed, 515 insertions(+), 83 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 2/8] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 Varadarajan Narayanan
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index e11c563..5d7a51f 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -60,6 +60,8 @@ Required properties for child node:
one for each entry in clock-names.
- clock-names: Must contain following for pcie and usb qmp phys:
"pipe<lane-number>" for pipe clock specific to each lane.
+ - clock-output-names: Name of the phy clock that will be the parent for
+ the above pipe clock.
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
@@ -96,6 +98,7 @@ Example:
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+ clock-output-names = "pcie_0_pipe_clk_src";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/8] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d7a51f..82fe0c4 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
Required properties:
- compatible: compatible list, contains:
+ "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,ipq8074-qmp-pcie-phy" must contain:
+ "phy", "phy_phy".
- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
- clock-output-names: Name of the phy clock that will be the parent for
the above pipe clock.
+ For "qcom,ipq8074-qmp-pcie-phy":
+ - "pcie20_phy0_pipe_clk" Pipe Clock parent
+ (or)
+ "pcie20_phy1_pipe_clk"
+
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
- reset-names: Must contain following for pcie qmp phys:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 2/8] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-21 8:01 ` Vivek Gautam
2017-07-20 5:34 ` [PATCH v3 4/8] phy: qcom-qmp: Handle unavailable registers Varadarajan Narayanan
` (4 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.
Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..97020ec 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -925,20 +925,13 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
* clk | +-------+ | +-----+
* +---------------+
*/
-static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
+static int phy_pipe_clk_register(struct qcom_qmp *qmp, const char *clk_name)
{
- char name[24];
struct clk_fixed_rate *fixed;
struct clk_init_data init = { };
- switch (qmp->cfg->type) {
- case PHY_TYPE_USB3:
- snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src");
- break;
- case PHY_TYPE_PCIE:
- snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id);
- break;
- default:
+ if ((qmp->cfg->type != PHY_TYPE_USB3) &&
+ (qmp->cfg->type != PHY_TYPE_PCIE)) {
/* not all phys register pipe clocks, so return success */
return 0;
}
@@ -947,7 +940,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
if (!fixed)
return -ENOMEM;
- init.name = name;
+ init.name = clk_name;
init.ops = &clk_fixed_rate_ops;
/* controllers using QMP phys use 125MHz pipe clock interface */
@@ -1110,6 +1103,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
id = 0;
for_each_available_child_of_node(dev->of_node, child) {
+ const char *clk_name;
+
/* Create per-lane phy */
ret = qcom_qmp_phy_create(dev, child, id);
if (ret) {
@@ -1118,11 +1113,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
return ret;
}
+ ret = of_property_read_string(child, "clock-output-names",
+ &clk_name);
+ if (ret) {
+ dev_err(dev,
+ "failed to get clock-output-names for lane%d phy, %d\n",
+ id, ret);
+ return ret;
+ }
+
/*
* Register the pipe clock provided by phy.
* See function description to see details of this pipe clock.
*/
- ret = phy_pipe_clk_register(qmp, id);
+ ret = phy_pipe_clk_register(qmp, clk_name);
if (ret) {
dev_err(qmp->dev,
"failed to register pipe clock source\n");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/8] phy: qcom-qmp: Handle unavailable registers
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
` (2 preceding siblings ...)
2017-07-20 5:34 ` [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 5/8] phy: qcom-qmp: Add support for IPQ8074 Varadarajan Narayanan
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
In some implementations of the QMP phy, some registers might not
be present. Provide a way identify such registers and not access
those registers.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 97020ec..000ad1c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -187,6 +187,8 @@ struct qmp_phy_init_tbl {
.in_layout = 1, \
}
+#define QPHY_REG_INVAL 0xffffffffu
+
/* set of registers with offsets different per-PHY */
enum qphy_reg_layout {
/* Common block control registers */
@@ -676,15 +678,18 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
SERDES_START | PCS_START);
- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
- mask = cfg->mask_com_pcs_ready;
-
- ret = readl_poll_timeout(status, val, (val & mask), 10,
- PHY_INIT_COMPLETE_TIMEOUT);
- if (ret) {
- dev_err(qmp->dev,
- "phy common block init timed-out\n");
- goto err_com_init;
+ if (cfg->regs[QPHY_COM_PCS_READY_STATUS] != QPHY_REG_INVAL) {
+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
+ mask = cfg->mask_com_pcs_ready;
+
+ ret = readl_poll_timeout(status, val, (val & mask), 10,
+ PHY_INIT_COMPLETE_TIMEOUT);
+ if (ret) {
+ dev_err(qmp->dev,
+ "%s: phy common block init timed-out\n",
+ __func__);
+ goto err_com_init;
+ }
}
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 5/8] phy: qcom-qmp: Add support for IPQ8074
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
` (3 preceding siblings ...)
2017-07-20 5:34 ` [PATCH v3 4/8] phy: qcom-qmp: Handle unavailable registers Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 6/8] PCI: dwc: qcom: Use block IP version for operations Varadarajan Narayanan
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan, smuthayy
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy <smuthayy@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 135 ++++++++++++++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 000ad1c..9019f66 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -59,6 +59,7 @@
#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
#define QSERDES_COM_RESETSM_CNTRL 0x0b4
#define QSERDES_COM_RESTRIM_CTRL 0x0bc
@@ -143,6 +144,11 @@
#define QPHY_LOCK_DETECT_CONFIG3 0x88
#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
+#define QPHY_OSC_DTCT_ACTIONS 0x1AC
+#define QPHY_RX_SIGDET_LVL 0x1D8
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
@@ -224,6 +230,17 @@ enum qphy_reg_layout {
[QPHY_PCS_READY_STATUS] = 0x174,
};
+static const unsigned int ipq8074_pciephy_regs_layout[] = {
+ [QPHY_COM_SW_RESET] = 0x800,
+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x804,
+ [QPHY_COM_START_CONTROL] = 0x808,
+ [QPHY_COM_PCS_READY_STATUS] = QPHY_REG_INVAL,
+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
+ [QPHY_SW_RESET] = 0x00,
+ [QPHY_START_CTRL] = 0x08,
+ [QPHY_PCS_READY_STATUS] = 0x174,
+};
+
static const unsigned int usb3phy_regs_layout[] = {
[QPHY_FLL_CNTRL1] = 0xc0,
[QPHY_FLL_CNTRL2] = 0xc4,
@@ -582,6 +599,121 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
.mask_pcs_ready = PHYSTATUS,
};
+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
+};
+
+/* list of resets */
+static const char * const ipq8074_pciephy_reset_l[] = {
+ "phy", "phy_phy",
+};
+
+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
+ .tx_tbl = ipq8074_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
+ .rx_tbl = ipq8074_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
+ .clk_list = NULL,
+ .num_clks = 0,
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = ipq8074_pciephy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .mask_pcs_ready = PHYSTATUS,
+
+ .has_phy_com_ctrl = true,
+ .has_lane_rst = false,
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
static void qcom_qmp_phy_configure(void __iomem *base,
const unsigned int *regs,
const struct qmp_phy_init_tbl tbl[],
@@ -1047,6 +1179,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
}, {
.compatible = "qcom,msm8996-qmp-usb3-phy",
.data = &msm8996_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
+ .data = &ipq8074_pciephy_cfg,
},
{ },
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 6/8] PCI: dwc: qcom: Use block IP version for operations
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
` (4 preceding siblings ...)
2017-07-20 5:34 ` [PATCH v3 5/8] phy: qcom-qmp: Add support for IPQ8074 Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 7/8] dt-bindings: pci: qcom: Add support for IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 8/8] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller Varadarajan Narayanan
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 124 ++++++++++++++++++++++----------------------
1 file changed, 62 insertions(+), 62 deletions(-)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index d15657d..98c74d7 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -61,7 +61,7 @@
#define PERST_DELAY_US 1000
-struct qcom_pcie_resources_v0 {
+struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
@@ -75,7 +75,7 @@ struct qcom_pcie_resources_v0 {
struct regulator *vdda_refclk;
};
-struct qcom_pcie_resources_v1 {
+struct qcom_pcie_resources_1_0_0 {
struct clk *iface;
struct clk *aux;
struct clk *master_bus;
@@ -84,7 +84,7 @@ struct qcom_pcie_resources_v1 {
struct regulator *vdda;
};
-struct qcom_pcie_resources_v2 {
+struct qcom_pcie_resources_2_3_2 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -92,7 +92,7 @@ struct qcom_pcie_resources_v2 {
struct clk *pipe_clk;
};
-struct qcom_pcie_resources_v3 {
+struct qcom_pcie_resources_2_4_0 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
@@ -111,10 +111,10 @@ struct qcom_pcie_resources_v3 {
};
union qcom_pcie_resources {
- struct qcom_pcie_resources_v0 v0;
- struct qcom_pcie_resources_v1 v1;
- struct qcom_pcie_resources_v2 v2;
- struct qcom_pcie_resources_v3 v3;
+ struct qcom_pcie_resources_1_0_0 v1_0_0;
+ struct qcom_pcie_resources_2_1_0 v2_1_0;
+ struct qcom_pcie_resources_2_3_2 v2_3_2;
+ struct qcom_pcie_resources_2_4_0 v2_4_0;
};
struct qcom_pcie;
@@ -172,7 +172,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
return dw_pcie_wait_for_link(pci);
}
-static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
+static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
{
u32 val;
@@ -182,9 +182,9 @@ static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
}
-static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
@@ -232,9 +232,9 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
return PTR_ERR_OR_ZERO(res->phy_reset);
}
-static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
@@ -249,9 +249,9 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
regulator_disable(res->vdda_refclk);
}
-static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
+static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
u32 val;
@@ -367,9 +367,9 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
return ret;
}
-static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+ struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
@@ -397,9 +397,9 @@ static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
return PTR_ERR_OR_ZERO(res->core);
}
-static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+ struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
reset_control_assert(res->core);
clk_disable_unprepare(res->slave_bus);
@@ -409,9 +409,9 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
regulator_disable(res->vdda);
}
-static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
+static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+ struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
int ret;
@@ -477,7 +477,7 @@ static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
return ret;
}
-static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
+static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
{
u32 val;
@@ -487,9 +487,9 @@ static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
writel(val, pcie->parf + PCIE20_PARF_LTSSM);
}
-static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
+ struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
@@ -513,9 +513,9 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
return PTR_ERR_OR_ZERO(res->pipe_clk);
}
-static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
+ struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
clk_disable_unprepare(res->pipe_clk);
clk_disable_unprepare(res->slave_clk);
@@ -524,9 +524,9 @@ static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
clk_disable_unprepare(res->aux_clk);
}
-static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
+static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
+ struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
u32 val;
@@ -589,9 +589,9 @@ static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
return ret;
}
-static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
+static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
+ struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
int ret;
@@ -605,9 +605,9 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
return 0;
}
-static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)
+static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
+ struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
@@ -674,9 +674,9 @@ static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)
return 0;
}
-static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)
+static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
+ struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
reset_control_assert(res->axi_m_reset);
reset_control_assert(res->axi_s_reset);
@@ -692,9 +692,9 @@ static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)
clk_disable_unprepare(res->slave_clk);
}
-static int qcom_pcie_init_v3(struct qcom_pcie *pcie)
+static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
{
- struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
+ struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
u32 val;
@@ -952,37 +952,37 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
.rd_own_conf = qcom_pcie_rd_own_conf,
};
-static const struct qcom_pcie_ops ops_v0 = {
- .get_resources = qcom_pcie_get_resources_v0,
- .init = qcom_pcie_init_v0,
- .deinit = qcom_pcie_deinit_v0,
- .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
+static const struct qcom_pcie_ops ops_2_1_0 = {
+ .get_resources = qcom_pcie_get_resources_2_1_0,
+ .init = qcom_pcie_init_2_1_0,
+ .deinit = qcom_pcie_deinit_2_1_0,
+ .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
};
-static const struct qcom_pcie_ops ops_v1 = {
- .get_resources = qcom_pcie_get_resources_v1,
- .init = qcom_pcie_init_v1,
- .deinit = qcom_pcie_deinit_v1,
- .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
+static const struct qcom_pcie_ops ops_1_0_0 = {
+ .get_resources = qcom_pcie_get_resources_1_0_0,
+ .init = qcom_pcie_init_1_0_0,
+ .deinit = qcom_pcie_deinit_1_0_0,
+ .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
};
-static const struct qcom_pcie_ops ops_v2 = {
- .get_resources = qcom_pcie_get_resources_v2,
- .init = qcom_pcie_init_v2,
- .post_init = qcom_pcie_post_init_v2,
- .deinit = qcom_pcie_deinit_v2,
- .ltssm_enable = qcom_pcie_v2_ltssm_enable,
+static const struct qcom_pcie_ops ops_2_3_2 = {
+ .get_resources = qcom_pcie_get_resources_2_3_2,
+ .init = qcom_pcie_init_2_3_2,
+ .post_init = qcom_pcie_post_init_2_3_2,
+ .deinit = qcom_pcie_deinit_2_3_2,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
};
-static const struct qcom_pcie_ops ops_v3 = {
- .get_resources = qcom_pcie_get_resources_v3,
- .init = qcom_pcie_init_v3,
- .deinit = qcom_pcie_deinit_v3,
- .ltssm_enable = qcom_pcie_v2_ltssm_enable,
+static const struct qcom_pcie_ops ops_2_4_0 = {
+ .get_resources = qcom_pcie_get_resources_2_4_0,
+ .init = qcom_pcie_init_2_4_0,
+ .deinit = qcom_pcie_deinit_2_4_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
static int qcom_pcie_probe(struct platform_device *pdev)
@@ -1071,11 +1071,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_pcie_match[] = {
- { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
- { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
- { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
- { .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
- { .compatible = "qcom,pcie-ipq4019", .data = &ops_v3 },
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
+ { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
{ }
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 7/8] dt-bindings: pci: qcom: Add support for IPQ8074
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
` (5 preceding siblings ...)
2017-07-20 5:34 ` [PATCH v3 6/8] PCI: dwc: qcom: Use block IP version for operations Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 8/8] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller Varadarajan Narayanan
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 9d418b7..b3e36ef 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+ - "qcom,pcie-ipq8074" for ipq8074
- reg:
Usage: required
@@ -105,6 +106,16 @@
- "bus_master" Master AXI clock
- "bus_slave" Slave AXI clock
+- clock-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" PCIe to SysNOC BIU clock
+ - "axi_m" AXI Master clock
+ - "axi_s" AXI Slave clock
+ - "ahb" AHB clock
+ - "aux" Auxiliary clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -144,6 +155,18 @@
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+- reset-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "pipe" PIPE reset
+ - "sleep" Sleep reset
+ - "sticky" Core Sticky reset
+ - "axi_m" AXI Master reset
+ - "axi_s" AXI Slave reset
+ - "ahb" AHB Reset
+ - "axi_m_sticky" AXI Master Sticky reset
+
- power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: <prop-encoded-array>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 8/8] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
` (6 preceding siblings ...)
2017-07-20 5:34 ` [PATCH v3 7/8] dt-bindings: pci: qcom: Add support for IPQ8074 Varadarajan Narayanan
@ 2017-07-20 5:34 ` Varadarajan Narayanan
7 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2017-07-20 5:34 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, svarbanov, kishon, sboyd,
vivek.gautam, fengguang.wu, weiyongjun1, linux-pci, devicetree,
linux-kernel, linux-arm-msm
Cc: Varadarajan Narayanan, smuthayy
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
The core init is the similar to the existing SoC, however the
clocks and reset lines differ.
Signed-off-by: smuthayy <smuthayy@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/pci/dwc/pcie-qcom.c | 264 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 259 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 98c74d7..b2ea953 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -37,6 +37,20 @@
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
+#define MST_WAKEUP_EN BIT(13)
+#define SLV_WAKEUP_EN BIT(12)
+#define MSTR_ACLK_CGC_DIS BIT(10)
+#define SLV_ACLK_CGC_DIS BIT(9)
+#define CORE_CLK_CGC_DIS BIT(6)
+#define AUX_PWR_DET BIT(4)
+#define L23_CLK_RMV_DIS BIT(2)
+#define L1_CLK_RMV_DIS BIT(1)
+
+#define PCIE20_COMMAND_STATUS 0x04
+#define CMD_BME_VAL 0x4
+#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
+#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
+
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
@@ -58,9 +72,22 @@
#define CFG_BRIDGE_SB_INIT BIT(0)
#define PCIE20_CAP 0x70
+#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
+#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
+#define PCIE_CAP_LINK1_VAL 0x2fd7f
+
+#define PCIE20_PARF_Q2A_FLUSH 0x1AC
+
+#define PCIE20_MISC_CONTROL_1_REG 0x8BC
+#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+#define AXI_CLK_RATE 200000000
+
+#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
+#define SLV_ADDR_SPACE_SZ 0x10000000
+
struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
@@ -110,11 +137,21 @@ struct qcom_pcie_resources_2_4_0 {
struct reset_control *phy_ahb_reset;
};
+struct qcom_pcie_resources_2_3_3 {
+ struct clk *iface;
+ struct clk *axi_m_clk;
+ struct clk *axi_s_clk;
+ struct clk *ahb_clk;
+ struct clk *aux_clk;
+ struct reset_control *rst[7];
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
struct qcom_pcie_resources_2_3_2 v2_3_2;
struct qcom_pcie_resources_2_4_0 v2_4_0;
+ struct qcom_pcie_resources_2_3_3 v2_3_3;
};
struct qcom_pcie;
@@ -884,6 +921,206 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
return ret;
}
+static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int i;
+ const char *rst_names[] = {
+ "axi_m", "axi_s", "pipe",
+ "axi_m_sticky", "sticky",
+ "ahb", "sleep",
+ };
+
+ res->iface = devm_clk_get(dev, "iface");
+ if (IS_ERR(res->iface))
+ return PTR_ERR(res->iface);
+
+ res->axi_m_clk = devm_clk_get(dev, "axi_m");
+ if (IS_ERR(res->axi_m_clk))
+ return PTR_ERR(res->axi_m_clk);
+
+ res->axi_s_clk = devm_clk_get(dev, "axi_s");
+ if (IS_ERR(res->axi_s_clk))
+ return PTR_ERR(res->axi_s_clk);
+
+ res->ahb_clk = devm_clk_get(dev, "ahb");
+ if (IS_ERR(res->ahb_clk))
+ return PTR_ERR(res->ahb_clk);
+
+ res->aux_clk = devm_clk_get(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
+ res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
+ if (IS_ERR(res->rst[i]))
+ return PTR_ERR(res->rst[i]);
+ }
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+
+ clk_disable_unprepare(res->iface);
+ clk_disable_unprepare(res->axi_m_clk);
+ clk_disable_unprepare(res->axi_s_clk);
+ clk_disable_unprepare(res->ahb_clk);
+ clk_disable_unprepare(res->aux_clk);
+}
+
+static int qcom_pcie_enable_resources_2_3_3(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret;
+
+ ret = clk_prepare_enable(res->iface);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(res->axi_m_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_axi_m;
+ }
+
+ ret = clk_set_rate(res->axi_m_clk, AXI_CLK_RATE);
+ if (ret) {
+ dev_err(dev, "MClk rate set failed (%d)\n", ret);
+ goto err_clk_axi_m;
+ }
+
+ ret = clk_prepare_enable(res->axi_s_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable axi slave clock\n");
+ goto err_clk_axi_s;
+ }
+
+ ret = clk_set_rate(res->axi_s_clk, AXI_CLK_RATE);
+ if (ret) {
+ dev_err(dev, "MClk rate set failed (%d)\n", ret);
+ goto err_clk_axi_s;
+ }
+
+ ret = clk_prepare_enable(res->ahb_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ahb clock\n");
+ goto err_clk_ahb;
+ }
+
+ ret = clk_prepare_enable(res->aux_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ udelay(1);
+
+ return 0;
+
+err_clk_aux:
+ clk_disable_unprepare(res->ahb_clk);
+err_clk_ahb:
+ clk_disable_unprepare(res->axi_s_clk);
+err_clk_axi_s:
+ clk_disable_unprepare(res->axi_m_clk);
+err_clk_axi_m:
+ clk_disable_unprepare(res->iface);
+
+ return ret;
+}
+
+static int qcom_pcie_2_3_3_reset(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
+ ret = reset_control_assert(res->rst[i]);
+ if (ret) {
+ dev_err(pcie->pci->dev,
+ "%s: reset assert failed for %d\n",
+ __func__, i);
+ return ret;
+ }
+ }
+
+ msleep(20);
+
+ for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
+ ret = reset_control_deassert(res->rst[i]);
+ if (ret) {
+ dev_err(pcie->pci->dev,
+ "%s: reset deassert failed for %d\n",
+ __func__, i);
+ return ret;
+ }
+ }
+
+ msleep(20);
+
+ return 0;
+}
+
+static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
+{
+ struct dw_pcie *pci = pcie->pci;
+ int ret;
+ u32 val;
+
+ ret = qcom_pcie_2_3_3_reset(pcie);
+ if (ret)
+ return ret;
+
+ qcom_ep_reset_assert(pcie);
+
+ ret = qcom_pcie_enable_resources_2_3_3(pcie);
+ if (ret)
+ return ret;
+
+ writel(SLV_ADDR_SPACE_SZ, pcie->parf +
+ PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+ ret = phy_power_on(pcie->phy);
+ if (ret) {
+ pcie->ops->deinit(pcie);
+ return ret;
+ }
+
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
+ | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+ writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
+ writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
+ writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
+
+ val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
+ val &= ~(BIT(10) | BIT(11));
+ writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
+
+ writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
+ PCIE20_DEVICE_CONTROL2_STATUS2);
+
+ return 0;
+}
+
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
@@ -985,6 +1222,13 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
+static const struct qcom_pcie_ops ops_2_3_3 = {
+ .get_resources = qcom_pcie_get_resources_2_3_3,
+ .init = qcom_pcie_init_2_3_3,
+ .deinit = qcom_pcie_deinit_2_3_3,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static int qcom_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1070,12 +1314,22 @@ static int qcom_pcie_probe(struct platform_device *pdev)
return 0;
}
+/*
+ * Declare one of_device_id entry
+ * c - Compatible string
+ * d - Associated data
+ * w - SoC wrapper version (ignored)
+ * s - Synopsys core version (ignored)
+ */
+#define QCOM_DECL(c, d, w, s) { .compatible = c, .data = &d }
+
static const struct of_device_id qcom_pcie_match[] = {
- { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
- { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
- { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
- { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
- { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
+ QCOM_DECL("qcom,pcie-apq8084", ops_1_0_0, 1.0.0, 4.11a),
+ QCOM_DECL("qcom,pcie-ipq8064", ops_2_1_0, 2.1.0, 4.01a),
+ QCOM_DECL("qcom,pcie-apq8064", ops_2_1_0, 2.1.0, 4.01a),
+ QCOM_DECL("qcom,pcie-msm8996", ops_2_3_2, 2.3.2, 4.21a),
+ QCOM_DECL("qcom,pcie-ipq4019", ops_2_4_0, 2.4.0, 4.20a),
+ QCOM_DECL("qcom,pcie-ipq8074", ops_2_3_3, 2.3.3, 4.30a),
{ }
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name
2017-07-20 5:34 ` [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan
@ 2017-07-21 8:01 ` Vivek Gautam
0 siblings, 0 replies; 10+ messages in thread
From: Vivek Gautam @ 2017-07-21 8:01 UTC (permalink / raw)
To: Varadarajan Narayanan, bhelgaas, robh+dt, mark.rutland,
svarbanov, kishon, sboyd, fengguang.wu, weiyongjun1, linux-pci,
devicetree, linux-kernel, linux-arm-msm
Hi,
On 07/20/2017 11:04 AM, Varadarajan Narayanan wrote:
> Presently, the phy pipe clock's name is assumed to be either
> usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
> phy lane's number). However, this will not work if an SoC has
> more than one instance of the phy. Hence, instead of assuming
> the name of the clock, fetch it from the DT.
>
> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++++++++++++++++------------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 78ca628..97020ec 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -925,20 +925,13 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
> * clk | +-------+ | +-----+
> * +---------------+
> */
> -static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
> +static int phy_pipe_clk_register(struct qcom_qmp *qmp, const char *clk_name)
> {
> - char name[24];
> struct clk_fixed_rate *fixed;
> struct clk_init_data init = { };
>
> - switch (qmp->cfg->type) {
> - case PHY_TYPE_USB3:
> - snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src");
> - break;
> - case PHY_TYPE_PCIE:
> - snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id);
> - break;
> - default:
> + if ((qmp->cfg->type != PHY_TYPE_USB3) &&
> + (qmp->cfg->type != PHY_TYPE_PCIE)) {
> /* not all phys register pipe clocks, so return success */
> return 0;
> }
> @@ -947,7 +940,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id)
> if (!fixed)
> return -ENOMEM;
>
> - init.name = name;
> + init.name = clk_name;
> init.ops = &clk_fixed_rate_ops;
>
> /* controllers using QMP phys use 125MHz pipe clock interface */
> @@ -1110,6 +1103,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
>
> id = 0;
> for_each_available_child_of_node(dev->of_node, child) {
> + const char *clk_name;
> +
> /* Create per-lane phy */
> ret = qcom_qmp_phy_create(dev, child, id);
> if (ret) {
> @@ -1118,11 +1113,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
> return ret;
> }
>
> + ret = of_property_read_string(child, "clock-output-names",
> + &clk_name);
> + if (ret) {
Sorry, missed this earlier.
You shouldn't error out for phys that don't expose 'clock-output'.
So returning success in case the property doesn't exist for particular
phys makes sense.
And again for usb and pcie this property becomes mandatory.
Regards
Vivek
> + dev_err(dev,
> + "failed to get clock-output-names for lane%d phy, %d\n",
> + id, ret);
> + return ret;
> + }
> +
> /*
> * Register the pipe clock provided by phy.
> * See function description to see details of this pipe clock.
> */
> - ret = phy_pipe_clk_register(qmp, id);
> + ret = phy_pipe_clk_register(qmp, clk_name);
> if (ret) {
> dev_err(qmp->dev,
> "failed to register pipe clock source\n");
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-07-21 8:01 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-20 5:34 [PATCH v3 0/8] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 1/8] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 2/8] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan
2017-07-21 8:01 ` Vivek Gautam
2017-07-20 5:34 ` [PATCH v3 4/8] phy: qcom-qmp: Handle unavailable registers Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 5/8] phy: qcom-qmp: Add support for IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 6/8] PCI: dwc: qcom: Use block IP version for operations Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 7/8] dt-bindings: pci: qcom: Add support for IPQ8074 Varadarajan Narayanan
2017-07-20 5:34 ` [PATCH v3 8/8] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller Varadarajan Narayanan
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