From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: <p.zabel@pengutronix.de>, <robh+dt@kernel.org>,
<matthias.bgg@gmail.com>, <airlied@linux.ie>,
<mark.rutland@arm.com>, <dri-devel@lists.freedesktop.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <Bibby.Hsieh@mediatek.com>,
<yt.shen@mediatek.com>
Subject: Re: [PATCH v2 01/25] arm64: dts: add display nodes for mt8183
Date: Thu, 28 Mar 2019 11:18:26 +0800 [thread overview]
Message-ID: <1553743106.14682.6.camel@mtksdaap41> (raw)
In-Reply-To: <1553667561-25447-2-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:18 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add display nodes for mt8183
I think this patch should be after binding document patch. You should
define the compatible string then you could add device node.
>
> Change-Id: I9ce7081a2159ec7cc199999285b0390b01de43fe
Remove 'Change-Id' when you upstream.
Regards,
CK
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 107 +++++++++++++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 75c4881..f219dbd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -16,6 +16,14 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl0 = &ovl0;
> + ovl_2l0 = &ovl0_2l;
> + ovl_2l1 = &ovl1_2l;
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -317,6 +325,105 @@
> #clock-cells = <1>;
> };
>
> + display_components: dispsys@14000000 {
> + compatible = "mediatek,mt8183-display";
> + reg = <0 0x14000000 0 0x1000>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl0: ovl@14008000 {
> + compatible = "mediatek,mt8183-disp-ovl";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu M4U_PORT_DISP_OVL0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + ovl0_2l: ovl@14009000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + ovl1_2l: ovl@1400a000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma0: rdma@1400b000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma1: rdma@1400c000 {
> + compatible = "mediatek,mt8183-disp-rdma1";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + color0: color@1400e000 {
> + compatible = "mediatek,mt8183-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
> +
> + ccorr0: ccorr@1400f000 {
> + compatible = "mediatek,mt8183-disp-ccorr";
> + reg = <0 0x1400f000 0 0x1000>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@14010000 {
> + compatible = "mediatek,mt8183-disp-aal",
> + "mediatek,mt8173-disp-aal";
> + reg = <0 0x14010000 0 0x1000>;
> + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + };
> +
> + gamma0: gamma@14011000 {
> + compatible = "mediatek,mt8183-disp-gamma",
> + "mediatek,mt8173-disp-gamma";
> + reg = <0 0x14011000 0 0x1000>;
> + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + };
> +
> + dither0: dither@14012000 {
> + compatible = "mediatek,mt8183-disp-dither";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + };
> +
> smi_common: smi@14019000 {
> compatible = "mediatek,mt8183-smi-common", "syscon";
> reg = <0 0x14019000 0 0x1000>;
next prev parent reply other threads:[~2019-03-28 3:18 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 6:18 [PATCH v2 00/25] add drm support for MT8183 yongqiang.niu
2019-03-27 6:18 ` [PATCH v2 01/25] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-03-28 3:18 ` CK Hu [this message]
2019-03-27 6:18 ` [PATCH v2 02/25] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-03-27 9:39 ` CK Hu
2019-03-31 6:42 ` Rob Herring
2019-03-27 6:18 ` [PATCH v2 03/25] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-03-28 1:33 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 04/25] drm/mediatek: add mutex sof " yongqiang.niu
2019-03-28 3:02 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 05/25] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-03-28 3:37 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 06/25] drm/mediatek: redefine mtk_ddp_sout_sel yongqiang.niu
2019-04-11 6:09 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 07/25] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-04-11 5:30 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 08/25] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-04-11 5:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 09/25] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-04-11 10:42 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 10/25] drm/mediatek: add commponent OVL0_2L yongqiang.niu
2019-04-11 6:14 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 11/25] drm/mediatek: add component OVL1_2L yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 12/25] drm/mediatek: add component DITHER yongqiang.niu
2019-04-11 6:28 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 13/25] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-04-11 6:48 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 14/25] drm/medaitek: add layer_nr " yongqiang.niu
2019-04-11 10:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 15/25] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-04-11 11:01 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 16/25] drm/mediatek: add ddp write register common api yongqiang.niu
2019-04-11 11:15 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 17/25] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-04-16 7:38 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 18/25] drm/mediatek: add RDMA fifo size error handle yongqiang.niu
2019-04-16 8:00 ` CK Hu
2019-04-16 8:37 ` Yongqiang Niu
2019-04-16 11:31 ` YT Shen
2019-03-27 6:19 ` [PATCH v2 19/25] drm/mediatek: add function mtk_ddp_comp_get_type yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 20/25] drm/mediatek: add ovl0/ovl0_2l usecase yongqiang.niu
2019-04-16 8:20 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 21/25] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-04-11 10:33 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 22/25] drm/mediatek: adjust ddp clock control flow yongqiang.niu
2019-04-16 8:24 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 23/25] drm/mediatek: add vmap support for mediatek drm yongqiang.niu
2019-04-16 8:30 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 24/25] drm/mediatek: respect page offset for PRIME mmap calls yongqiang.niu
2019-04-16 8:33 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 25/25] drm/mediatek: enable allow_fb_modifiers for mediatek drm yongqiang.niu
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