From: Krishna Reddy <vdumpa@nvidia.com>
To: unlisted-recipients:; (no To-header on input)
Cc: <linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<treding@nvidia.com>, <yhsu@nvidia.com>, <snikam@nvidia.com>,
<praithatha@nvidia.com>, <talho@nvidia.com>,
<avanbrunt@nvidia.com>, <thomasz@nvidia.com>, <olof@lixom.net>,
<jtukkinen@nvidia.com>, <mperttunen@nvidia.com>,
Krishna Reddy <vdumpa@nvidia.com>
Subject: [PATCH 3/7] iommu/arm-smmu: Add tlb_sync implementation hook
Date: Thu, 29 Aug 2019 15:47:03 -0700 [thread overview]
Message-ID: <1567118827-26358-4-git-send-email-vdumpa@nvidia.com> (raw)
In-Reply-To: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com>
tlb_sync hook allows nvidia smmu handle tlb sync
across multiple SMMUs as necessary.
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
drivers/iommu/arm-smmu-nvidia.c | 32 ++++++++++++++++++++++++++++++++
drivers/iommu/arm-smmu.c | 8 +++++---
drivers/iommu/arm-smmu.h | 4 ++++
3 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu-nvidia.c b/drivers/iommu/arm-smmu-nvidia.c
index d93ceda..a429b2c 100644
--- a/drivers/iommu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm-smmu-nvidia.c
@@ -56,11 +56,43 @@ static void nsmmu_write_reg64(struct arm_smmu_device *smmu,
writeq_relaxed(val, nsmmu_page(smmu, i, page) + offset);
}
+static void nsmmu_tlb_sync_wait(struct arm_smmu_device *smmu, int page,
+ int sync, int status, int inst)
+{
+ u32 reg;
+ unsigned int spin_cnt, delay;
+
+ for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
+ for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
+ reg = readl_relaxed(
+ nsmmu_page(smmu, inst, page) + status);
+ if (!(reg & sTLBGSTATUS_GSACTIVE))
+ return;
+ cpu_relax();
+ }
+ udelay(delay);
+ }
+ dev_err_ratelimited(smmu->dev,
+ "TLB sync timed out -- SMMU may be deadlocked\n");
+}
+
+static void nsmmu_tlb_sync(struct arm_smmu_device *smmu, int page,
+ int sync, int status)
+{
+ int i;
+
+ arm_smmu_writel(smmu, page, sync, 0);
+
+ for (i = 0; i < to_nsmmu(smmu)->num_inst; i++)
+ nsmmu_tlb_sync_wait(smmu, page, sync, status, i);
+}
+
static const struct arm_smmu_impl nsmmu_impl = {
.read_reg = nsmmu_read_reg,
.write_reg = nsmmu_write_reg,
.read_reg64 = nsmmu_read_reg64,
.write_reg64 = nsmmu_write_reg64,
+ .tlb_sync = nsmmu_tlb_sync,
};
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 46e1641..f5454e71 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -52,9 +52,6 @@
*/
#define QCOM_DUMMY_VAL -1
-#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
-#define TLB_SPIN_COUNT 10
-
#define MSI_IOVA_BASE 0x8000000
#define MSI_IOVA_LENGTH 0x100000
@@ -244,6 +241,11 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
unsigned int spin_cnt, delay;
u32 reg;
+ if (smmu->impl->tlb_sync) {
+ smmu->impl->tlb_sync(smmu, page, sync, status);
+ return;
+ }
+
arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 9645bf1..d3217f1 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -207,6 +207,8 @@ enum arm_smmu_cbar_type {
/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS 128
+#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
+#define TLB_SPIN_COUNT 10
/* Shared driver definitions */
enum arm_smmu_arch_version {
@@ -336,6 +338,8 @@ struct arm_smmu_impl {
int (*cfg_probe)(struct arm_smmu_device *smmu);
int (*reset)(struct arm_smmu_device *smmu);
int (*init_context)(struct arm_smmu_domain *smmu_domain);
+ void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
+ int status);
};
static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
--
2.1.4
next prev parent reply other threads:[~2019-08-29 22:45 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 22:47 [PATCH 0/7] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2019-08-29 22:47 ` [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation Krishna Reddy
2019-08-30 15:02 ` Robin Murphy
2019-08-30 18:16 ` Krishna Reddy
2019-09-02 13:39 ` Robin Murphy
2019-09-03 1:07 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Krishna Reddy
2019-08-30 12:07 ` Mikko Perttunen
2019-08-30 15:13 ` Robin Murphy
2019-08-30 18:12 ` Krishna Reddy
2019-09-02 7:38 ` Thierry Reding
2019-08-29 22:47 ` Krishna Reddy [this message]
2019-08-30 11:14 ` [PATCH 3/7] iommu/arm-smmu: Add tlb_sync implementation hook Thierry Reding
2019-08-30 19:00 ` Krishna Reddy
2019-08-30 15:23 ` Robin Murphy
2019-08-30 18:05 ` Krishna Reddy
2019-08-30 22:49 ` Krishna Reddy
2019-09-02 13:00 ` Robin Murphy
2019-08-29 22:47 ` [PATCH 4/7] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2019-08-30 11:17 ` Thierry Reding
2019-08-30 19:16 ` Krishna Reddy
2019-08-30 15:43 ` Robin Murphy
2019-08-30 17:43 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 5/7] arm64: tegra: Add Memory controller DT node on T194 Krishna Reddy
2019-08-30 11:18 ` Thierry Reding
2019-08-29 22:47 ` [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU Krishna Reddy
2019-08-30 12:09 ` Mikko Perttunen
2019-08-30 18:39 ` Krishna Reddy
2019-08-30 15:44 ` Robin Murphy
2019-08-30 17:25 ` Krishna Reddy
2019-08-30 17:45 ` Robin Murphy
2019-08-30 18:35 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 7/7] arm64: tegra: enable SMMU for SDHCI and EQOS Krishna Reddy
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