* [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-08 17:05 ` [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header tip-bot2 for Kan Liang
2019-10-08 17:05 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
` (7 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel
Cc: ak, Kan Liang, Borislav Petkov, Thomas Gleixner
From: Kan Liang <kan.liang@linux.intel.com>
Comet Lake is the new 10th Gen Intel processor.
Add CPU model number for Comet Lake to the Intel family list.
The CPU model number is not published in SDM yet. It comes
from an authoritative internal source.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/intel-family.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index f046225..c606c0b 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -83,6 +83,9 @@
#define INTEL_FAM6_TIGERLAKE_L 0x8C
#define INTEL_FAM6_TIGERLAKE 0x8D
+#define INTEL_FAM6_COMETLAKE 0xA5
+#define INTEL_FAM6_COMETLAKE_L 0xA6
+
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
@ 2019-10-08 17:05 ` tip-bot2 for Kan Liang
2019-10-08 17:05 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-08 17:05 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Borislav Petkov, Tony Luck, ak, H. Peter Anvin,
Ingo Molnar, Peter Zijlstra, Thomas Gleixner, x86-ml,
Borislav Petkov, linux-kernel
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 8d7c6ac3b2371eb1cbc9925a88f4d10efff374de
Gitweb: https://git.kernel.org/tip/8d7c6ac3b2371eb1cbc9925a88f4d10efff374de
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:02 -07:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 08 Oct 2019 19:01:31 +02:00
x86/cpu: Add Comet Lake to the Intel CPU models header
Comet Lake is the new 10th Gen Intel processor. Add two new CPU model
numbers to the Intel family list.
The CPU model numbers are not published in the SDM yet but they come
from an authoritative internal source.
[ bp: Touch up commit message. ]
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Cc: ak@linux.intel.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1570549810-25049-2-git-send-email-kan.liang@linux.intel.com
---
arch/x86/include/asm/intel-family.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index f046225..c606c0b 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -83,6 +83,9 @@
#define INTEL_FAM6_TIGERLAKE_L 0x8C
#define INTEL_FAM6_TIGERLAKE 0x8D
+#define INTEL_FAM6_COMETLAKE 0xA5
+#define INTEL_FAM6_COMETLAKE_L 0xA6
+
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
2019-10-08 17:05 ` [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header tip-bot2 for Kan Liang
@ 2019-10-08 17:05 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-08 17:05 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Borislav Petkov, Tony Luck, ak, H. Peter Anvin,
Ingo Molnar, Peter Zijlstra, Thomas Gleixner, x86-ml,
Borislav Petkov, linux-kernel
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 8d7c6ac3b2371eb1cbc9925a88f4d10efff374de
Gitweb: https://git.kernel.org/tip/8d7c6ac3b2371eb1cbc9925a88f4d10efff374de
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:02 -07:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 08 Oct 2019 19:01:31 +02:00
x86/cpu: Add Comet Lake to the Intel CPU models header
Comet Lake is the new 10th Gen Intel processor. Add two new CPU model
numbers to the Intel family list.
The CPU model numbers are not published in the SDM yet but they come
from an authoritative internal source.
[ bp: Touch up commit message. ]
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Cc: ak@linux.intel.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1570549810-25049-2-git-send-email-kan.liang@linux.intel.com
---
arch/x86/include/asm/intel-family.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index f046225..c606c0b 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -83,6 +83,9 @@
#define INTEL_FAM6_TIGERLAKE_L 0x8C
#define INTEL_FAM6_TIGERLAKE 0x8D
+#define INTEL_FAM6_COMETLAKE 0xA5
+#define INTEL_FAM6_COMETLAKE_L 0xA6
+
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
` (6 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Comet Lake is the new 10th Gen Intel processor. From the perspective
of Intel PMU, there is nothing changed compared with Sky Lake.
Share the perf code with Sky Lake.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 27ee47a..9d91a47 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4983,6 +4983,8 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_SKYLAKE:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
x86_add_quirk(intel_pebs_isolation_quirk);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/intel: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: a53ad0305c1f25edf63db8ae2a9a0289af8d73d4
Gitweb: https://git.kernel.org/tip/a53ad0305c1f25edf63db8ae2a9a0289af8d73d4
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:03 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:14 +02:00
perf/x86/intel: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. From the perspective
of Intel PMU, there is nothing changed compared with Sky Lake.
Share the perf code with Sky Lake.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-3-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 27ee47a..9d91a47 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4983,6 +4983,8 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_SKYLAKE:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
x86_add_quirk(intel_pebs_isolation_quirk);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: perf/urgent] perf/x86/intel: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 9066288b2aab1804dc1eebec6ff88474363b89cb
Gitweb: https://git.kernel.org/tip/9066288b2aab1804dc1eebec6ff88474363b89cb
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:03 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:08 +02:00
perf/x86/intel: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. From the perspective
of Intel PMU, there is nothing changed compared with Sky Lake.
Share the perf code with Sky Lake.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-3-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 27ee47a..9d91a47 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4983,6 +4983,8 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_SKYLAKE:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
x86_add_quirk(intel_pebs_isolation_quirk);
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/9] perf/x86/msr: Add Comet Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
` (5 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Comet Lake is the new 10th Gen Intel processor. PPERF and SMI_COUNT MSRs
are also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index b1afc77..c177bbe 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -89,6 +89,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/msr: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 0dcbd5393eae6915a85cb0079a90ec3dc89c455f
Gitweb: https://git.kernel.org/tip/0dcbd5393eae6915a85cb0079a90ec3dc89c455f
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:04 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:15 +02:00
perf/x86/msr: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. PPERF and SMI_COUNT MSRs
are also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-4-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index b1afc77..c177bbe 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -89,6 +89,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: perf/urgent] perf/x86/msr: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 9674b1cc0f94c34f76e58c102623a866836f269e
Gitweb: https://git.kernel.org/tip/9674b1cc0f94c34f76e58c102623a866836f269e
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:04 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:08 +02:00
perf/x86/msr: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. PPERF and SMI_COUNT MSRs
are also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-4-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index b1afc77..c177bbe 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -89,6 +89,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_KABYLAKE_L:
case INTEL_FAM6_KABYLAKE:
+ case INTEL_FAM6_COMETLAKE_L:
+ case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/9] perf/x86/cstate: Add Comet Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (2 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
` (4 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Comet Lake is the new 10th Gen Intel processor. From the perspective of
Intel cstate residency counters, there is nothing changed compared with
Kaby Lake.
Share hswult_cstates with Kaby Lake.
Update the comments for Comet Lake.
Kaby Lake is missed in the comments for some Residency Counters. Update
the comments for Kaby Lake as well.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/cstate.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 9f2f390..21c65e1 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -45,46 +45,48 @@
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
- CNL
+ * CNL,KBL,CML
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL
+ * GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML
* Scope: Package (physical package)
*
*/
@@ -614,6 +616,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 1d4d9a6e37ebe8e4ffc3abfcdd24988e7f89df4a
Gitweb: https://git.kernel.org/tip/1d4d9a6e37ebe8e4ffc3abfcdd24988e7f89df4a
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:05 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:15 +02:00
perf/x86/cstate: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. From the perspective of
Intel cstate residency counters, there is nothing changed compared with
Kaby Lake.
Share hswult_cstates with Kaby Lake.
Update the comments for Comet Lake.
Kaby Lake is missed in the comments for some Residency Counters. Update
the comments for Kaby Lake as well.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-5-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 9f2f390..21c65e1 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -45,46 +45,48 @@
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
- CNL
+ * CNL,KBL,CML
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL
+ * GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML
* Scope: Package (physical package)
*
*/
@@ -614,6 +616,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Add Comet Lake CPU support
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 1ffa6c04dae39776a3c222bdf88051e394386c01
Gitweb: https://git.kernel.org/tip/1ffa6c04dae39776a3c222bdf88051e394386c01
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:05 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:08 +02:00
perf/x86/cstate: Add Comet Lake CPU support
Comet Lake is the new 10th Gen Intel processor. From the perspective of
Intel cstate residency counters, there is nothing changed compared with
Kaby Lake.
Share hswult_cstates with Kaby Lake.
Update the comments for Comet Lake.
Kaby Lake is missed in the comments for some Residency Counters. Update
the comments for Kaby Lake as well.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-5-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 9f2f390..21c65e1 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -45,46 +45,48 @@
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
- CNL
+ * CNL,KBL,CML
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL
+ * GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL
+ * SKL,KNL,GLM,CNL,KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
+ * KBL,CML
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL
+ * Available model: HSW ULT,KBL,CNL,CML
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML
* Scope: Package (physical package)
*
*/
@@ -614,6 +616,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (3 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 6/9] perf/x86/cstate: Update C-state counters " kan.liang
` (3 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
PPERF and SMI_COUNT MSRs are also supported by Ice Lake desktop and
server.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c177bbe..8515512 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -92,6 +92,9 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_COMETLAKE_L:
case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
+ case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers for Ice Lake
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 4f0ce17d816a53326947b085bd755d8c1b9b05fb
Gitweb: https://git.kernel.org/tip/4f0ce17d816a53326947b085bd755d8c1b9b05fb
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:06 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:16 +02:00
perf/x86/msr: Add new CPU model numbers for Ice Lake
PPERF and SMI_COUNT MSRs are also supported by Ice Lake desktop and
server.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-6-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c177bbe..8515512 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -92,6 +92,9 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_COMETLAKE_L:
case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
+ case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers for Ice Lake
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 1a5da78d00ce0152994946debd1417513dc35eb3
Gitweb: https://git.kernel.org/tip/1a5da78d00ce0152994946debd1417513dc35eb3
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:06 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:09 +02:00
perf/x86/msr: Add new CPU model numbers for Ice Lake
PPERF and SMI_COUNT MSRs are also supported by Ice Lake desktop and
server.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-6-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c177bbe..8515512 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -92,6 +92,9 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_COMETLAKE_L:
case INTEL_FAM6_COMETLAKE:
case INTEL_FAM6_ICELAKE_L:
+ case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 6/9] perf/x86/cstate: Update C-state counters for Ice Lake
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (4 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support kan.liang
` (2 subsequent siblings)
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.
Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.
Fixes: f08c47d1f86c ("perf/x86/intel/cstate: Add Icelake support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/cstate.c | 36 +++++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 21c65e1..4d232ac 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,43 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
+ * ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML
+ * GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
* Scope: Package (physical package)
*
*/
@@ -546,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model icl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -629,8 +643,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Update C-state counters for Ice Lake
2019-10-08 15:50 ` [PATCH 6/9] perf/x86/cstate: Update C-state counters " kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 374f26643b3ce2bfab02053e292f16adf6e57aa1
Gitweb: https://git.kernel.org/tip/374f26643b3ce2bfab02053e292f16adf6e57aa1
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:07 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:16 +02:00
perf/x86/cstate: Update C-state counters for Ice Lake
There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.
Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: f08c47d1f86c ("perf/x86/intel/cstate: Add Icelake support")
Link: https://lkml.kernel.org/r/1570549810-25049-7-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 36 ++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 21c65e1..4d232ac 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,43 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
+ * ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML
+ * GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
* Scope: Package (physical package)
*
*/
@@ -546,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model icl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -629,8 +643,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Update C-state counters for Ice Lake
2019-10-08 15:50 ` [PATCH 6/9] perf/x86/cstate: Update C-state counters " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: f1857a2467755e5faa3c727d7146b6db960abee1
Gitweb: https://git.kernel.org/tip/f1857a2467755e5faa3c727d7146b6db960abee1
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:07 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:09 +02:00
perf/x86/cstate: Update C-state counters for Ice Lake
There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.
Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: f08c47d1f86c ("perf/x86/intel/cstate: Add Icelake support")
Link: https://lkml.kernel.org/r/1570549810-25049-7-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 36 ++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 21c65e1..4d232ac 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,43 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
+ * ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML
+ * GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
* Scope: Package (physical package)
*
*/
@@ -546,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model icl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -629,8 +643,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (5 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 6/9] perf/x86/cstate: Update C-state counters " kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
core PMU, there is little changes compared with Ice Lake, e.g. small
changes in event list. But it doesn't impact on core PMU functionality.
Share the perf code with Ice Lake. The event list patch will be submitted
later separately.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9d91a47..fcef678 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5033,6 +5033,8 @@ __init int intel_pmu_init(void)
/* fall through */
case INTEL_FAM6_ICELAKE_L:
case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/intel: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 3fefafb17502e2483abe190d11b1778a1f202d70
Gitweb: https://git.kernel.org/tip/3fefafb17502e2483abe190d11b1778a1f202d70
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:08 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:17 +02:00
perf/x86/intel: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
core PMU, there is little changes compared with Ice Lake, e.g. small
changes in event list. But it doesn't impact on core PMU functionality.
Share the perf code with Ice Lake. The event list patch will be submitted
later separately.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-8-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9d91a47..fcef678 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5033,6 +5033,8 @@ __init int intel_pmu_init(void)
/* fall through */
case INTEL_FAM6_ICELAKE_L:
case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: perf/urgent] perf/x86/intel: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 23645a76ba816652d6898def2ee69c6a6250c9b1
Gitweb: https://git.kernel.org/tip/23645a76ba816652d6898def2ee69c6a6250c9b1
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:08 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:09 +02:00
perf/x86/intel: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
core PMU, there is little changes compared with Ice Lake, e.g. small
changes in event list. But it doesn't impact on core PMU functionality.
Share the perf code with Ice Lake. The event list patch will be submitted
later separately.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-8-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9d91a47..fcef678 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5033,6 +5033,8 @@ __init int intel_pmu_init(void)
/* fall through */
case INTEL_FAM6_ICELAKE_L:
case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 8/9] perf/x86/msr: Add Tiger Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (6 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are
also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 8515512..6f86650 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ICELAKE:
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_ICELAKE_D:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/msr: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: b01a8e2edb924feee1b66f74df1198788fc37cca
Gitweb: https://git.kernel.org/tip/b01a8e2edb924feee1b66f74df1198788fc37cca
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:09 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:18 +02:00
perf/x86/msr: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are
also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-9-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 8515512..6f86650 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ICELAKE:
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_ICELAKE_D:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [tip: perf/urgent] perf/x86/msr: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 0917b95079af82c69d8f5bab301faeebcd2cb3cd
Gitweb: https://git.kernel.org/tip/0917b95079af82c69d8f5bab301faeebcd2cb3cd
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:09 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:09 +02:00
perf/x86/msr: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are
also supported.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-9-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 8515512..6f86650 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ICELAKE:
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_ICELAKE_D:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 9/9] perf/x86/cstate: Add Tiger Lake CPU support
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
` (7 preceding siblings ...)
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
@ 2019-10-08 15:50 ` kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
8 siblings, 2 replies; 28+ messages in thread
From: kan.liang @ 2019-10-08 15:50 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
cstate residency counters, there is nothing changed compared with
Ice Lake.
Share icl_cstates with Ice Lake.
Update the comments for Tiger Lake.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/cstate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 4d232ac..e1daf41 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,44 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- * ICL
+ * ICL,TGL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML,ICL
+ * GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL
* Scope: Package (physical package)
*
*/
@@ -645,6 +645,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
@ 2019-10-09 12:59 ` tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-09 12:59 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 5e715e1121340369e10aa14c6d498a1928c304bb
Gitweb: https://git.kernel.org/tip/5e715e1121340369e10aa14c6d498a1928c304bb
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:10 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 09 Oct 2019 12:44:20 +02:00
perf/x86/cstate: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
cstate residency counters, there is nothing changed compared with
Ice Lake.
Share icl_cstates with Ice Lake.
Update the comments for Tiger Lake.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-10-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 4d232ac..e1daf41 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,44 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- * ICL
+ * ICL,TGL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML,ICL
+ * GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL
* Scope: Package (physical package)
*
*/
@@ -645,6 +645,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply related [flat|nested] 28+ messages in thread* [tip: perf/urgent] perf/x86/cstate: Add Tiger Lake CPU support
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
@ 2019-10-12 13:19 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 28+ messages in thread
From: tip-bot2 for Kan Liang @ 2019-10-12 13:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Kan Liang, Peter Zijlstra (Intel),
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 52e92f409dede388b7dc3ee13491fbf7a80db935
Gitweb: https://git.kernel.org/tip/52e92f409dede388b7dc3ee13491fbf7a80db935
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Tue, 08 Oct 2019 08:50:10 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 12 Oct 2019 15:13:09 +02:00
perf/x86/cstate: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
cstate residency counters, there is nothing changed compared with
Ice Lake.
Share icl_cstates with Ice Lake.
Update the comments for Tiger Lake.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-10-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/intel/cstate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 4d232ac..e1daf41 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,44 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- * ICL
+ * ICL,TGL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML,ICL
+ * GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML,ICL
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML,ICL
+ * KBL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL
* Scope: Package (physical package)
*
*/
@@ -645,6 +645,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
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