From: Sharat Masetty <smasetty@codeaurora.org>
To: freedreno@lists.freedesktop.org
Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, will@kernel.org,
robin.murphy@arm.com, joro@8bytes.org,
iommu@lists.linux-foundation.org, jcrouse@codeaurora.org,
saiprakash.ranjan@codeaurora.org,
Sharat Masetty <smasetty@codeaurora.org>
Subject: [PATCH v2 0/7] drm/msm/a6xx: System Cache Support
Date: Thu, 2 Jan 2020 16:32:06 +0530 [thread overview]
Message-ID: <1577962933-13577-1-git-send-email-smasetty@codeaurora.org> (raw)
Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved render performance as well as lower power consumption by reducing
the bus traffic to the system memory.
The system cache architecture allows the cache to be split into slices which
then be used by multiple SOC clients. This patch series is an effort to enable
and use two of those slices perallocated for the GPU, one for the GPU data
buffers and another for the GPU SMMU hardware pagetables.
v2: Code reviews and rebased code on top of Jordan's split pagetables series
To enable the system cache driver, add [1] to your stack if not already
present. Please review.
[1] https://lore.kernel.org/patchwork/patch/1165298/
Jordan Crouse (3):
iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
drm/msm: Attach the IOMMU device during initialization
drm/msm: Refactor address space initialization
Sharat Masetty (3):
drm: msm: a6xx: Properly free up the iommu objects
drm/msm: rearrange the gpu_rmw() function
drm/msm/a6xx: Add support for using system cache(LLC)
Vivek Gautam (1):
iommu/arm-smmu: Add domain attribute for QCOM system cache
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 16 ++++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 124 +++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 ++++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 19 ++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 4 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 19 +++--
drivers/gpu/drm/msm/msm_drv.c | 8 ++
drivers/gpu/drm/msm/msm_drv.h | 9 +--
drivers/gpu/drm/msm/msm_gem_vma.c | 37 ++-------
drivers/gpu/drm/msm/msm_gpu.c | 49 +-----------
drivers/gpu/drm/msm/msm_gpu.h | 9 +--
drivers/gpu/drm/msm/msm_gpummu.c | 7 --
drivers/gpu/drm/msm/msm_iommu.c | 22 +++---
drivers/gpu/drm/msm/msm_mmu.h | 5 +-
drivers/iommu/arm-smmu-impl.c | 3 +-
drivers/iommu/arm-smmu-qcom.c | 10 +++
drivers/iommu/arm-smmu.c | 25 +++++--
drivers/iommu/arm-smmu.h | 4 +-
include/linux/iommu.h | 1 +
25 files changed, 269 insertions(+), 158 deletions(-)
--
1.9.1
next reply other threads:[~2020-01-02 11:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 11:02 Sharat Masetty [this message]
2020-01-02 11:02 ` [PATCH v2 1/7] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context Sharat Masetty
2020-01-31 22:00 ` Matthias Kaehlcke
2020-01-02 11:02 ` [PATCH v2 2/7] iommu/arm-smmu: Add domain attribute for QCOM system cache Sharat Masetty
2020-01-03 19:02 ` [Freedreno] " Rob Clark
2020-01-02 11:02 ` [PATCH v2 3/7] drm/msm: Attach the IOMMU device during initialization Sharat Masetty
2020-01-02 11:02 ` [PATCH v2 4/7] drm/msm: Refactor address space initialization Sharat Masetty
2020-01-02 11:02 ` [PATCH v2 5/7] drm: msm: a6xx: Properly free up the iommu objects Sharat Masetty
2020-01-02 11:02 ` [PATCH v2 6/7] drm/msm: rearrange the gpu_rmw() function Sharat Masetty
2020-01-02 11:02 ` [PATCH v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sharat Masetty
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