[PATCH v1 0/3] Add GCC clock driver support

[PATCH v1 0/3] Add GCC clock driver support

[Taniya Das]

 [v1]
  * Add a new frequency of 51.2MHz for QUP clock.
  * Add support for gcc_sec_ctrl_clk_src RCG for client to be able to request
   various frequencies.

Taniya Das (3):
  clk: qcom: gcc: Add support for a new frequency for SC7180
  dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
  clk: qcom: gcc: Add support for Secure control source clock

 drivers/clk/qcom/gcc-sc7180.c               | 94 ++++++++++++++++++-----------
 include/dt-bindings/clock/qcom,gcc-sc7180.h |  1 +
 2 files changed, 59 insertions(+), 36 deletions(-)

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v1 1/3] clk: qcom: gcc: Add support for a new frequency for SC7180

[Taniya Das]

There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
thus update the frequency table and parent data/map to use the GPLL6
source PLL.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/gcc-sc7180.c | 73 ++++++++++++++++++++++---------------------
 1 file changed, 37 insertions(+), 36 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index 7f59fb8..ad75847 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -390,6 +390,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
+	F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
 	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
@@ -405,8 +406,8 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {

 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s0_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -414,15 +415,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 	.cmd_rcgr = 0x17034,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s1_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -430,15 +431,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 	.cmd_rcgr = 0x17164,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s2_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -446,15 +447,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 	.cmd_rcgr = 0x17294,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s3_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -462,15 +463,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 	.cmd_rcgr = 0x173c4,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s4_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -478,15 +479,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 	.cmd_rcgr = 0x174f4,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 	.name = "gcc_qupv3_wrap0_s5_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -494,15 +495,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 	.cmd_rcgr = 0x17624,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s0_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -510,15 +511,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 	.cmd_rcgr = 0x18018,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s1_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -526,15 +527,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 	.cmd_rcgr = 0x18148,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s2_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -542,15 +543,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 	.cmd_rcgr = 0x18278,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s3_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -558,15 +559,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 	.cmd_rcgr = 0x183a8,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s4_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -574,15 +575,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 	.cmd_rcgr = 0x184d8,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 };

 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 	.name = "gcc_qupv3_wrap1_s5_clk_src",
-	.parent_data = gcc_parent_data_0,
-	.num_parents = 4,
+	.parent_data = gcc_parent_data_1,
+	.num_parents = 5,
 	.ops = &clk_rcg2_ops,
 };

@@ -590,7 +591,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 	.cmd_rcgr = 0x18608,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_0,
+	.parent_map = gcc_parent_map_1,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 };
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v1 2/3] dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID

[Taniya Das]

The gcc_sec_ctrl_clk_src clock is required to be controlled by the
secure controller driver.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
index e8029b2e..281d0b4 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc7180.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
@@ -132,6 +132,7 @@
 #define GCC_VIDEO_GPLL0_DIV_CLK_SRC				122
 #define GCC_VIDEO_THROTTLE_AXI_CLK				123
 #define GCC_VIDEO_XO_CLK					124
+#define GCC_SEC_CTRL_CLK_SRC					125

 /* GCC resets */
 #define GCC_QUSB2PHY_PRIM_BCR					0
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control source clock

[Taniya Das]

The secure controller driver requires to request for various frequencies
on the source clock, thus add support for the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/gcc-sc7180.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ad75847..3302f19 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 	},
 };

+static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
+	F(4800000, P_BI_TCXO, 4, 0, 0),
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
+	.cmd_rcgr = 0x3d030,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gcc_parent_map_3,
+	.freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gcc_sec_ctrl_clk_src",
+		.parent_data = gcc_parent_data_3,
+		.num_parents = 3,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
 	.halt_reg = 0x82024,
 	.halt_check = BRANCH_HALT_DELAY,
@@ -2337,6 +2357,7 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
 	[GPLL7] = &gpll7.clkr,
 	[GPLL4] = &gpll4.clkr,
 	[GPLL1] = &gpll1.clkr,
+	[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
 };

 static const struct qcom_reset_map gcc_sc7180_resets[] = {
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Re: [PATCH v1 0/3] Add GCC clock driver support

[Stephen Boyd]

The subject of this cover letter is too generic. Is it more like

	clk: qcom: sc7180: Add secure clk and more QUP frequencies

or so?

Quoting Taniya Das (2020-03-16 03:54:39)
>  [v1]
>   * Add a new frequency of 51.2MHz for QUP clock.
>   * Add support for gcc_sec_ctrl_clk_src RCG for client to be able to request
>    various frequencies.
> 
> Taniya Das (3):
>   clk: qcom: gcc: Add support for a new frequency for SC7180
>   dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
>   clk: qcom: gcc: Add support for Secure control source clock

Is this for sc7180? Please indicate as such in the subject lines.

> 
>  drivers/clk/qcom/gcc-sc7180.c               | 94 ++++++++++++++++++-----------
>  include/dt-bindings/clock/qcom,gcc-sc7180.h |  1 +
>  2 files changed, 59 insertions(+), 36 deletions(-)

Re: [PATCH v1 1/3] clk: qcom: gcc: Add support for a new frequency for SC7180

[Stephen Boyd]

Quoting Taniya Das (2020-03-16 03:54:40)
> There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
> thus update the frequency table and parent data/map to use the GPLL6
> source PLL.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---

Any Fixes: tag for this? I guess the beginning of this driver being
introduced?

>  drivers/clk/qcom/gcc-sc7180.c | 73 ++++++++++++++++++++++---------------------
>  1 file changed, 37 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> index 7f59fb8..ad75847 100644
> --- a/drivers/clk/qcom/gcc-sc7180.c
> +++ b/drivers/clk/qcom/gcc-sc7180.c
> @@ -405,8 +406,8 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> 
>  static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>         .name = "gcc_qupv3_wrap0_s0_clk_src",
> -       .parent_data = gcc_parent_data_0,
> -       .num_parents = 4,
> +       .parent_data = gcc_parent_data_1,

This should have been done initially. We shouldn't need to describe
"new" parents when they have always been there. Are there other clks in
this driver that actually have more parents than we've currently
described? If so, please fix them.

> +       .num_parents = 5,

Can you use ARRAY_SIZE(gcc_parent_data_1) instead? That way this isn't a
hard-coded value.

>         .ops = &clk_rcg2_ops,
>  };
>

Re: [PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control source clock

[Stephen Boyd]

Quoting Taniya Das (2020-03-16 03:54:42)
> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> index ad75847..3302f19 100644
> --- a/drivers/clk/qcom/gcc-sc7180.c
> +++ b/drivers/clk/qcom/gcc-sc7180.c
> @@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>         },
>  };
> 
> +static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
> +       F(4800000, P_BI_TCXO, 4, 0, 0),
> +       F(19200000, P_BI_TCXO, 1, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
> +       .cmd_rcgr = 0x3d030,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = gcc_parent_map_3,
> +       .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "gcc_sec_ctrl_clk_src",
> +               .parent_data = gcc_parent_data_3,
> +               .num_parents = 3,

ARRAY_SIZE please.

> +               .ops = &clk_rcg2_ops,
> +       },
> +};
> +
>  static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>         .halt_reg = 0x82024,
>         .halt_check = BRANCH_HALT_DELAY,

Re: [PATCH v1 1/3] clk: qcom: gcc: Add support for a new frequency for SC7180

[Taniya Das]

Hello Stephen,

Thanks for your review.

On 3/16/2020 11:19 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2020-03-16 03:54:40)
>> There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
>> thus update the frequency table and parent data/map to use the GPLL6
>> source PLL.
>>
>> Signed-off-by: Taniya Das <tdas@codeaurora.org>
>> ---
> 
> Any Fixes: tag for this? I guess the beginning of this driver being
> introduced?
> 

Sure, will add the same.

>>   drivers/clk/qcom/gcc-sc7180.c | 73 ++++++++++++++++++++++---------------------
>>   1 file changed, 37 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>> index 7f59fb8..ad75847 100644
>> --- a/drivers/clk/qcom/gcc-sc7180.c
>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>> @@ -405,8 +406,8 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>>
>>   static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>>          .name = "gcc_qupv3_wrap0_s0_clk_src",
>> -       .parent_data = gcc_parent_data_0,
>> -       .num_parents = 4,
>> +       .parent_data = gcc_parent_data_1,
> 
> This should have been done initially. We shouldn't need to describe
> "new" parents when they have always been there. Are there other clks in
> this driver that actually have more parents than we've currently
> described? If so, please fix them.
> 

The auto generation script does not consider to define the parent unless 
it is used in the frequency table to derive a frequency. For now I 
didn't find any other sources missed.

>> +       .num_parents = 5,
> 
> Can you use ARRAY_SIZE(gcc_parent_data_1) instead? That way this isn't a
> hard-coded value.
> 

Yes will take care of it too.

>>          .ops = &clk_rcg2_ops,
>>   };
>>

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control source clock

[Taniya Das]

Hello Stephen,

Thanks for your review.

On 3/16/2020 11:19 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2020-03-16 03:54:42)
>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>> index ad75847..3302f19 100644
>> --- a/drivers/clk/qcom/gcc-sc7180.c
>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>> @@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>>          },
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
>> +       F(4800000, P_BI_TCXO, 4, 0, 0),
>> +       F(19200000, P_BI_TCXO, 1, 0, 0),
>> +       { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
>> +       .cmd_rcgr = 0x3d030,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = gcc_parent_map_3,
>> +       .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "gcc_sec_ctrl_clk_src",
>> +               .parent_data = gcc_parent_data_3,
>> +               .num_parents = 3,
> 
> ARRAY_SIZE please.
> 

Will take care of the same.

>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
>>   static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>>          .halt_reg = 0x82024,
>>          .halt_check = BRANCH_HALT_DELAY,

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