[PATCH V1 0/4] Minor fixes to sdhci-msm

[PATCH V1 0/4] Minor fixes to sdhci-msm

[Veerabhadrarao Badiganti]

Enable a couple of CAPS that qcom sd host controller supports.
Set a quirk for enabling support for auto cmd12.
And enable adma length mismatch error interrupt.

Veerabhadrarao Badiganti (4):
  mmc: sdhci-msm: Enable MMC_CAP_WAIT_WHILE_BUSY host capability
  mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability
  mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk
  mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

 drivers/mmc/host/sdhci-msm.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

[PATCH V1 1/4] mmc: sdhci-msm: Enable MMC_CAP_WAIT_WHILE_BUSY host capability

[Veerabhadrarao Badiganti]

MSM sd host controller is capable of HW busy detection of device busy
singaling over DAT0 line.

So set MMC_CAP_WAIT_WHILE_BUSY capability for qcom sdhc.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 09ff731..013dcea 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2087,6 +2087,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 		goto clk_disable;
 	}
 
+	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+
 	pm_runtime_get_noresume(&pdev->dev);
 	pm_runtime_set_active(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 1/4] mmc: sdhci-msm: Enable MMC_CAP_WAIT_WHILE_BUSY host capability

[Adrian Hunter]

On 12/04/20 6:53 pm, Veerabhadrarao Badiganti wrote:
> MSM sd host controller is capable of HW busy detection of device busy
> singaling over DAT0 line.

singaling -> signaling

> 
> So set MMC_CAP_WAIT_WHILE_BUSY capability for qcom sdhc.
> 
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 09ff731..013dcea 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -2087,6 +2087,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  		goto clk_disable;
>  	}
>  
> +	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> +
>  	pm_runtime_get_noresume(&pdev->dev);
>  	pm_runtime_set_active(&pdev->dev);
>  	pm_runtime_enable(&pdev->dev);
> 

[PATCH V1 2/4] mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability

[Veerabhadrarao Badiganti]

sdhci-msm controller requires the R1B response for commands that
has this response associated with them.

So enable MMC_CAP_NEED_RSP_BUSY capability.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 013dcea..d826e9b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2088,6 +2088,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	}
 
 	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+	msm_host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
 
 	pm_runtime_get_noresume(&pdev->dev);
 	pm_runtime_set_active(&pdev->dev);
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 2/4] mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability

[Adrian Hunter]

On 12/04/20 6:53 pm, Veerabhadrarao Badiganti wrote:
> sdhci-msm controller requires the R1B response for commands that
> has this response associated with them.
> 
> So enable MMC_CAP_NEED_RSP_BUSY capability.
> 
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 013dcea..d826e9b 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -2088,6 +2088,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  	}
>  
>  	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> +	msm_host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
>  
>  	pm_runtime_get_noresume(&pdev->dev);
>  	pm_runtime_set_active(&pdev->dev);
> 

Re: [PATCH V1 2/4] mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability

[Ulf Hansson]

On Sun, 12 Apr 2020 at 17:54, Veerabhadrarao Badiganti
<vbadigan@codeaurora.org> wrote:
>
> sdhci-msm controller requires the R1B response for commands that
> has this response associated with them.
>
> So enable MMC_CAP_NEED_RSP_BUSY capability.

I assume this potentially should be considered as fix and tagged for stable?

Another question, if there is there an upper limit of the busy timeout
in the HW (cmd->busy_timeout) or does the driver use a software
timeout that is adjustable?

Kind regards
Uffe

>
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
> ---
>  drivers/mmc/host/sdhci-msm.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 013dcea..d826e9b 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -2088,6 +2088,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>         }
>
>         msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> +       msm_host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
>
>         pm_runtime_get_noresume(&pdev->dev);
>         pm_runtime_set_active(&pdev->dev);
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 2/4] mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability

[Veerabhadrarao Badiganti]

Hi Ulf,

On 4/16/2020 5:46 PM, Ulf Hansson wrote:
> On Sun, 12 Apr 2020 at 17:54, Veerabhadrarao Badiganti
> <vbadigan@codeaurora.org> wrote:
>> sdhci-msm controller requires the R1B response for commands that
>> has this response associated with them.
>>
>> So enable MMC_CAP_NEED_RSP_BUSY capability.
> I assume this potentially should be considered as fix and tagged for stable?
Yes Stable flag can be applied to this.

Patch with MMC_CAP_WAIT_WHILE_BUSY cap also needed besides this.
Shall I push V2 with stable flag?

> Another question, if there is there an upper limit of the busy timeout
> in the HW (cmd->busy_timeout) or does the driver use a software
> timeout that is adjustable?

The max supported h.w busy timeout value on qcom h/w 21sec.

> Kind regards
> Uffe
>
>> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
>> ---
>>   drivers/mmc/host/sdhci-msm.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index 013dcea..d826e9b 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -2088,6 +2088,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>          }
>>
>>          msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
>> +       msm_host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
>>
>>          pm_runtime_get_noresume(&pdev->dev);
>>          pm_runtime_set_active(&pdev->dev);
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 2/4] mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability

[Ulf Hansson]

On Thu, 16 Apr 2020 at 16:49, Veerabhadrarao Badiganti
<vbadigan@codeaurora.org> wrote:
>
> Hi Ulf,
>
> On 4/16/2020 5:46 PM, Ulf Hansson wrote:
> > On Sun, 12 Apr 2020 at 17:54, Veerabhadrarao Badiganti
> > <vbadigan@codeaurora.org> wrote:
> >> sdhci-msm controller requires the R1B response for commands that
> >> has this response associated with them.
> >>
> >> So enable MMC_CAP_NEED_RSP_BUSY capability.
> > I assume this potentially should be considered as fix and tagged for stable?
> Yes Stable flag can be applied to this.
>
> Patch with MMC_CAP_WAIT_WHILE_BUSY cap also needed besides this.
> Shall I push V2 with stable flag?

Ah, so maybe squash both into one patch to simplify for stable?

Yes, please add a stable tag in v2.

>
> > Another question, if there is there an upper limit of the busy timeout
> > in the HW (cmd->busy_timeout) or does the driver use a software
> > timeout that is adjustable?
>
> The max supported h.w busy timeout value on qcom h/w 21sec.

Alright, that sounds like it should be sufficient for most cases. But
perhaps not for eMMC sanitize.

How do you cope with the situation when the R1B response is passed to
the driver and the cmd->busy_timeout exceeds the 21s?

[...]

Kind regards
Uffe

[PATCH V1 3/4] mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk

[Veerabhadrarao Badiganti]

sdhci-msm can support auto cmd12.
So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index d826e9b..482045b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1882,7 +1882,9 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
 	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
-		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
+
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 	.ops = &sdhci_msm_ops,
 };
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 3/4] mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk

[Adrian Hunter]

On 12/04/20 6:53 pm, Veerabhadrarao Badiganti wrote:
> sdhci-msm can support auto cmd12.
> So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.
> 
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index d826e9b..482045b 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1882,7 +1882,9 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
>  static const struct sdhci_pltfm_data sdhci_msm_pdata = {
>  	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
>  		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
> -		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> +		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
> +
>  	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
>  	.ops = &sdhci_msm_ops,
>  };
> 

[PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

[Veerabhadrarao Badiganti]

ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
ADMA length mismatch error interrupt. Enable it by default.

And update all bit shift defines with BIT macro.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 482045b..660e1bc 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -56,19 +56,19 @@
 #define CORE_FLL_CYCLE_CNT	BIT(18)
 #define CORE_DLL_CLOCK_DISABLE	BIT(21)
 
-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa3c
 #define CORE_CLK_PWRSAVE	BIT(1)
 #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
 #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
 #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
-#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
-#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
+#define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
+#define CORE_IO_PAD_PWR_SWITCH	BIT(16)
 #define CORE_HC_SELECT_IN_EN	BIT(18)
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
-#define CORE_3_0V_SUPPORT	(1 << 25)
-#define CORE_1_8V_SUPPORT	(1 << 26)
+#define CORE_3_0V_SUPPORT	BIT(25)
+#define CORE_1_8V_SUPPORT	BIT(26)
 #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
 
 #define CORE_CSR_CDC_CTLR_CFG0		0x130
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

[Veerabhadrarao Badiganti]

On 4/12/2020 9:23 PM, Veerabhadrarao Badiganti wrote:
> ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
> ADMA length mismatch error interrupt. Enable it by default.
>
> And update all bit shift defines with BIT macro.
>
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
> ---
>   drivers/mmc/host/sdhci-msm.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 482045b..660e1bc 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -56,19 +56,19 @@
>   #define CORE_FLL_CYCLE_CNT	BIT(18)
>   #define CORE_DLL_CLOCK_DISABLE	BIT(21)
>   
> -#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
> +#define CORE_VENDOR_SPEC_POR_VAL 0xa3c
Sorry . This should be 0xa9c, not 0xa3c. Correcting it.
>   #define CORE_CLK_PWRSAVE	BIT(1)
>   #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>   #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>   #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
> -#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
> -#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
> +#define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
> +#define CORE_IO_PAD_PWR_SWITCH	BIT(16)
>   #define CORE_HC_SELECT_IN_EN	BIT(18)
>   #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>   #define CORE_HC_SELECT_IN_MASK	(7 << 19)
>   
> -#define CORE_3_0V_SUPPORT	(1 << 25)
> -#define CORE_1_8V_SUPPORT	(1 << 26)
> +#define CORE_3_0V_SUPPORT	BIT(25)
> +#define CORE_1_8V_SUPPORT	BIT(26)
>   #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
>   
>   #define CORE_CSR_CDC_CTLR_CFG0		0x130

[PATCH V1] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

[Veerabhadrarao Badiganti]

ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
ADMA length mismatch error interrupt. Enable it by default.

And update all bit shift defines with BIT macro.

Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
---
 drivers/mmc/host/sdhci-msm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 482045b..7d744f9 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -56,19 +56,19 @@
 #define CORE_FLL_CYCLE_CNT	BIT(18)
 #define CORE_DLL_CLOCK_DISABLE	BIT(21)
 
-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
 #define CORE_CLK_PWRSAVE	BIT(1)
 #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
 #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
 #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
-#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
-#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
+#define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
+#define CORE_IO_PAD_PWR_SWITCH	BIT(16)
 #define CORE_HC_SELECT_IN_EN	BIT(18)
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
-#define CORE_3_0V_SUPPORT	(1 << 25)
-#define CORE_1_8V_SUPPORT	(1 << 26)
+#define CORE_3_0V_SUPPORT	BIT(25)
+#define CORE_1_8V_SUPPORT	BIT(26)
 #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
 
 #define CORE_CSR_CDC_CTLR_CFG0		0x130
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH V1] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

[Adrian Hunter]

On 12/04/20 8:07 pm, Veerabhadrarao Badiganti wrote:
> ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
> ADMA length mismatch error interrupt. Enable it by default.
> 
> And update all bit shift defines with BIT macro.
> 
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 482045b..7d744f9 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -56,19 +56,19 @@
>  #define CORE_FLL_CYCLE_CNT	BIT(18)
>  #define CORE_DLL_CLOCK_DISABLE	BIT(21)
>  
> -#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
> +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
>  #define CORE_CLK_PWRSAVE	BIT(1)
>  #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>  #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>  #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
> -#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
> -#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
> +#define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
> +#define CORE_IO_PAD_PWR_SWITCH	BIT(16)
>  #define CORE_HC_SELECT_IN_EN	BIT(18)
>  #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>  #define CORE_HC_SELECT_IN_MASK	(7 << 19)
>  
> -#define CORE_3_0V_SUPPORT	(1 << 25)
> -#define CORE_1_8V_SUPPORT	(1 << 26)
> +#define CORE_3_0V_SUPPORT	BIT(25)
> +#define CORE_1_8V_SUPPORT	BIT(26)
>  #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
>  
>  #define CORE_CSR_CDC_CTLR_CFG0		0x130
>