Re: [PATCH v2 4/8] clk: qcom: smd: Add support for SDM660 rpm clocks

From: Stephen Boyd <sboyd@kernel.org>
To: Konrad Dybcio <konradybcio@gmail.com>, skrzynka@konradybcio.pl
Cc: Konrad Dybcio <konradybcio@gmail.com>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Kees Cook <keescook@chromium.org>,
	Anton Vorontsov <anton@enomsg.org>,
	Colin Cross <ccross@android.com>, Tony Luck <tony.luck@intel.com>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-gpio@vger.kernel.org
Subject: Re: [PATCH v2 4/8] clk: qcom: smd: Add support for SDM660 rpm clocks
Date: Mon, 22 Jun 2020 01:48:53 -0700	[thread overview]
Message-ID: <159281573385.62212.14646958691369932904@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20200622075749.21925-5-konradybcio@gmail.com>

Quoting Konrad Dybcio (2020-06-22 00:57:42)
> Add rpm smd clocks, PMIC and bus clocks which are required on
> SDM630/660 (and APQ variants) for clients to vote on.
> 
> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>

Just minor nits. Please resend without the other dts and SoC things and
trim the Cc list way down. Thanks.

> ---
>  .../devicetree/bindings/clock/qcom,rpmcc.txt  |  1 +
>  drivers/clk/qcom/clk-smd-rpm.c                | 77 +++++++++++++++++++
>  include/dt-bindings/clock/qcom,rpmcc.h        | 10 +++
>  3 files changed, 88 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> index 90a1349bc713..2ced7807d574 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> @@ -20,6 +20,7 @@ Required properties :
>                         "qcom,rpmcc-msm8996", "qcom,rpmcc"
>                         "qcom,rpmcc-msm8998", "qcom,rpmcc"
>                         "qcom,rpmcc-qcs404", "qcom,rpmcc"
> +                        "qcom,rpmcc-sdm660", "qcom,rpmcc"

This one looks right, but indented incorrectly?

>  
>  - #clock-cells : shall contain 1
>  
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> index 52f63ad787ba..4ae9e79e602e 100644
> --- a/drivers/clk/qcom/clk-smd-rpm.c
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -766,15 +766,92 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
>         .num_clks = ARRAY_SIZE(msm8998_clks),
>  };
>  
> +/* sdm660 */
> +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
> +                                                               19200000);
> +DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
> +DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
> +DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
> +                                               QCOM_SMD_RPM_BUS_CLK, 0);
> +DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
> +DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
> +                                                  QCOM_SMD_RPM_MMAXI_CLK, 0);
> +DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
> +DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
> +DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
> +                                               QCOM_SMD_RPM_AGGR_CLK, 2);
> +DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
> +                                               QCOM_SMD_RPM_MISC_CLK, 1);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
> +
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
> +                                                       ln_bb_clk1_pin_a, 1);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
> +                                                       ln_bb_clk2_pin_a, 2);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
> +                                                       ln_bb_clk3_pin_a, 3);
> +static struct clk_smd_rpm *sdm660_clks[] = {
> +       [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
> +       [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
> +       [RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk,
> +       [RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk,
> +       [RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk,
> +       [RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk,
> +       [RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk,
> +       [RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk,
> +       [RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk,
> +       [RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk,
> +       [RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk,
> +       [RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk,
> +       [RPM_SMD_IPA_CLK] = &sdm660_ipa_clk,
> +       [RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk,
> +       [RPM_SMD_CE1_CLK] = &sdm660_ce1_clk,
> +       [RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk,
> +       [RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk,
> +       [RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk,
> +       [RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk,
> +       [RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk,
> +       [RPM_SMD_RF_CLK1] = &sdm660_rf_clk1,
> +       [RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a,
> +       [RPM_SMD_DIV_CLK1] = &sdm660_div_clk1,
> +       [RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a,
> +       [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1,
> +       [RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a,
> +       [RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2,
> +       [RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a,
> +       [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
> +       [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
> +       [RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin,
> +       [RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin,
> +       [RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin,
> +       [RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a,
> +       [RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin,
> +       [RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a,
> +       [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
> +       [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
> +};
> +
> +static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
> +       .clks = sdm660_clks,
> +       .num_clks = ARRAY_SIZE(sdm660_clks),
> +};
> +
>  static const struct of_device_id rpm_smd_clk_match_table[] = {
>         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
>         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
>         { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
>         { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
>         { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
> +       { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },

Should come last, because s comes after q.

>         { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
>         { }
>  };
> +

Drop this diff.

>  MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
>  
>  static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,