* [PATCH v8 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
@ 2020-02-21 10:12 ` Macpaul Lin
2020-02-21 10:12 ` [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
` (4 subsequent siblings)
5 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2020-02-21 10:12 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel,
Shawn Guo, Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This patch adds MT6765 smi binding document
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../memory-controllers/mediatek,smi-common.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..3f96d1e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -18,6 +18,7 @@ Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
+ "mediatek,mt6765-smi-common", "syscon"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
"mediatek,mt8183-smi-common"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
2020-02-21 10:12 ` [PATCH v8 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
@ 2020-02-21 10:12 ` Macpaul Lin
2021-04-06 14:01 ` Matthias Brugger
2020-02-21 10:12 ` [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Macpaul Lin @ 2020-02-21 10:12 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel,
Shawn Guo, Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This adds scpsys support for MT6765
Add subdomain support for MT6765:
isp, mm, connsys, mfg, and cam.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 130 +++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index f669d37..9940c6d 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -15,6 +15,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
+#include <dt-bindings/power/mt6765-power.h>
#include <dt-bindings/power/mt6797-power.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
@@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct platform_device *pdev,
};
/*
+ * MT6765 power domain support
+ */
+#define SPM_PWR_STATUS_MT6765 0x0180
+#define SPM_PWR_STATUS_2ND_MT6765 0x0184
+
+static const struct scp_domain_data scp_domain_data_mt6765[] = {
+ [MT6765_POWER_DOMAIN_VCODEC] = {
+ .name = "vcodec",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x308,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
+ BIT(20), BIT(20)),
+ BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
+ BIT(2), BIT(2)),
+ },
+ },
+ [MT6765_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x30C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_id = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
+ BIT(16) | BIT(17), BIT(16) | BIT(17)),
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(1) | BIT(2), BIT(1) | BIT(2)),
+ },
+ },
+ [MT6765_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x32C,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(13), BIT(13)),
+ BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
+ BIT(18), BIT(18)),
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(14) | BIT(16), BIT(14) | BIT(16)),
+ },
+ },
+ [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_id = {"mfg"},
+ },
+ [MT6765_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(25), BIT(25)),
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(21) | BIT(22), BIT(21) | BIT(22)),
+ }
+ },
+ [MT6765_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x344,
+ .sram_pdn_bits = GENMASK(8, 9),
+ .sram_pdn_ack_bits = GENMASK(12, 13),
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
+ BIT(19) | BIT(21), BIT(19) | BIT(21)),
+ BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
+ BIT(20), BIT(20)),
+ BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
+ BIT(3), BIT(3)),
+ }
+ },
+ [MT6765_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x34C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt6765[] = {
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
+ {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
+ {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
+};
+
+/*
* MT6797 power domain support
*/
@@ -1032,6 +1147,18 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.bus_prot_reg_update = false,
};
+static const struct scp_soc_data mt6765_data = {
+ .domains = scp_domain_data_mt6765,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
+ .subdomains = scp_subdomain_mt6765,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
+ },
+ .bus_prot_reg_update = true,
+};
+
static const struct scp_soc_data mt6797_data = {
.domains = scp_domain_data_mt6797,
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -1088,6 +1215,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt2712-scpsys",
.data = &mt2712_data,
}, {
+ .compatible = "mediatek,mt6765-scpsys",
+ .data = &mt6765_data,
+ }, {
.compatible = "mediatek,mt6797-scpsys",
.data = &mt6797_data,
}, {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2020-02-21 10:12 ` [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
@ 2021-04-06 14:01 ` Matthias Brugger
2021-04-06 14:04 ` Matthias Brugger
0 siblings, 1 reply; 22+ messages in thread
From: Matthias Brugger @ 2021-04-06 14:01 UTC (permalink / raw)
To: Macpaul Lin, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
On 21/02/2020 11:12, Macpaul Lin wrote:
> From: Mars Cheng <mars.cheng@mediatek.com>
>
> This adds scpsys support for MT6765
> Add subdomain support for MT6765:
> isp, mm, connsys, mfg, and cam.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 130 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 130 insertions(+)
>
Unfortunately scpsys is deprecated in the meantime. Please port you patches to
the new mtk-pm-domains.c driver. The biggest difference is, that the domain and
subdomain structure of the pm domains is describe in device tree instead of
hard-coded in the driver.
Regards,
Matthias
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index f669d37..9940c6d 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -15,6 +15,7 @@
>
> #include <dt-bindings/power/mt2701-power.h>
> #include <dt-bindings/power/mt2712-power.h>
> +#include <dt-bindings/power/mt6765-power.h>
> #include <dt-bindings/power/mt6797-power.h>
> #include <dt-bindings/power/mt7622-power.h>
> #include <dt-bindings/power/mt7623a-power.h>
> @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> };
>
> /*
> + * MT6765 power domain support
> + */
> +#define SPM_PWR_STATUS_MT6765 0x0180
> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184
> +
> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
> + [MT6765_POWER_DOMAIN_VCODEC] = {
> + .name = "vcodec",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x300,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x308,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .subsys_clk_prefix = "isp",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(20), BIT(20)),
> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
> + BIT(2), BIT(2)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_MM] = {
> + .name = "mm",
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x30C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .basic_clk_id = {"mm"},
> + .subsys_clk_prefix = "mm",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(16) | BIT(17), BIT(16) | BIT(17)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(10) | BIT(11), BIT(10) | BIT(11)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(1) | BIT(2), BIT(1) | BIT(2)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x32C,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(13), BIT(13)),
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(18), BIT(18)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(14) | BIT(16), BIT(14) | BIT(16)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> + .sta_mask = BIT(23),
> + .ctl_offs = 0x334,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .basic_clk_id = {"mfg"},
> + },
> + [MT6765_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x338,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(25), BIT(25)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(21) | BIT(22), BIT(21) | BIT(22)),
> + }
> + },
> + [MT6765_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x344,
> + .sram_pdn_bits = GENMASK(8, 9),
> + .sram_pdn_ack_bits = GENMASK(12, 13),
> + .subsys_clk_prefix = "cam",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(19) | BIT(21), BIT(19) | BIT(21)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(20), BIT(20)),
> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
> + BIT(3), BIT(3)),
> + }
> + },
> + [MT6765_POWER_DOMAIN_MFG_CORE0] = {
> + .name = "mfg_core0",
> + .sta_mask = BIT(7),
> + .ctl_offs = 0x34C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> +};
> +
> +static const struct scp_subdomain scp_subdomain_mt6765[] = {
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
> +};
> +
> +/*
> * MT6797 power domain support
> */
>
> @@ -1032,6 +1147,18 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .bus_prot_reg_update = false,
> };
>
> +static const struct scp_soc_data mt6765_data = {
> + .domains = scp_domain_data_mt6765,
> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
> + .subdomains = scp_subdomain_mt6765,
> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
> + .regs = {
> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
> + },
> + .bus_prot_reg_update = true,
> +};
> +
> static const struct scp_soc_data mt6797_data = {
> .domains = scp_domain_data_mt6797,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
> @@ -1088,6 +1215,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .compatible = "mediatek,mt2712-scpsys",
> .data = &mt2712_data,
> }, {
> + .compatible = "mediatek,mt6765-scpsys",
> + .data = &mt6765_data,
> + }, {
> .compatible = "mediatek,mt6797-scpsys",
> .data = &mt6797_data,
> }, {
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2021-04-06 14:01 ` Matthias Brugger
@ 2021-04-06 14:04 ` Matthias Brugger
0 siblings, 0 replies; 22+ messages in thread
From: Matthias Brugger @ 2021-04-06 14:04 UTC (permalink / raw)
To: Macpaul Lin, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
On 06/04/2021 16:01, Matthias Brugger wrote:
>
>
> On 21/02/2020 11:12, Macpaul Lin wrote:
>> From: Mars Cheng <mars.cheng@mediatek.com>
>>
>> This adds scpsys support for MT6765
>> Add subdomain support for MT6765:
>> isp, mm, connsys, mfg, and cam.
>>
>> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
>> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>> ---
>> drivers/soc/mediatek/mtk-scpsys.c | 130 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 130 insertions(+)
>>
>
> Unfortunately scpsys is deprecated in the meantime. Please port you patches to
> the new mtk-pm-domains.c driver. The biggest difference is, that the domain and
> subdomain structure of the pm domains is describe in device tree instead of
> hard-coded in the driver.
>
I got confused by the email grouping in my mail client. I already gave the same
feedback in v10 :)
> Regards,
> Matthias
>
>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
>> index f669d37..9940c6d 100644
>> --- a/drivers/soc/mediatek/mtk-scpsys.c
>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
>> @@ -15,6 +15,7 @@
>>
>> #include <dt-bindings/power/mt2701-power.h>
>> #include <dt-bindings/power/mt2712-power.h>
>> +#include <dt-bindings/power/mt6765-power.h>
>> #include <dt-bindings/power/mt6797-power.h>
>> #include <dt-bindings/power/mt7622-power.h>
>> #include <dt-bindings/power/mt7623a-power.h>
>> @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>> };
>>
>> /*
>> + * MT6765 power domain support
>> + */
>> +#define SPM_PWR_STATUS_MT6765 0x0180
>> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184
>> +
>> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
>> + [MT6765_POWER_DOMAIN_VCODEC] = {
>> + .name = "vcodec",
>> + .sta_mask = BIT(26),
>> + .ctl_offs = 0x300,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + },
>> + [MT6765_POWER_DOMAIN_ISP] = {
>> + .name = "isp",
>> + .sta_mask = BIT(5),
>> + .ctl_offs = 0x308,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .subsys_clk_prefix = "isp",
>> + .bp_table = {
>> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> + BIT(20), BIT(20)),
>> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
>> + BIT(2), BIT(2)),
>> + },
>> + },
>> + [MT6765_POWER_DOMAIN_MM] = {
>> + .name = "mm",
>> + .sta_mask = BIT(3),
>> + .ctl_offs = 0x30C,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .basic_clk_id = {"mm"},
>> + .subsys_clk_prefix = "mm",
>> + .bp_table = {
>> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> + BIT(16) | BIT(17), BIT(16) | BIT(17)),
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(10) | BIT(11), BIT(10) | BIT(11)),
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(1) | BIT(2), BIT(1) | BIT(2)),
>> + },
>> + },
>> + [MT6765_POWER_DOMAIN_CONN] = {
>> + .name = "conn",
>> + .sta_mask = BIT(1),
>> + .ctl_offs = 0x32C,
>> + .sram_pdn_bits = 0,
>> + .sram_pdn_ack_bits = 0,
>> + .bp_table = {
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(13), BIT(13)),
>> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> + BIT(18), BIT(18)),
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(14) | BIT(16), BIT(14) | BIT(16)),
>> + },
>> + },
>> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
>> + .name = "mfg_async",
>> + .sta_mask = BIT(23),
>> + .ctl_offs = 0x334,
>> + .sram_pdn_bits = 0,
>> + .sram_pdn_ack_bits = 0,
>> + .basic_clk_id = {"mfg"},
>> + },
>> + [MT6765_POWER_DOMAIN_MFG] = {
>> + .name = "mfg",
>> + .sta_mask = BIT(4),
>> + .ctl_offs = 0x338,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .bp_table = {
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(25), BIT(25)),
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(21) | BIT(22), BIT(21) | BIT(22)),
>> + }
>> + },
>> + [MT6765_POWER_DOMAIN_CAM] = {
>> + .name = "cam",
>> + .sta_mask = BIT(25),
>> + .ctl_offs = 0x344,
>> + .sram_pdn_bits = GENMASK(8, 9),
>> + .sram_pdn_ack_bits = GENMASK(12, 13),
>> + .subsys_clk_prefix = "cam",
>> + .bp_table = {
>> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> + BIT(19) | BIT(21), BIT(19) | BIT(21)),
>> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> + BIT(20), BIT(20)),
>> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
>> + BIT(3), BIT(3)),
>> + }
>> + },
>> + [MT6765_POWER_DOMAIN_MFG_CORE0] = {
>> + .name = "mfg_core0",
>> + .sta_mask = BIT(7),
>> + .ctl_offs = 0x34C,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + },
>> +};
>> +
>> +static const struct scp_subdomain scp_subdomain_mt6765[] = {
>> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
>> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
>> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
>> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
>> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
>> +};
>> +
>> +/*
>> * MT6797 power domain support
>> */
>>
>> @@ -1032,6 +1147,18 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>> .bus_prot_reg_update = false,
>> };
>>
>> +static const struct scp_soc_data mt6765_data = {
>> + .domains = scp_domain_data_mt6765,
>> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
>> + .subdomains = scp_subdomain_mt6765,
>> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
>> + .regs = {
>> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
>> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
>> + },
>> + .bus_prot_reg_update = true,
>> +};
>> +
>> static const struct scp_soc_data mt6797_data = {
>> .domains = scp_domain_data_mt6797,
>> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
>> @@ -1088,6 +1215,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
>> .compatible = "mediatek,mt2712-scpsys",
>> .data = &mt2712_data,
>> }, {
>> + .compatible = "mediatek,mt6765-scpsys",
>> + .data = &mt6765_data,
>> + }, {
>> .compatible = "mediatek,mt6797-scpsys",
>> .data = &mt6797_data,
>> }, {
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
2020-02-21 10:12 ` [PATCH v8 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
2020-02-21 10:12 ` [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
@ 2020-02-21 10:12 ` Macpaul Lin
2021-03-09 16:08 ` Chun-Kuang Hu
2020-02-21 10:12 ` [PATCH v8 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
` (2 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Macpaul Lin @ 2020-02-21 10:12 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel,
Shawn Guo, Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
Add basic chip support for Mediatek 6765, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++++++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 458bbc4..22bdf1a 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
new file mode 100644
index 0000000..36dddff2
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt6765.dtsi"
+
+/ {
+ model = "MediaTek MT6765 EVB";
+ compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
new file mode 100644
index 0000000..2662470
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt6765-clk.h>
+
+/ {
+ compatible = "mediatek,mt6765";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x001>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x002>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x003>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x102>;
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+ };
+
+ clocks {
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x2000>, /* GICH */
+ <0 0x0c420000 0 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt6765-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt6765-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: pericfg@10003000 {
+ compatible = "mediatek,mt6765-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt6765-scpsys";
+ reg = <0 0x10006000 0 0x1000>; /* spm */
+ #power-domain-cells = <1>;
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&mmsys_config CLK_MM_SMI_COMMON>,
+ <&mmsys_config CLK_MM_SMI_COMM0>,
+ <&mmsys_config CLK_MM_SMI_COMM1>,
+ <&mmsys_config CLK_MM_SMI_LARB0>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&mmsys_config CLK_MM_SMI_IMG>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_DFP_VAD>,
+ <&camsys CLK_CAM>,
+ <&camsys CLK_CAM_CCU>,
+ <&mmsys_config CLK_MM_SMI_CAM>;
+ clock-names = "mfg", "mm",
+ "mm-0", "mm-1", "mm-2", "mm-3",
+ "isp-0", "isp-1", "cam-0", "cam-1",
+ "cam-2", "cam-3", "cam-4";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
+ apmixed: syscon@1000c000 {
+ compatible = "mediatek,mt6765-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt6765-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x50>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART0>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART1>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audio: syscon@11220000 {
+ compatible = "mediatek,mt6765-audsys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mipi_rx_ana_csi0a: syscon@11c10000 {
+ compatible = "mediatek,mt6765-mipi0a",
+ "syscon";
+ reg = <0 0x11c10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys_config: syscon@14000000 {
+ compatible = "mediatek,mt6765-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi_common@14002000 {
+ compatible = "mediatek,mt6765-smi-common", "syscon";
+ reg = <0 0x14002000 0 0x1000>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt6765-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ venc_gcon: syscon@17000000 {
+ compatible = "mediatek,mt6765-vcodecsys", "syscon";
+ reg = <0 0x17000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt6765-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ }; /* end of soc */
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support
2020-02-21 10:12 ` [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
@ 2021-03-09 16:08 ` Chun-Kuang Hu
2021-03-10 6:05 ` Macpaul Lin
0 siblings, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-03-09 16:08 UTC (permalink / raw)
To: Macpaul Lin
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, DTML, linux-kernel, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-clk, CC Hwang,
Loda Chou, Mediatek WSD Upstream
Hi, Macpaul:
Macpaul Lin <macpaul.lin@mediatek.com> 於 2020年2月21日 週五 下午6:22寫道：
>
> From: Mars Cheng <mars.cheng@mediatek.com>
>
> Add basic chip support for Mediatek 6765, include
> uart node with correct uart clocks, pwrap device
>
> Add clock controller nodes, include topckgen, infracfg,
> apmixedsys and subsystem.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++
> arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++++++++++++++++++++++++
> 3 files changed, 287 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 458bbc4..22bdf1a 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> new file mode 100644
> index 0000000..36dddff2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Mediatek MT6765
> + *
> + * (C) Copyright 2018. Mediatek, Inc.
> + *
> + * Mars Cheng <mars.cheng@mediatek.com>
> + */
> +
> +/dts-v1/;
> +#include "mt6765.dtsi"
> +
> +/ {
> + model = "MediaTek MT6765 EVB";
> + compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x1e800000>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
> new file mode 100644
> index 0000000..2662470
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
> @@ -0,0 +1,253 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Mediatek MT6765
> + *
> + * (C) Copyright 2018. Mediatek, Inc.
> + *
> + * Mars Cheng <mars.cheng@mediatek.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/mt6765-clk.h>
> +
> +/ {
> + compatible = "mediatek,mt6765";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
[snip]
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> + <0 0x0c100000 0 0x200000>, /* GICR */
> + <0 0x0c400000 0 0x2000>, /* GICC */
> + <0 0x0c410000 0 0x2000>, /* GICH */
> + <0 0x0c420000 0 0x20000>; /* GICV */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt6765-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt6765-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: pericfg@10003000 {
> + compatible = "mediatek,mt6765-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + };
> +
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt6765-scpsys";
> + reg = <0 0x10006000 0 0x1000>; /* spm */
> + #power-domain-cells = <1>;
> + clocks = <&topckgen CLK_TOP_MFG_SEL>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&mmsys_config CLK_MM_SMI_COMMON>,
> + <&mmsys_config CLK_MM_SMI_COMM0>,
> + <&mmsys_config CLK_MM_SMI_COMM1>,
> + <&mmsys_config CLK_MM_SMI_LARB0>,
> + <&imgsys CLK_IMG_LARB2>,
> + <&mmsys_config CLK_MM_SMI_IMG>,
> + <&camsys CLK_CAM_LARB3>,
> + <&camsys CLK_CAM_DFP_VAD>,
> + <&camsys CLK_CAM>,
> + <&camsys CLK_CAM_CCU>,
> + <&mmsys_config CLK_MM_SMI_CAM>;
> + clock-names = "mfg", "mm",
> + "mm-0", "mm-1", "mm-2", "mm-3",
> + "isp-0", "isp-1", "cam-0", "cam-1",
> + "cam-2", "cam-3", "cam-4";
> + infracfg = <&infracfg>;
> + smi_comm = <&smi_common>;
> + };
> +
> + apmixed: syscon@1000c000 {
> + compatible = "mediatek,mt6765-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + sysirq: interrupt-controller@10200a80 {
> + compatible = "mediatek,mt6765-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200a80 0 0x50>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt6765-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_UART0>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt6765-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x400>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_UART1>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + audio: syscon@11220000 {
> + compatible = "mediatek,mt6765-audsys", "syscon";
> + reg = <0 0x11220000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mipi_rx_ana_csi0a: syscon@11c10000 {
> + compatible = "mediatek,mt6765-mipi0a",
> + "syscon";
> + reg = <0 0x11c10000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys_config: syscon@14000000 {
> + compatible = "mediatek,mt6765-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
I does not see interrupts property in binding document [1], please add
this in binding document first.
I'm curious about this interrupt. In which condition would it be triggered?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=v5.12-rc2
Regards,
Chun-Kuang.
> + #clock-cells = <1>;
> + };
> +
> + smi_common: smi_common@14002000 {
> + compatible = "mediatek,mt6765-smi-common", "syscon";
> + reg = <0 0x14002000 0 0x1000>;
> + };
> +
> + imgsys: syscon@15020000 {
> + compatible = "mediatek,mt6765-imgsys", "syscon";
> + reg = <0 0x15020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + venc_gcon: syscon@17000000 {
> + compatible = "mediatek,mt6765-vcodecsys", "syscon";
> + reg = <0 0x17000000 0 0x10000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: syscon@1a000000 {
> + compatible = "mediatek,mt6765-camsys", "syscon";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> + }; /* end of soc */
> +};
> --
> 1.7.9.5
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support
2021-03-09 16:08 ` Chun-Kuang Hu
@ 2021-03-10 6:05 ` Macpaul Lin
0 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, DTML, linux-kernel, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-clk, CC Hwang,
Loda Chou, Mediatek WSD Upstream
On Wed, 2021-03-10 at 00:08 +0800, Chun-Kuang Hu wrote:
> Hi, Macpaul:
>
> Macpaul Lin <macpaul.lin@mediatek.com> 於 2020年2月21日 週五 下午6:22寫道：
> >
> > From: Mars Cheng <mars.cheng@mediatek.com>
> >
> > Add basic chip support for Mediatek 6765, include
> > uart node with correct uart clocks, pwrap device
> >
> > Add clock controller nodes, include topckgen, infracfg,
> > apmixedsys and subsystem.
> >
> > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> > Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++
> > arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++++++++++++++++++++++++
> > 3 files changed, 287 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
[deleted]
> > +
> > + mmsys_config: syscon@14000000 {
> > + compatible = "mediatek,mt6765-mmsys", "syscon";
> > + reg = <0 0x14000000 0 0x1000>;
> > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>
> I does not see interrupts property in binding document [1], please add
> this in binding document first.
> I'm curious about this interrupt. In which condition would it be triggered?
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=v5.12-rc2
>
> Regards,
> Chun-Kuang.
Thanks for reminding.
I'll remove interrupts binding in next version and leave it for mmsys
driver owner to update when the configuration of mmsys driver is
enabled.
[...]
> > + smi_common: smi_common@14002000 {
> > + compatible = "mediatek,mt6765-smi-common", "syscon";
> > + reg = <0 0x14002000 0 0x1000>;
> > + };
> > +
@Yong Wu
Thanks for reviewing here, I'll replace smi_common@14002000 to
smi@14002000
Regards,
Macpaul Lin
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v8 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
` (2 preceding siblings ...)
2020-02-21 10:12 ` [PATCH v8 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
@ 2020-02-21 10:12 ` Macpaul Lin
2020-06-18 11:06 ` [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
5 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2020-02-21 10:12 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, mtk01761,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Chunfeng Yun, Evan Green, Yong Wu, Joerg Roedel,
Shawn Guo, Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Mediatek WSD Upstream, CC Hwang, Loda Chou
From: Owen Chen <owen.chen@mediatek.com>
Enable MT6765 clock configs, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
arch/arm64/configs/defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6a83ba2..9d3da81 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -489,6 +489,12 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y
CONFIG_REGULATOR_QCOM_SPMI=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_S2MPS11=y
+CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y
+CONFIG_COMMON_CLK_MT6765_CAMSYS=y
+CONFIG_COMMON_CLK_MT6765_MMSYS=y
+CONFIG_COMMON_CLK_MT6765_IMGSYS=y
+CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
+CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y
CONFIG_REGULATOR_VCTRL=m
CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v8 0/4] Add basic SoC support for mt6765
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
` (3 preceding siblings ...)
2020-02-21 10:12 ` [PATCH v8 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
@ 2020-06-18 11:06 ` Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
5 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2020-06-18 11:06 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Stephen Boyd
Cc: Mark Rutland, Matthias Brugger, Catalin Marinas, Will Deacon,
Michael Turquette, Stephen Boyd, mtk01761, Fabien Parent,
Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen, Chunfeng Yun,
Evan Green, Yong Wu, Joerg Roedel, Shawn Guo, Marc Zyngier,
Ryder Lee, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-clk, Mediatek WSD Upstream, CC Hwang,
Loda Chou
On Fri, 2020-02-21 at 18:12 +0800, Macpaul Lin wrote:
> This patch adds basic SoC support for Mediatek's new 8-core SoC,
> MT6765, which is mainly for smartphone application.
>
> Changes in V8:
> 1. Origin V7 patchset:
> https://patchwork.kernel.org/cover/11370105/
> Split origin V7 patchset into 2 patchset,
> keep remain patches #2, #5, #6, and #7 in the same order as this
> V8 patchset.
> [v7,2/7] dt-bindings: mediatek: Add smi dts binding for Mediatek
> MT6765 SoC
> [v7,5/7] soc: mediatek: add MT6765 scpsys and subdomain support
> [v7,6/7] arm64: dts: mediatek: add mt6765 support
> [v7,7/7] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
>
> Changes in V7:
> 1. Adapt V6's patchset to latest kernel tree 5.5-rc1.
> Origin V6 patchset:
> https://patchwork.kernel.org/cover/11041963/
> 2. Correct 2 clock-controller type in documentation:
> mipi0 and venc_gcon.
> [v7 1/7] dt-bindings: clock: mediatek: document clk bindings
> 3. Remove V6's patch 03 because it has been taken into 5.5-next-soc
> [v6, 03/08] dt-bindings: mediatek: add MT6765 power dt-bindings
> 3. Update Reviewed-by: Rob Herring <robh@kernel.org> for
> [v6, 04/08] clk: mediatek: add mt6765 clock IDs
> --> [v7, 03/07] clk: mediatek: add mt6765 clock IDs
> 4. Update SPDX tag for
> [v6, 05/08] clk: mediatek: Add MT6765 clock support
> --> [v7, 04/07] clk: mediatek: Add MT6765 clock support
>
> Changes in V6:
> 1. Adapt V5's patchset to latest kernel tree.
> Origin V5 patchset.
> https://lore.kernel.org/patchwork/cover/963612/
> 2. Due to clk's common code has been submit by other platform,
> this patch set will have dependencies with the following patchsets
> as the following orders.
> 2.a. [v8,00/21] MT8183 IOMMU SUPPORT
> https://patchwork.kernel.org/cover/11023585/
> 2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC
> https://patchwork.kernel.org/cover/10962385/
> 2.c. [v6,00/14] Mediatek MT8183 scpsys support
> https://patchwork.kernel.org/cover/11005751/
> 3. Correct power related patches into dt-binding patches.
> 4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change
> and make dependencies in order.
> 5. Update some commit message in clk related patches.
>
> Changes in V5:
> 1. add clk support
>
> Changes in V4:
> 1. add gic's settings in reg properties
> 2. remove some patches about dt-bindings since GKH already took them
>
> Changes in V3:
> 1. split dt-binding document patchs
> 2. fix mt6765.dtsi warnings with W=12
> 3. remove uncessary PPI affinity for timer
> 4. add gicc base for gic dt node
>
> Changes in V2:
> 1. fix clk properties in uart dts node
> 2. fix typo in submit title
> 3. add simple-bus in mt6765.dtsi
> 4. use correct SPDX license format
>
> Mars Cheng (3):
> dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
> soc: mediatek: add MT6765 scpsys and subdomain support
> arm64: dts: mediatek: add mt6765 support
>
> Owen Chen (1):
> arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
>
> .../memory-controllers/mediatek,smi-common.txt | 1 +
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
> arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++
> arch/arm64/configs/defconfig | 6 +
> drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++
> 6 files changed, 424 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
>
Dear Matthias and Rob,
Just a remind of these patches related to MT6765.
Thanks for Stephen's help, the other clock related patches of MT6765 has
been already merged into 5.8-rc1. I've tested these v8 patches of MT6765
on 5.8-rc1 and seems they were able to be applied. Could you kindly help
to check if these patches were qualified to be merged into your tree?
Thanks a lot!
Best regards,
Macpaul Lin
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v9 0/4] Add basic SoC support for mt6765
2020-02-21 10:12 [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
` (4 preceding siblings ...)
2020-06-18 11:06 ` [PATCH v8 0/4] Add basic SoC support for mt6765 Macpaul Lin
@ 2021-03-09 12:05 ` Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
` (4 more replies)
5 siblings, 5 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-09 12:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
This patch adds basic SoC support for Mediatek's new 8-core SoC,
MT6765, which is mainly for smartphone application.
Changes in V9:
1. Origin V8 patchset:
https://patchwork.kernel.org/cover/11396015/
[v9,1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek
MT6765 SoC
- No Change.
[v9,2/4] soc: mediatek: add MT6765 scpsys and subdomain support
- Fix build error based on 5.11-rc1 because
- bp_table has been deprecated.
- basic_clk_id has been renamed to clk_id.
- correct the number order in marco GENMASK().
Note: mediatek is working on porting mt6765's scpsys to driver
"mtk-pm-domains", however we think supporting for "mtk-scpsys" is
required before new glue is available.
[v9,3/4] arm64: dts: mediatek: add mt6765 support
- No Change.
[v9,4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
- No Change.
Changes in V8:
1. Origin V7 patchset:
https://patchwork.kernel.org/cover/11370105/
Split origin V7 patchset into 2 patchset,
keep remain patches #2, #5, #6, and #7 in the same order as this
V8 patchset.
[v7,2/7] dt-bindings: mediatek: Add smi dts binding for Mediatek
MT6765 SoC
[v7,5/7] soc: mediatek: add MT6765 scpsys and subdomain support
[v7,6/7] arm64: dts: mediatek: add mt6765 support
[v7,7/7] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
Changes in V7:
1. Adapt V6's patchset to latest kernel tree 5.5-rc1.
Origin V6 patchset:
https://patchwork.kernel.org/cover/11041963/
2. Correct 2 clock-controller type in documentation:
mipi0 and venc_gcon.
[v7 1/7] dt-bindings: clock: mediatek: document clk bindings
3. Remove V6's patch 03 because it has been taken into 5.5-next-soc
[v6, 03/08] dt-bindings: mediatek: add MT6765 power dt-bindings
3. Update Reviewed-by: Rob Herring <robh@kernel.org> for
[v6, 04/08] clk: mediatek: add mt6765 clock IDs
--> [v7, 03/07] clk: mediatek: add mt6765 clock IDs
4. Update SPDX tag for
[v6, 05/08] clk: mediatek: Add MT6765 clock support
--> [v7, 04/07] clk: mediatek: Add MT6765 clock support
Changes in V6:
1. Adapt V5's patchset to latest kernel tree.
Origin V5 patchset.
https://lore.kernel.org/patchwork/cover/963612/
2. Due to clk's common code has been submit by other platform,
this patch set will have dependencies with the following patchsets
as the following orders.
2.a. [v8,00/21] MT8183 IOMMU SUPPORT
https://patchwork.kernel.org/cover/11023585/
2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC
https://patchwork.kernel.org/cover/10962385/
2.c. [v6,00/14] Mediatek MT8183 scpsys support
https://patchwork.kernel.org/cover/11005751/
3. Correct power related patches into dt-binding patches.
4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change
and make dependencies in order.
5. Update some commit message in clk related patches.
Changes in V5:
1. add clk support
Changes in V4:
1. add gic's settings in reg properties
2. remove some patches about dt-bindings since GKH already took them
Changes in V3:
1. split dt-binding document patchs
2. fix mt6765.dtsi warnings with W=12
3. remove uncessary PPI affinity for timer
4. add gicc base for gic dt node
Changes in V2:
1. fix clk properties in uart dts node
2. fix typo in submit title
3. add simple-bus in mt6765.dtsi
4. use correct SPDX license format
Mars Cheng (3):
dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
soc: mediatek: add MT6765 scpsys and subdomain support
arm64: dts: mediatek: add mt6765 support
Owen Chen (1):
arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
.../memory-controllers/mediatek,smi-common.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++
arch/arm64/configs/defconfig | 6 +
drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++
6 files changed, 424 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
--
1.7.9.5
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v9 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
@ 2021-03-09 12:05 ` Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
` (3 subsequent siblings)
4 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-09 12:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This patch adds MT6765 smi binding document
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/memory-controllers/mediatek,smi-common.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index a08a32340987..4a4f4377576f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -31,6 +31,7 @@ properties:
- enum:
- mediatek,mt2701-smi-common
- mediatek,mt2712-smi-common
+ - mediatek,mt6765-smi-common
- mediatek,mt6779-smi-common
- mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
@ 2021-03-09 12:05 ` Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
` (2 subsequent siblings)
4 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-09 12:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This adds scpsys support for MT6765
Add subdomain support for MT6765:
isp, mm, connsys, mfg, and cam.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 91 +++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index ca75b14931ec..fc8d3858f1b4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -15,6 +15,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
+#include <dt-bindings/power/mt6765-power.h>
#include <dt-bindings/power/mt6797-power.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
@@ -750,6 +751,81 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = {
{MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
};
+/*
+ * MT6765 power domain support
+ */
+#define SPM_PWR_STATUS_MT6765 0x0180
+#define SPM_PWR_STATUS_2ND_MT6765 0x0184
+
+static const struct scp_domain_data scp_domain_data_mt6765[] = {
+ [MT6765_POWER_DOMAIN_VCODEC] = {
+ .name = "vcodec",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x308,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x30C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT6765_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x32C,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ },
+ [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT6765_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT6765_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x34C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt6765[] = {
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
+ {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
+ {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
+};
+
/*
* MT6797 power domain support
*/
@@ -1033,6 +1109,18 @@ static const struct scp_soc_data mt2712_data = {
.bus_prot_reg_update = false,
};
+static const struct scp_soc_data mt6765_data = {
+ .domains = scp_domain_data_mt6765,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
+ .subdomains = scp_subdomain_mt6765,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
+ },
+ .bus_prot_reg_update = true,
+};
+
static const struct scp_soc_data mt6797_data = {
.domains = scp_domain_data_mt6797,
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -1088,6 +1176,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
}, {
.compatible = "mediatek,mt2712-scpsys",
.data = &mt2712_data,
+ }, {
+ .compatible = "mediatek,mt6765-scpsys",
+ .data = &mt6765_data,
}, {
.compatible = "mediatek,mt6797-scpsys",
.data = &mt6797_data,
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 3/4] arm64: dts: mediatek: add mt6765 support
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
@ 2021-03-09 12:05 ` Macpaul Lin
2021-03-09 12:05 ` [PATCH v9 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
4 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-09 12:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
Add basic chip support for Mediatek 6765, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index deba27ab7657..176c817f9f9a 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
new file mode 100644
index 000000000000..36dddff2b7f8
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt6765.dtsi"
+
+/ {
+ model = "MediaTek MT6765 EVB";
+ compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
new file mode 100644
index 000000000000..2662470fe607
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt6765-clk.h>
+
+/ {
+ compatible = "mediatek,mt6765";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x001>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x002>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x003>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x102>;
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+ };
+
+ clocks {
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x2000>, /* GICH */
+ <0 0x0c420000 0 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt6765-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt6765-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: pericfg@10003000 {
+ compatible = "mediatek,mt6765-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt6765-scpsys";
+ reg = <0 0x10006000 0 0x1000>; /* spm */
+ #power-domain-cells = <1>;
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&mmsys_config CLK_MM_SMI_COMMON>,
+ <&mmsys_config CLK_MM_SMI_COMM0>,
+ <&mmsys_config CLK_MM_SMI_COMM1>,
+ <&mmsys_config CLK_MM_SMI_LARB0>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&mmsys_config CLK_MM_SMI_IMG>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_DFP_VAD>,
+ <&camsys CLK_CAM>,
+ <&camsys CLK_CAM_CCU>,
+ <&mmsys_config CLK_MM_SMI_CAM>;
+ clock-names = "mfg", "mm",
+ "mm-0", "mm-1", "mm-2", "mm-3",
+ "isp-0", "isp-1", "cam-0", "cam-1",
+ "cam-2", "cam-3", "cam-4";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
+ apmixed: syscon@1000c000 {
+ compatible = "mediatek,mt6765-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt6765-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x50>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART0>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART1>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audio: syscon@11220000 {
+ compatible = "mediatek,mt6765-audsys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mipi_rx_ana_csi0a: syscon@11c10000 {
+ compatible = "mediatek,mt6765-mipi0a",
+ "syscon";
+ reg = <0 0x11c10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys_config: syscon@14000000 {
+ compatible = "mediatek,mt6765-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi_common@14002000 {
+ compatible = "mediatek,mt6765-smi-common", "syscon";
+ reg = <0 0x14002000 0 0x1000>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt6765-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ venc_gcon: syscon@17000000 {
+ compatible = "mediatek,mt6765-vcodecsys", "syscon";
+ reg = <0 0x17000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt6765-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ }; /* end of soc */
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
` (2 preceding siblings ...)
2021-03-09 12:05 ` [PATCH v9 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
@ 2021-03-09 12:05 ` Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
4 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-09 12:05 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Owen Chen <owen.chen@mediatek.com>
Enable MT6765 clock configs, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
arch/arm64/configs/defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d612f633b771..553137e81b8e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -622,6 +622,12 @@ CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_VCTRL=m
+CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y
+CONFIG_COMMON_CLK_MT6765_CAMSYS=y
+CONFIG_COMMON_CLK_MT6765_MMSYS=y
+CONFIG_COMMON_CLK_MT6765_IMGSYS=y
+CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
+CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y
CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
CONFIG_RC_DEVICES=y
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v10 0/4] Add basic SoC support for mt6765
2021-03-09 12:05 ` [PATCH v9 " Macpaul Lin
` (3 preceding siblings ...)
2021-03-09 12:05 ` [PATCH v9 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
@ 2021-03-10 6:36 ` Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
` (3 more replies)
4 siblings, 4 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:36 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
This patch adds basic SoC support for Mediatek's new 8-core SoC,
MT6765, which is mainly for smartphone application.
Changes in V10:
[v10,1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek
MT6765 SoC
- No Change.
[v10,2/4] soc: mediatek: add MT6765 scpsys and subdomain support
- No Change.
[v10,3/4] arm64: dts: mediatek: add mt6765 support
- Remove interrupt in mmsys node.
- Replace smi_common@14002000 to smi@14002000
[v10,4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
- No Change.
Changes in V9:
1. Origin V8 patchset:
https://patchwork.kernel.org/cover/11396015/
[v9,1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek
MT6765 SoC
- No Change.
[v9,2/4] soc: mediatek: add MT6765 scpsys and subdomain support
- Fix build error based on 5.11-rc1 because
- bp_table has been deprecated.
- basic_clk_id has been renamed to clk_id.
- correct the number order in marco GENMASK().
Note: mediatek is working on porting mt6765's scpsys to driver
"mtk-pm-domains", however we think supporting for "mtk-scpsys" is
required before new glue is available.
[v9,3/4] arm64: dts: mediatek: add mt6765 support
- No Change.
[v9,4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
- No Change.
Changes in V8:
1. Origin V7 patchset:
https://patchwork.kernel.org/cover/11370105/
Split origin V7 patchset into 2 patchset,
keep remain patches #2, #5, #6, and #7 in the same order as this
V8 patchset.
[v7,2/7] dt-bindings: mediatek: Add smi dts binding for Mediatek
MT6765 SoC
[v7,5/7] soc: mediatek: add MT6765 scpsys and subdomain support
[v7,6/7] arm64: dts: mediatek: add mt6765 support
[v7,7/7] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
Changes in V7:
1. Adapt V6's patchset to latest kernel tree 5.5-rc1.
Origin V6 patchset:
https://patchwork.kernel.org/cover/11041963/
2. Correct 2 clock-controller type in documentation:
mipi0 and venc_gcon.
[v7 1/7] dt-bindings: clock: mediatek: document clk bindings
3. Remove V6's patch 03 because it has been taken into 5.5-next-soc
[v6, 03/08] dt-bindings: mediatek: add MT6765 power dt-bindings
3. Update Reviewed-by: Rob Herring <robh@kernel.org> for
[v6, 04/08] clk: mediatek: add mt6765 clock IDs
--> [v7, 03/07] clk: mediatek: add mt6765 clock IDs
4. Update SPDX tag for
[v6, 05/08] clk: mediatek: Add MT6765 clock support
--> [v7, 04/07] clk: mediatek: Add MT6765 clock support
Changes in V6:
1. Adapt V5's patchset to latest kernel tree.
Origin V5 patchset.
https://lore.kernel.org/patchwork/cover/963612/
2. Due to clk's common code has been submit by other platform,
this patch set will have dependencies with the following patchsets
as the following orders.
2.a. [v8,00/21] MT8183 IOMMU SUPPORT
https://patchwork.kernel.org/cover/11023585/
2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC
https://patchwork.kernel.org/cover/10962385/
2.c. [v6,00/14] Mediatek MT8183 scpsys support
https://patchwork.kernel.org/cover/11005751/
3. Correct power related patches into dt-binding patches.
4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change
and make dependencies in order.
5. Update some commit message in clk related patches.
Changes in V5:
1. add clk support
Changes in V4:
1. add gic's settings in reg properties
2. remove some patches about dt-bindings since GKH already took them
Changes in V3:
1. split dt-binding document patchs
2. fix mt6765.dtsi warnings with W=12
3. remove uncessary PPI affinity for timer
4. add gicc base for gic dt node
Changes in V2:
1. fix clk properties in uart dts node
2. fix typo in submit title
3. add simple-bus in mt6765.dtsi
4. use correct SPDX license format
Mars Cheng (3):
dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
soc: mediatek: add MT6765 scpsys and subdomain support
arm64: dts: mediatek: add mt6765 support
Owen Chen (1):
arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
.../mediatek,smi-common.yaml | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 252 ++++++++++++++++++
arch/arm64/configs/defconfig | 6 +
drivers/soc/mediatek/mtk-scpsys.c | 91 +++++++
6 files changed, 384 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
--
2.18.0
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
@ 2021-03-10 6:36 ` Macpaul Lin
2021-03-30 10:48 ` Matthias Brugger
2021-03-10 6:36 ` [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
` (2 subsequent siblings)
3 siblings, 1 reply; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:36 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This patch adds MT6765 smi binding document
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/memory-controllers/mediatek,smi-common.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index a08a32340987..4a4f4377576f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -31,6 +31,7 @@ properties:
- enum:
- mediatek,mt2701-smi-common
- mediatek,mt2712-smi-common
+ - mediatek,mt6765-smi-common
- mediatek,mt6779-smi-common
- mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
2021-03-10 6:36 ` [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
@ 2021-03-30 10:48 ` Matthias Brugger
0 siblings, 0 replies; 22+ messages in thread
From: Matthias Brugger @ 2021-03-30 10:48 UTC (permalink / raw)
To: Macpaul Lin, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo, Marc Zyngier,
Ryder Lee, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-clk, Krzysztof Kozlowski
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
CC Hwang, Loda Chou
On 10/03/2021 07:36, Macpaul Lin wrote:
> From: Mars Cheng <mars.cheng@mediatek.com>
>
> This patch adds MT6765 smi binding document
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
Patch looks good, but where is the driver part for it?
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> .../bindings/memory-controllers/mediatek,smi-common.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> index a08a32340987..4a4f4377576f 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> @@ -31,6 +31,7 @@ properties:
> - enum:
> - mediatek,mt2701-smi-common
> - mediatek,mt2712-smi-common
> + - mediatek,mt6765-smi-common
> - mediatek,mt6779-smi-common
> - mediatek,mt8167-smi-common
> - mediatek,mt8173-smi-common
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
@ 2021-03-10 6:36 ` Macpaul Lin
2021-04-01 9:24 ` Matthias Brugger
2021-03-10 6:36 ` [PATCH v10 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
3 siblings, 1 reply; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:36 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
This adds scpsys support for MT6765
Add subdomain support for MT6765:
isp, mm, connsys, mfg, and cam.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 91 +++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index ca75b14931ec..fc8d3858f1b4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -15,6 +15,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
+#include <dt-bindings/power/mt6765-power.h>
#include <dt-bindings/power/mt6797-power.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
@@ -750,6 +751,81 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = {
{MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
};
+/*
+ * MT6765 power domain support
+ */
+#define SPM_PWR_STATUS_MT6765 0x0180
+#define SPM_PWR_STATUS_2ND_MT6765 0x0184
+
+static const struct scp_domain_data scp_domain_data_mt6765[] = {
+ [MT6765_POWER_DOMAIN_VCODEC] = {
+ .name = "vcodec",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x308,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x30C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT6765_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x32C,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ },
+ [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT6765_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT6765_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x34C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt6765[] = {
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
+ {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
+ {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
+};
+
/*
* MT6797 power domain support
*/
@@ -1033,6 +1109,18 @@ static const struct scp_soc_data mt2712_data = {
.bus_prot_reg_update = false,
};
+static const struct scp_soc_data mt6765_data = {
+ .domains = scp_domain_data_mt6765,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
+ .subdomains = scp_subdomain_mt6765,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
+ },
+ .bus_prot_reg_update = true,
+};
+
static const struct scp_soc_data mt6797_data = {
.domains = scp_domain_data_mt6797,
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -1088,6 +1176,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
}, {
.compatible = "mediatek,mt2712-scpsys",
.data = &mt2712_data,
+ }, {
+ .compatible = "mediatek,mt6765-scpsys",
+ .data = &mt6765_data,
}, {
.compatible = "mediatek,mt6797-scpsys",
.data = &mt6797_data,
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
2021-03-10 6:36 ` [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
@ 2021-04-01 9:24 ` Matthias Brugger
0 siblings, 0 replies; 22+ messages in thread
From: Matthias Brugger @ 2021-04-01 9:24 UTC (permalink / raw)
To: Macpaul Lin, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Owen Chen,
Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo, Marc Zyngier,
Ryder Lee, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
CC Hwang, Loda Chou
Hi Macpaul,
On 10/03/2021 07:36, Macpaul Lin wrote:
> From: Mars Cheng <mars.cheng@mediatek.com>
>
> This adds scpsys support for MT6765
> Add subdomain support for MT6765:
> isp, mm, connsys, mfg, and cam.
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 91 +++++++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
the mtk-scpsys is the old version of the driver. Please port your code to the
new driver: mtk-pm-domains.c
The biggest difference for you will be to describe the power domain hierarchy in
DT instead as in the driver.
Regards,
Matthias
> index ca75b14931ec..fc8d3858f1b4 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -15,6 +15,7 @@
>
> #include <dt-bindings/power/mt2701-power.h>
> #include <dt-bindings/power/mt2712-power.h>
> +#include <dt-bindings/power/mt6765-power.h>
> #include <dt-bindings/power/mt6797-power.h>
> #include <dt-bindings/power/mt7622-power.h>
> #include <dt-bindings/power/mt7623a-power.h>
> @@ -750,6 +751,81 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = {
> {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
> };
>
> +/*
> + * MT6765 power domain support
> + */
> +#define SPM_PWR_STATUS_MT6765 0x0180
> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184
> +
> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
> + [MT6765_POWER_DOMAIN_VCODEC] = {
> + .name = "vcodec",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x300,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x308,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_MM] = {
> + .name = "mm",
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x30C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .clk_id = {CLK_MM},
> + },
> + [MT6765_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x32C,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + },
> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> + .sta_mask = BIT(23),
> + .ctl_offs = 0x334,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .clk_id = {CLK_MFG},
> + },
> + [MT6765_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x338,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x344,
> + .sram_pdn_bits = GENMASK(9, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + },
> + [MT6765_POWER_DOMAIN_MFG_CORE0] = {
> + .name = "mfg_core0",
> + .sta_mask = BIT(7),
> + .ctl_offs = 0x34C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> +};
> +
> +static const struct scp_subdomain scp_subdomain_mt6765[] = {
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
> +};
> +
> /*
> * MT6797 power domain support
> */
> @@ -1033,6 +1109,18 @@ static const struct scp_soc_data mt2712_data = {
> .bus_prot_reg_update = false,
> };
>
> +static const struct scp_soc_data mt6765_data = {
> + .domains = scp_domain_data_mt6765,
> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
> + .subdomains = scp_subdomain_mt6765,
> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
> + .regs = {
> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
> + },
> + .bus_prot_reg_update = true,
> +};
> +
> static const struct scp_soc_data mt6797_data = {
> .domains = scp_domain_data_mt6797,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
> @@ -1088,6 +1176,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
> }, {
> .compatible = "mediatek,mt2712-scpsys",
> .data = &mt2712_data,
> + }, {
> + .compatible = "mediatek,mt6765-scpsys",
> + .data = &mt6765_data,
> }, {
> .compatible = "mediatek,mt6797-scpsys",
> .data = &mt6797_data,
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v10 3/4] arm64: dts: mediatek: add mt6765 support
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
@ 2021-03-10 6:36 ` Macpaul Lin
2021-03-10 6:36 ` [PATCH v10 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
3 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:36 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Mars Cheng <mars.cheng@mediatek.com>
Add basic chip support for Mediatek 6765, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 252 ++++++++++++++++++++
3 files changed, 286 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index deba27ab7657..176c817f9f9a 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
new file mode 100644
index 000000000000..36dddff2b7f8
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt6765.dtsi"
+
+/ {
+ model = "MediaTek MT6765 EVB";
+ compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
new file mode 100644
index 000000000000..21683f3e1a3f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt6765-clk.h>
+
+/ {
+ compatible = "mediatek,mt6765";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x001>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x002>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x003>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x102>;
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+ };
+
+ clocks {
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x2000>, /* GICH */
+ <0 0x0c420000 0 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt6765-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt6765-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: pericfg@10003000 {
+ compatible = "mediatek,mt6765-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt6765-scpsys";
+ reg = <0 0x10006000 0 0x1000>; /* spm */
+ #power-domain-cells = <1>;
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&mmsys_config CLK_MM_SMI_COMMON>,
+ <&mmsys_config CLK_MM_SMI_COMM0>,
+ <&mmsys_config CLK_MM_SMI_COMM1>,
+ <&mmsys_config CLK_MM_SMI_LARB0>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&mmsys_config CLK_MM_SMI_IMG>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_DFP_VAD>,
+ <&camsys CLK_CAM>,
+ <&camsys CLK_CAM_CCU>,
+ <&mmsys_config CLK_MM_SMI_CAM>;
+ clock-names = "mfg", "mm",
+ "mm-0", "mm-1", "mm-2", "mm-3",
+ "isp-0", "isp-1", "cam-0", "cam-1",
+ "cam-2", "cam-3", "cam-4";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
+ apmixed: syscon@1000c000 {
+ compatible = "mediatek,mt6765-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt6765-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x50>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART0>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART1>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audio: syscon@11220000 {
+ compatible = "mediatek,mt6765-audsys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mipi_rx_ana_csi0a: syscon@11c10000 {
+ compatible = "mediatek,mt6765-mipi0a",
+ "syscon";
+ reg = <0 0x11c10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys_config: syscon@14000000 {
+ compatible = "mediatek,mt6765-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt6765-smi-common", "syscon";
+ reg = <0 0x14002000 0 0x1000>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt6765-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ venc_gcon: syscon@17000000 {
+ compatible = "mediatek,mt6765-vcodecsys", "syscon";
+ reg = <0 0x17000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt6765-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ }; /* end of soc */
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v10 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks
2021-03-10 6:36 ` [PATCH v10 0/4] Add basic SoC support for mt6765 Macpaul Lin
` (2 preceding siblings ...)
2021-03-10 6:36 ` [PATCH v10 3/4] arm64: dts: mediatek: add mt6765 support Macpaul Lin
@ 2021-03-10 6:36 ` Macpaul Lin
3 siblings, 0 replies; 22+ messages in thread
From: Macpaul Lin @ 2021-03-10 6:36 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Catalin Marinas,
Will Deacon, Michael Turquette, Stephen Boyd, Wendell Lin,
Fabien Parent, Weiyi Lu, Mars Cheng, Sean Wang, Macpaul Lin,
Owen Chen, Evan Green, Yong.Wu, Joerg Roedel, Shawn Guo,
Marc Zyngier, Ryder Lee, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-clk
Cc: Ainge Hsu, Eddie Hung, Mediatek WSD Upstream, Macpaul Lin,
Macpaul Lin, CC Hwang, Loda Chou
From: Owen Chen <owen.chen@mediatek.com>
Enable MT6765 clock configs, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
arch/arm64/configs/defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d612f633b771..553137e81b8e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -622,6 +622,12 @@ CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_VCTRL=m
+CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y
+CONFIG_COMMON_CLK_MT6765_CAMSYS=y
+CONFIG_COMMON_CLK_MT6765_MMSYS=y
+CONFIG_COMMON_CLK_MT6765_IMGSYS=y
+CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
+CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y
CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
CONFIG_RC_DEVICES=y
--
2.18.0
^ permalink raw reply related [flat|nested] 22+ messages in thread