* [v8 0/3] Add L3 provider support for SC7280
@ 2021-10-21 10:40 Odelu Kukatla
2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Odelu Kukatla @ 2021-10-21 10:40 UTC (permalink / raw)
To: georgi.djakov, bjorn.andersson, evgreen
Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder,
linux-kernel, linux-arm-msm, linux-pm, linux-arm-msm-owner
Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.
v8:
- Addressed Stephen's comments from v7
- Resolved region mapping conflict between cpufreq-hw and epss_l3 devices.
Odelu Kukatla (3):
dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
interconnect: qcom: Add EPSS L3 support on SC7280
arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
drivers/interconnect/qcom/sc7280.h | 2 ++
4 files changed, 30 insertions(+), 1 deletion(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 14+ messages in thread* [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla @ 2021-10-21 10:40 ` Odelu Kukatla 2021-10-27 16:59 ` Rob Herring 2021-10-28 22:13 ` Stephen Boyd 2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 2 siblings, 2 replies; 14+ messages in thread From: Odelu Kukatla @ 2021-10-21 10:40 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Georgi Djakov, Rob Herring, Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel Cc: sboyd, mdtipton, saravanak, okukatla, seansw, elder, linux-arm-msm-owner Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index e701524..116e434 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,sc7180-osm-l3 + - qcom,sc7280-epss-l3 - qcom,sc8180x-osm-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-10-27 16:59 ` Rob Herring 2021-10-28 22:13 ` Stephen Boyd 1 sibling, 0 replies; 14+ messages in thread From: Rob Herring @ 2021-10-27 16:59 UTC (permalink / raw) To: Odelu Kukatla Cc: sboyd, Georgi Djakov, mdtipton, Andy Gross, linux-pm, linux-arm-msm-owner, evgreen, bjorn.andersson, Rob Herring, seansw, georgi.djakov, saravanak, elder, devicetree, linux-arm-msm, linux-kernel, Sibi Sankar On Thu, 21 Oct 2021 16:10:55 +0530, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla 2021-10-27 16:59 ` Rob Herring @ 2021-10-28 22:13 ` Stephen Boyd 1 sibling, 0 replies; 14+ messages in thread From: Stephen Boyd @ 2021-10-28 22:13 UTC (permalink / raw) To: Andy Gross, Georgi Djakov, Odelu Kukatla, Rob Herring, Sibi Sankar, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, linux-pm Cc: mdtipton, saravanak, okukatla, seansw, elder, linux-arm-msm-owner Quoting Odelu Kukatla (2021-10-21 03:40:55) > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280 2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla 2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-10-21 10:40 ` Odelu Kukatla 2021-10-28 22:13 ` Stephen Boyd 2021-11-18 20:53 ` Bjorn Andersson 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 2 siblings, 2 replies; 14+ messages in thread From: Odelu Kukatla @ 2021-10-21 10:40 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Georgi Djakov, linux-arm-msm, linux-pm, linux-kernel Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder, linux-arm-msm-owner Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++- drivers/interconnect/qcom/sc7280.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index c7af143..eec1309 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include <linux/bitfield.h> @@ -15,6 +15,7 @@ #include <dt-bindings/interconnect/qcom,osm-l3.h> #include "sc7180.h" +#include "sc7280.h" #include "sc8180x.h" #include "sdm845.h" #include "sm8150.h" @@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; +DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); +DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); + +static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { + [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, + [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, +}; + +static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { + .nodes = sc7280_epss_l3_nodes, + .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_PERF_STATE, +}; + DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); @@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, + { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 }, diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h index 175e400..1fb9839 100644 --- a/drivers/interconnect/qcom/sc7280.h +++ b/drivers/interconnect/qcom/sc7280.h @@ -150,5 +150,7 @@ #define SC7280_SLAVE_PCIE_1 139 #define SC7280_SLAVE_QDSS_STM 140 #define SC7280_SLAVE_TCU 141 +#define SC7280_MASTER_EPSS_L3_APPS 142 +#define SC7280_SLAVE_EPSS_L3 143 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280 2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla @ 2021-10-28 22:13 ` Stephen Boyd 2021-11-18 20:53 ` Bjorn Andersson 1 sibling, 0 replies; 14+ messages in thread From: Stephen Boyd @ 2021-10-28 22:13 UTC (permalink / raw) To: Andy Gross, Georgi Djakov, Odelu Kukatla, bjorn.andersson, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, linux-pm Cc: mdtipton, sibis, saravanak, okukatla, seansw, elder, linux-arm-msm-owner Quoting Odelu Kukatla (2021-10-21 03:40:56) > Add Epoch Subsystem (EPSS) L3 interconnect provider support on > SC7280 SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280 2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla 2021-10-28 22:13 ` Stephen Boyd @ 2021-11-18 20:53 ` Bjorn Andersson 2021-11-22 15:25 ` Georgi Djakov 1 sibling, 1 reply; 14+ messages in thread From: Bjorn Andersson @ 2021-11-18 20:53 UTC (permalink / raw) To: Odelu Kukatla, georgi.djakov Cc: evgreen, Andy Gross, Georgi Djakov, linux-arm-msm, linux-pm, linux-kernel, sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-arm-msm-owner On Thu 21 Oct 05:40 CDT 2021, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider support on > SC7280 SoCs. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> @Georgi, do you intend to apply the two interconnect patches in this series? Regards, Bjorn > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++- > drivers/interconnect/qcom/sc7280.h | 2 ++ > 2 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c > index c7af143..eec1309 100644 > --- a/drivers/interconnect/qcom/osm-l3.c > +++ b/drivers/interconnect/qcom/osm-l3.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. > */ > > #include <linux/bitfield.h> > @@ -15,6 +15,7 @@ > #include <dt-bindings/interconnect/qcom,osm-l3.h> > > #include "sc7180.h" > +#include "sc7280.h" > #include "sc8180x.h" > #include "sdm845.h" > #include "sm8150.h" > @@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { > .reg_perf_state = OSM_REG_PERF_STATE, > }; > > +DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); > +DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); > + > +static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { > + [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, > + [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, > +}; > + > +static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { > + .nodes = sc7280_epss_l3_nodes, > + .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes), > + .lut_row_size = EPSS_LUT_ROW_SIZE, > + .reg_freq_lut = EPSS_REG_FREQ_LUT, > + .reg_perf_state = EPSS_REG_PERF_STATE, > +}; > + > DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); > DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); > > @@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) > > static const struct of_device_id osm_l3_of_match[] = { > { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, > + { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 }, > { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, > { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, > { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 }, > diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h > index 175e400..1fb9839 100644 > --- a/drivers/interconnect/qcom/sc7280.h > +++ b/drivers/interconnect/qcom/sc7280.h > @@ -150,5 +150,7 @@ > #define SC7280_SLAVE_PCIE_1 139 > #define SC7280_SLAVE_QDSS_STM 140 > #define SC7280_SLAVE_TCU 141 > +#define SC7280_MASTER_EPSS_L3_APPS 142 > +#define SC7280_SLAVE_EPSS_L3 143 > > #endif > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280 2021-11-18 20:53 ` Bjorn Andersson @ 2021-11-22 15:25 ` Georgi Djakov 0 siblings, 0 replies; 14+ messages in thread From: Georgi Djakov @ 2021-11-22 15:25 UTC (permalink / raw) To: Bjorn Andersson, Odelu Kukatla, georgi.djakov Cc: evgreen, Andy Gross, linux-arm-msm, linux-pm, linux-kernel, sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-arm-msm-owner On 18.11.21 22:53, Bjorn Andersson wrote: > On Thu 21 Oct 05:40 CDT 2021, Odelu Kukatla wrote: > >> Add Epoch Subsystem (EPSS) L3 interconnect provider support on >> SC7280 SoCs. >> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Thanks! > @Georgi, do you intend to apply the two interconnect patches in this > series? Yes, applied! BR, Georgi > > Regards, > Bjorn > >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++- >> drivers/interconnect/qcom/sc7280.h | 2 ++ >> 2 files changed, 21 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c >> index c7af143..eec1309 100644 >> --- a/drivers/interconnect/qcom/osm-l3.c >> +++ b/drivers/interconnect/qcom/osm-l3.c >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: GPL-2.0 >> /* >> - * Copyright (c) 2020, The Linux Foundation. All rights reserved. >> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. >> */ >> >> #include <linux/bitfield.h> >> @@ -15,6 +15,7 @@ >> #include <dt-bindings/interconnect/qcom,osm-l3.h> >> >> #include "sc7180.h" >> +#include "sc7280.h" >> #include "sc8180x.h" >> #include "sdm845.h" >> #include "sm8150.h" >> @@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { >> .reg_perf_state = OSM_REG_PERF_STATE, >> }; >> >> +DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); >> +DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); >> + >> +static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { >> + [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, >> + [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, >> +}; >> + >> +static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { >> + .nodes = sc7280_epss_l3_nodes, >> + .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes), >> + .lut_row_size = EPSS_LUT_ROW_SIZE, >> + .reg_freq_lut = EPSS_REG_FREQ_LUT, >> + .reg_perf_state = EPSS_REG_PERF_STATE, >> +}; >> + >> DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); >> DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); >> >> @@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) >> >> static const struct of_device_id osm_l3_of_match[] = { >> { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, >> + { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 }, >> { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, >> { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, >> { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 }, >> diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h >> index 175e400..1fb9839 100644 >> --- a/drivers/interconnect/qcom/sc7280.h >> +++ b/drivers/interconnect/qcom/sc7280.h >> @@ -150,5 +150,7 @@ >> #define SC7280_SLAVE_PCIE_1 139 >> #define SC7280_SLAVE_QDSS_STM 140 >> #define SC7280_SLAVE_TCU 141 >> +#define SC7280_MASTER_EPSS_L3_APPS 142 >> +#define SC7280_SLAVE_EPSS_L3 143 >> >> #endif >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> a Linux Foundation Collaborative Project >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla 2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla 2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla @ 2021-10-21 10:40 ` Odelu Kukatla 2021-10-28 22:14 ` Stephen Boyd ` (3 more replies) 2 siblings, 4 replies; 14+ messages in thread From: Odelu Kukatla @ 2021-10-21 10:40 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder, linux-pm, linux-arm-msm-owner Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d74a4c8..0b55742 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3687,6 +3687,14 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla @ 2021-10-28 22:14 ` Stephen Boyd 2021-10-28 23:27 ` Bjorn Andersson ` (2 subsequent siblings) 3 siblings, 0 replies; 14+ messages in thread From: Stephen Boyd @ 2021-10-28 22:14 UTC (permalink / raw) To: Andy Gross, Odelu Kukatla, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel Cc: mdtipton, sibis, saravanak, okukatla, seansw, elder, linux-pm, linux-arm-msm-owner Quoting Odelu Kukatla (2021-10-21 03:40:57) > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 2021-10-28 22:14 ` Stephen Boyd @ 2021-10-28 23:27 ` Bjorn Andersson 2021-11-01 13:39 ` okukatla 2021-11-22 15:25 ` Georgi Djakov 2022-02-24 20:54 ` (subset) " Bjorn Andersson 3 siblings, 1 reply; 14+ messages in thread From: Bjorn Andersson @ 2021-10-28 23:27 UTC (permalink / raw) To: Odelu Kukatla Cc: georgi.djakov, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index d74a4c8..0b55742 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3687,6 +3687,14 @@ > }; > }; > > + epss_l3: interconnect@18590000 { > + compatible = "qcom,sc7280-epss-l3"; > + reg = <0 0x18590000 0 0x1000>; This series looks like I would expect, with and without per-core dcvs. But can you please explain why this contradict what Sibi says here: https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/ Regards, Bjorn > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #interconnect-cells = <1>; > + }; > + > cpufreq_hw: cpufreq@18591000 { > compatible = "qcom,cpufreq-epss"; > reg = <0 0x18591000 0 0x1000>, > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-28 23:27 ` Bjorn Andersson @ 2021-11-01 13:39 ` okukatla 0 siblings, 0 replies; 14+ messages in thread From: okukatla @ 2021-11-01 13:39 UTC (permalink / raw) To: Bjorn Andersson Cc: georgi.djakov, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel, sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner On 2021-10-29 04:57, Bjorn Andersson wrote: > On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote: > >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index d74a4c8..0b55742 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -3687,6 +3687,14 @@ >> }; >> }; >> >> + epss_l3: interconnect@18590000 { >> + compatible = "qcom,sc7280-epss-l3"; >> + reg = <0 0x18590000 0 0x1000>; > > This series looks like I would expect, with and without per-core dcvs. > But can you please explain why this contradict what Sibi says here: > https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/ > > Regards, > Bjorn > Thanks for Review! Sibi's patch will be dropped, it is not required with my updated patch series: https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/ >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + #interconnect-cells = <1>; >> + }; >> + >> cpufreq_hw: cpufreq@18591000 { >> compatible = "qcom,cpufreq-epss"; >> reg = <0 0x18591000 0 0x1000>, >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 2021-10-28 22:14 ` Stephen Boyd 2021-10-28 23:27 ` Bjorn Andersson @ 2021-11-22 15:25 ` Georgi Djakov 2022-02-24 20:54 ` (subset) " Bjorn Andersson 3 siblings, 0 replies; 14+ messages in thread From: Georgi Djakov @ 2021-11-22 15:25 UTC (permalink / raw) To: bjorn.andersson, Odelu Kukatla, georgi.djakov, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner On 21.10.21 13:40, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Acked-by: Georgi Djakov <djakov@kernel.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index d74a4c8..0b55742 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3687,6 +3687,14 @@ > }; > }; > > + epss_l3: interconnect@18590000 { > + compatible = "qcom,sc7280-epss-l3"; > + reg = <0 0x18590000 0 0x1000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #interconnect-cells = <1>; > + }; > + > cpufreq_hw: cpufreq@18591000 { > compatible = "qcom,cpufreq-epss"; > reg = <0 0x18591000 0 0x1000>, > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla ` (2 preceding siblings ...) 2021-11-22 15:25 ` Georgi Djakov @ 2022-02-24 20:54 ` Bjorn Andersson 3 siblings, 0 replies; 14+ messages in thread From: Bjorn Andersson @ 2022-02-24 20:54 UTC (permalink / raw) To: evgreen, Odelu Kukatla, linux-kernel, georgi.djakov, devicetree, Rob Herring, Andy Gross, linux-arm-msm Cc: linux-arm-msm-owner, elder, seansw, sibis, linux-pm, saravanak, sboyd, mdtipton On Thu, 21 Oct 2021 16:10:57 +0530, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Applied, thanks! [3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider commit: 8b93fbd95ed46bb0d57e63c65cef155a09a75bb9 Best regards, -- Bjorn Andersson <bjorn.andersson@linaro.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-02-24 20:54 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla 2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla 2021-10-27 16:59 ` Rob Herring 2021-10-28 22:13 ` Stephen Boyd 2021-10-21 10:40 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla 2021-10-28 22:13 ` Stephen Boyd 2021-11-18 20:53 ` Bjorn Andersson 2021-11-22 15:25 ` Georgi Djakov 2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 2021-10-28 22:14 ` Stephen Boyd 2021-10-28 23:27 ` Bjorn Andersson 2021-11-01 13:39 ` okukatla 2021-11-22 15:25 ` Georgi Djakov 2022-02-24 20:54 ` (subset) " Bjorn Andersson
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