From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-perf-users@vger.kernel.org
Subject: Re: [RFC V1 02/11] arm64/perf: Add register definitions for BRBE
Date: Tue, 25 Jan 2022 10:34:22 +0530 [thread overview]
Message-ID: <165b3f65-c92e-75e3-9485-548e1c862ec4@arm.com> (raw)
In-Reply-To: <877dap8c0o.wl-maz@kernel.org>
On 1/24/22 7:35 PM, Marc Zyngier wrote:
> On Mon, 24 Jan 2022 04:30:44 +0000,
> Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>>
>> This adds BRBE related register definitions and various other related field
>> macros there in. These will be used subsequently in a BRBE driver which is
>> being added later on.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 216 ++++++++++++++++++++++++++++++++
>> 1 file changed, 216 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 898bee0004ae..d8fd7e806a47 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -141,6 +141,218 @@
>> #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
>> #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
>>
>> +/*
>> + * BRBINF<N>_EL1 Encoding: [2, 1, 8, CRm, op2]
>> + *
>> + * derived as <CRm> = c{N<3:0>} <op2> = (N<4>x4 + 0)
>> + */
>> +#define SYS_BRBINF0_EL1 sys_reg(2, 1, 8, 0, 0)
>> +#define SYS_BRBINF1_EL1 sys_reg(2, 1, 8, 1, 0)
>> +#define SYS_BRBINF2_EL1 sys_reg(2, 1, 8, 2, 0)
>> +#define SYS_BRBINF3_EL1 sys_reg(2, 1, 8, 3, 0)
>> +#define SYS_BRBINF4_EL1 sys_reg(2, 1, 8, 4, 0)
>> +#define SYS_BRBINF5_EL1 sys_reg(2, 1, 8, 5, 0)
>> +#define SYS_BRBINF6_EL1 sys_reg(2, 1, 8, 6, 0)
>> +#define SYS_BRBINF7_EL1 sys_reg(2, 1, 8, 7, 0)
>> +#define SYS_BRBINF8_EL1 sys_reg(2, 1, 8, 8, 0)
>> +#define SYS_BRBINF9_EL1 sys_reg(2, 1, 8, 9, 0)
>
> [snip]
>
> Since the architecture gives you the formula to build these, why do
> you enumerate each and every register encoding? I'd rather see
> something like:
>
> #define __SYS_BRBINFO(n) sys_reg(2, 1, 8, ((n) & 0xf), (((n) & 0x10)) >> 2)
> #define SYS_BRBINF0_EL1 __SYS_BRBINFO(0)
> [...]
>
> and something similar for all the new registers that come in packs of
> 32... We already have similar things for AMU, PMU, GIC and co.
Sure, above method seems like a better idea indeed. I will create these
constructs for BRBINF, BRBSRC and BRBTGT based registers set.
>
> Thanks,
>
> M.
>
>
next prev parent reply other threads:[~2022-01-25 5:21 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 4:30 [RFC V1 00/11] arm64/perf: Enable branch stack sampling Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 01/11] perf: Consolidate branch sample filter helpers Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 02/11] arm64/perf: Add register definitions for BRBE Anshuman Khandual
2022-01-24 14:05 ` Marc Zyngier
2022-01-25 5:04 ` Anshuman Khandual [this message]
2022-01-24 4:30 ` [RFC V1 03/11] arm64/perf: Update struct arm_pmu " Anshuman Khandual
2022-01-26 16:59 ` Rob Herring
2022-01-28 3:38 ` Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 04/11] arm64/perf: Update struct pmu_hw_events " Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 05/11] arm64/perf: Detect support " Anshuman Khandual
2022-01-26 17:18 ` Rob Herring
2022-01-28 3:27 ` Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 06/11] arm64/perf: Drive BRBE from perf event states Anshuman Khandual
2022-01-26 17:07 ` Rob Herring
2022-01-27 12:20 ` Anshuman Khandual
2022-01-27 14:31 ` Rob Herring
2022-01-24 4:30 ` [RFC V1 07/11] arm64/perf: Add BRBE driver Anshuman Khandual
2022-01-24 18:11 ` James Clark
2022-01-24 18:15 ` James Clark
2022-01-24 4:30 ` [RFC V1 08/11] arm64/perf: Enable branch stack sampling Anshuman Khandual
2022-01-24 18:02 ` James Clark
2022-01-24 4:30 ` [RFC V1 09/11] perf: Add more generic branch types Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 10/11] perf: Expand perf_branch_entry.type Anshuman Khandual
2022-01-25 16:58 ` James Clark
2022-01-28 4:14 ` Anshuman Khandual
2022-01-26 16:47 ` Rob Herring
2022-01-27 10:41 ` Anshuman Khandual
2022-01-24 4:30 ` [RFC V1 11/11] perf: Capture branch privilege information Anshuman Khandual
2022-01-25 15:39 ` James Clark
2022-02-02 11:11 ` Anshuman Khandual
2022-01-26 17:27 ` James Clark
2022-03-14 6:47 ` Anshuman Khandual
2022-01-25 16:25 ` [PATCH 0/1] perf test: Add branch stack sampling tests for ARM64 German Gomez
2022-01-25 16:25 ` [PATCH 1/1] " German Gomez
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=165b3f65-c92e-75e3-9485-548e1c862ec4@arm.com \
--to=anshuman.khandual@arm.com \
--cc=acme@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=mingo@redhat.com \
--cc=peterz@infradead.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).