From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Krzysztof Halasa <khc@pm.waw.pl>
Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
linux-ide@vger.kernel.org, lkml <linux-kernel@vger.kernel.org>
Subject: Re: SATA_SIL on IXP425 workaround
Date: Thu, 14 Jan 2010 21:05:15 +0000 [thread overview]
Message-ID: <20100114210515.7a477a43@lxorguk.ukuu.org.uk> (raw)
In-Reply-To: <m3my0gh2dc.fsf@intrepid.localdomain>
> We need to use the MMIO BAR at least for starting DMA transfers, the
> I/O ones are 64KB-limited. We can't just use read[bw] if reading all
> 32 bits has side effects.
Last time I instrumented this on x86 we never issued a > 64K linear block
in our s/g lists. In fact we went for years before anyone noticed we had
a bug with CS5530 and a couple of other chips that mishandled 64K segment
sizes, and that was only finally noticed in a very specific and weird
circumstance.
> Most of the time there are no problems with MMIO on IXP4xx as modern
> devices usually use 32-bit registers anyway, or at least they have no
> problem with read[bw] always driving all four PCI byte enable lines
> (write[bw] doesn't have this issue).
Fair enough
next prev parent reply other threads:[~2010-01-14 21:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-09 17:31 SATA_SIL on IXP425 workaround Krzysztof Halasa
2010-01-14 15:59 ` Bartlomiej Zolnierkiewicz
2010-01-14 18:08 ` Krzysztof Halasa
2010-01-14 19:22 ` Alan Cox
2010-01-14 20:12 ` Krzysztof Halasa
2010-01-14 21:05 ` Alan Cox [this message]
2010-01-16 5:03 ` Robert Hancock
2010-01-14 20:29 ` Bartlomiej Zolnierkiewicz
2010-01-14 21:00 ` Alan Cox
2010-01-21 5:00 ` Jeff Garzik
2010-01-21 4:58 ` Jeff Garzik
2010-01-21 6:48 ` Jeff Garzik
2010-01-21 18:37 ` Jeff Garzik
2010-01-21 21:47 ` Krzysztof Halasa
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