From: Krzysztof Halasa <khc@pm.waw.pl>
To: Jeff Garzik <jeff@garzik.org>
Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
linux-ide@vger.kernel.org, lkml <linux-kernel@vger.kernel.org>
Subject: Re: SATA_SIL on IXP425 workaround
Date: Thu, 21 Jan 2010 22:47:20 +0100 [thread overview]
Message-ID: <m3sk9zceqf.fsf@intrepid.localdomain> (raw)
In-Reply-To: <4B589EFC.6050002@garzik.org> (Jeff Garzik's message of "Thu, 21 Jan 2010 13:37:48 -0500")
Jeff Garzik <jeff@garzik.org> writes:
> It is definitely possible to do all 32-bit accesses... but that
> requires activating and exclusively using the command buffering
> feature, because direct 32-bit access to the taskfile registers will
> result in a 32-bit access to Data rather than the desired effect.
Command buffering? The DS for SIL3512 lists IDEx taskfile registers
for command buffering, but I can't see any explanation there.
BTW I don't know requirements of other platforms, but IXP4xx has only
problems with 8- and 16-bit PCI memory reads. Other ops including
all memory writes, and all "port" I/O are ok.
Unfortunately I can't test any patch ATM, -ENOHW. I might be able to get
access to this hw again, but I don't know at this point.
--
Krzysztof Halasa
prev parent reply other threads:[~2010-01-21 21:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-09 17:31 SATA_SIL on IXP425 workaround Krzysztof Halasa
2010-01-14 15:59 ` Bartlomiej Zolnierkiewicz
2010-01-14 18:08 ` Krzysztof Halasa
2010-01-14 19:22 ` Alan Cox
2010-01-14 20:12 ` Krzysztof Halasa
2010-01-14 21:05 ` Alan Cox
2010-01-16 5:03 ` Robert Hancock
2010-01-14 20:29 ` Bartlomiej Zolnierkiewicz
2010-01-14 21:00 ` Alan Cox
2010-01-21 5:00 ` Jeff Garzik
2010-01-21 4:58 ` Jeff Garzik
2010-01-21 6:48 ` Jeff Garzik
2010-01-21 18:37 ` Jeff Garzik
2010-01-21 21:47 ` Krzysztof Halasa [this message]
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