[patch 0/2] clk: spear3xx: Make it actually work

[patch 0/2] clk: spear3xx: Make it actually work

[Thomas Gleixner]

This code is broken since commit 5df33a62c (SPEAr: Switch to common
clock framework). Sigh...

The first patch fixes that issue and the second one makes the uarts1/2
usable. 

Quality stuff that.

Thanks,

	tglx

[patch 1/2] clk: spear3xx: Use proper control register offset

[Thomas Gleixner]

[-- Attachment #1: spear-clk-fix-crap.patch --]
[-- Type: text/plain, Size: 877 bytes --]

The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
---
 drivers/clk/spear/spear3xx_clock.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: linux/drivers/clk/spear/spear3xx_clock.c
===================================================================
--- linux.orig/drivers/clk/spear/spear3xx_clock.c
+++ linux/drivers/clk/spear/spear3xx_clock.c
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 
-#define SPEAR320_CONTROL_REG		(soc_config_base + 0x0000)
+#define SPEAR320_CONTROL_REG		(soc_config_base + 0x0010)
 #define SPEAR320_EXT_CTRL_REG		(soc_config_base + 0x0018)
 
 	#define SPEAR320_UARTX_PCLK_MASK		0x1

[patch 2/2] clk: spear3xx: Set proper clock parent of uart1/2

[Thomas Gleixner]

[-- Attachment #1: spear-clk-force-ras-apb-for-uart12.patch --]
[-- Type: text/plain, Size: 2803 bytes --]

The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.

Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 drivers/clk/spear/spear3xx_clock.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

Index: linux/drivers/clk/spear/spear3xx_clock.c
===================================================================
--- linux.orig/drivers/clk/spear/spear3xx_clock.c
+++ linux/drivers/clk/spear/spear3xx_clock.c
@@ -245,7 +245,8 @@ static const char *smii0_parents[] = { "
 	"ras_syn0_gclk", };
 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
 
-static void __init spear320_clk_init(void __iomem *soc_config_base)
+static void __init spear320_clk_init(void __iomem *soc_config_base,
+				     struct clk *ras_apb_clk)
 {
 	struct clk *clk;
 
@@ -342,6 +343,8 @@ static void __init spear320_clk_init(voi
 			SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "a3000000.serial");
+	/* Enforce ras_apb_clk */
+	clk_set_parent(clk, ras_apb_clk);
 
 	clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
 			ARRAY_SIZE(uartx_parents),
@@ -349,6 +352,8 @@ static void __init spear320_clk_init(voi
 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 	clk_register_clkdev(clk, NULL, "a4000000.serial");
+	/* Enforce ras_apb_clk */
+	clk_set_parent(clk, ras_apb_clk);
 
 	clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
 			ARRAY_SIZE(uartx_parents),
@@ -379,12 +384,12 @@ static void __init spear320_clk_init(voi
 	clk_register_clkdev(clk, NULL, "60100000.serial");
 }
 #else
-static inline void spear320_clk_init(void __iomem *soc_config_base) { }
+static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
 #endif
 
 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
 {
-	struct clk *clk, *clk1;
+	struct clk *clk, *clk1, *ras_apb_clk;
 
 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 			32000);
@@ -613,6 +618,7 @@ void __init spear3xx_clk_init(void __iom
 	clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
 			RAS_APB_CLK_ENB, 0, &_lock);
 	clk_register_clkdev(clk, "ras_apb_clk", NULL);
+	ras_apb_clk = clk;
 
 	clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
 			RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
@@ -659,5 +665,5 @@ void __init spear3xx_clk_init(void __iom
 	else if (of_machine_is_compatible("st,spear310"))
 		spear310_clk_init();
 	else if (of_machine_is_compatible("st,spear320"))
-		spear320_clk_init(soc_config_base);
+		spear320_clk_init(soc_config_base, ras_apb_clk);
 }

Re: [patch 1/2] clk: spear3xx: Use proper control register offset

[Viresh Kumar]

On Fri, Jun 20, 2014 at 3:22 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> The control register is at offset 0x10, not 0x0. This is wreckaged
> since commit 5df33a62c (SPEAr: Switch to common clock framework).
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: stable@vger.kernel.org
> ---
>  drivers/clk/spear/spear3xx_clock.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Index: linux/drivers/clk/spear/spear3xx_clock.c
> ===================================================================
> --- linux.orig/drivers/clk/spear/spear3xx_clock.c
> +++ linux/drivers/clk/spear/spear3xx_clock.c
> @@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi
>  /* array of all spear 320 clock lookups */
>  #ifdef CONFIG_MACH_SPEAR320
>
> -#define SPEAR320_CONTROL_REG           (soc_config_base + 0x0000)
> +#define SPEAR320_CONTROL_REG           (soc_config_base + 0x0010)
>  #define SPEAR320_EXT_CTRL_REG          (soc_config_base + 0x0018)
>
>         #define SPEAR320_UARTX_PCLK_MASK                0x1

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Re: [patch 2/2] clk: spear3xx: Set proper clock parent of uart1/2

[Viresh Kumar]

On Fri, Jun 20, 2014 at 3:22 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> The uarts only work when the parent is ras_ahb_clk. The stale 3.5
> based ST tree does this in the board file.
>
> Add it to the clk init function. Not pretty, but the mess there is
> amazing anyway.

I still feel that board file is the right place to do it. Similar stuff might be
required for some other peripheral clocks later and this solution
wouldn't be scalable then.

But if you insist on doing it this way:

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Re: [patch 2/2] clk: spear3xx: Set proper clock parent of uart1/2

[Thomas Gleixner]

On Fri, 20 Jun 2014, Viresh Kumar wrote:

> On Fri, Jun 20, 2014 at 3:22 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> > The uarts only work when the parent is ras_ahb_clk. The stale 3.5
> > based ST tree does this in the board file.
> >
> > Add it to the clk init function. Not pretty, but the mess there is
> > amazing anyway.
> 
> I still feel that board file is the right place to do it. Similar stuff might be
> required for some other peripheral clocks later and this solution
> wouldn't be scalable then.
> 
> But if you insist on doing it this way:

I really do not care much as long as it works.
 
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> 

Re: [patch 0/2] clk: spear3xx: Make it actually work

[Mike Turquette]

Quoting Thomas Gleixner (2014-06-19 14:52:23)
> This code is broken since commit 5df33a62c (SPEAr: Switch to common
> clock framework). Sigh...
> 
> The first patch fixes that issue and the second one makes the uarts1/2
> usable. 

Applied to clk-fixes.

Regards,
Mike

> 
> Quality stuff that.
> 
> Thanks,
> 
>         tglx
> 
> 
> 
>