* [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states
@ 2016-05-03 8:24 Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header Shreyas B. Prabhu
` (8 more replies)
0 siblings, 9 replies; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe
Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu,
Rafael J. Wysocki, Daniel Lezcano, linux-pm
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
PSSCR has following key fields
Bits 0:3 - Power-Saving Level Status. This field indicates the
lowest power-saving state the thread entered since stop
instruction was last executed.
Bit 42 - Enable State Loss
0 - No state is lost irrespective of other fields
1 - Allows state loss
Bits 44:47 - Power-Saving Level Limit
This limits the power-saving level that can be entered into.
Bits 60:63 - Requested Level
Used to specify which power-saving level must be entered on
executing stop instruction
Stop idle states and their properties like name, latency, target
residency, psscr value are exposed via device tree.
This patch series adds support for this new mechanism.
Patches 1-6 are cleanups and code movement.
Patch 7 adds platform specific support for stop and psscr handling.
Patch 8 adds cpuidle driver support.
Patch 9 makes offlined cpu use stop state.
Changes in v2
=============
- Rebased on v4.6-rc6
- Using CPU_FTR_ARCH_300 bit instead of CPU_FTR_STOP_INST
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-pm@vger.kernel.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Michael Neuling <mikey@neuling.org>
Cc: linuxppc-dev@lists.ozlabs.org
Shreyas B. Prabhu (9):
powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header
powerpc/kvm: make hypervisor state restore a function
powerpc/powernv: Move idle code usable by multiple hardware to common
location
powerpc/powernv: Make power7_powersave_common more generic
powerpc/powernv: Move idle related macros to cpuidle.h
powerpc/powernv: set power_save func after the idle states are
initialized
powerpc/powernv: Add platform support for stop instruction
cpuidle/powernv: Add support for POWER ISA v3 idle states
powerpc/powernv: Use deepest stop state when cpu is offlined
arch/powerpc/include/asm/cpuidle.h | 29 ++++
arch/powerpc/include/asm/exception-64s.h | 18 +++
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerpc/include/asm/machdep.h | 1 +
arch/powerpc/include/asm/opal-api.h | 11 +-
arch/powerpc/include/asm/paca.h | 4 +
arch/powerpc/include/asm/ppc-opcode.h | 4 +
arch/powerpc/include/asm/processor.h | 1 +
arch/powerpc/include/asm/reg.h | 11 ++
arch/powerpc/kernel/Makefile | 2 +
arch/powerpc/kernel/asm-offsets.c | 4 +
arch/powerpc/kernel/exceptions-64s.S | 29 +---
arch/powerpc/kernel/idle_power7.S | 212 +++-------------------------
arch/powerpc/kernel/idle_power_common.S | 185 +++++++++++++++++++++++++
arch/powerpc/kernel/idle_power_stop.S | 221 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/Kconfig | 4 +
arch/powerpc/platforms/powernv/Kconfig | 1 +
arch/powerpc/platforms/powernv/idle.c | 94 +++++++++++--
arch/powerpc/platforms/powernv/powernv.h | 1 +
arch/powerpc/platforms/powernv/setup.c | 2 +-
arch/powerpc/platforms/powernv/smp.c | 4 +-
drivers/cpuidle/cpuidle-powernv.c | 57 +++++++-
22 files changed, 659 insertions(+), 238 deletions(-)
create mode 100644 arch/powerpc/kernel/idle_power_common.S
create mode 100644 arch/powerpc/kernel/idle_power_stop.S
--
2.4.11
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 4:35 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function Shreyas B. Prabhu
` (7 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move
the macro to a common location (exception-64s.h)
This patch does not change any functionality.
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/exception-64s.h | 18 ++++++++++++++++++
arch/powerpc/kernel/idle_power7.S | 20 +-------------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 93ae809..6a625af 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -545,4 +545,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#define FINISH_NAP
#endif
+#define CHECK_HMI_INTERRUPT \
+ mfspr r0,SPRN_SRR1; \
+BEGIN_FTR_SECTION_NESTED(66); \
+ rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
+FTR_SECTION_ELSE_NESTED(66); \
+ rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
+ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
+ cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
+ bne 20f; \
+ /* Invoke opal call to handle hmi */ \
+ ld r2,PACATOC(r13); \
+ ld r1,PACAR1(r13); \
+ std r3,ORIG_GPR3(r1); /* Save original r3 */ \
+ li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
+ bl opal_call_realmode; \
+ ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
+20: nop;
+
#endif /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 470ceeb..6b3404b 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -19,6 +19,7 @@
#include <asm/kvm_book3s_asm.h>
#include <asm/opal.h>
#include <asm/cpuidle.h>
+#include <asm/exception-64s.h>
#include <asm/book3s/64/mmu-hash.h>
#undef DEBUG
@@ -257,25 +258,6 @@ _GLOBAL(power7_winkle)
b power7_powersave_common
/* No return */
-#define CHECK_HMI_INTERRUPT \
- mfspr r0,SPRN_SRR1; \
-BEGIN_FTR_SECTION_NESTED(66); \
- rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
-FTR_SECTION_ELSE_NESTED(66); \
- rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
-ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
- cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
- bne 20f; \
- /* Invoke opal call to handle hmi */ \
- ld r2,PACATOC(r13); \
- ld r1,PACAR1(r13); \
- std r3,ORIG_GPR3(r1); /* Save original r3 */ \
- li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
- bl opal_call_realmode; \
- ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
-20: nop;
-
-
_GLOBAL(power7_wakeup_tb_loss)
ld r2,PACATOC(r13);
ld r1,PACAR1(r13)
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 6:25 ` Gautham R Shenoy
2016-05-20 1:45 ` Paul Mackerras
2016-05-03 8:24 ` [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location Shreyas B. Prabhu
` (6 subsequent siblings)
8 siblings, 2 replies; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.
At a higher level this is what the change looks like-
Before this patch -
power7_wakeup_tb_loss:
restore hypervisor state
if (thread needed by kvm)
goto kvm_start_guest
restore nvgprs, cr, pc
rfid to process context
power7_wakeup_loss:
restore nvgprs, cr, pc
rfid to process context
reset vector:
if (waking from deep idle states)
goto power7_wakeup_tb_loss
else
if (thread needed by kvm)
goto kvm_start_guest
goto power7_wakeup_loss
After this patch -
power7_wakeup_tb_loss:
restore hypervisor state
return
power7_restore_hyp_resource():
if (waking from deep idle states)
goto power7_wakeup_tb_loss
return
power7_wakeup_loss:
restore nvgprs, cr, pc
rfid to process context
reset vector:
power7_restore_hyp_resource()
if (thread needed by kvm)
goto kvm_start_guest
goto power7_wakeup_loss
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/kernel/exceptions-64s.S | 29 +++-------------
arch/powerpc/kernel/idle_power7.S | 67 ++++++++++++++++++++----------------
2 files changed, 41 insertions(+), 55 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 7716ceb..7ebfbb0 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -107,25 +107,8 @@ BEGIN_FTR_SECTION
beq 9f
cmpwi cr3,r13,2
+ bl power7_restore_hyp_resource
- /*
- * Check if last bit of HSPGR0 is set. This indicates whether we are
- * waking up from winkle.
- */
- GET_PACA(r13)
- clrldi r5,r13,63
- clrrdi r13,r13,1
- cmpwi cr4,r5,1
- mtspr SPRN_HSPRG0,r13
-
- lbz r0,PACA_THREAD_IDLE_STATE(r13)
- cmpwi cr2,r0,PNV_THREAD_NAP
- bgt cr2,8f /* Either sleep or Winkle */
-
- /* Waking up from nap should not cause hypervisor state loss */
- bgt cr3,.
-
- /* Waking up from nap */
li r0,PNV_THREAD_RUNNING
stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
@@ -143,13 +126,9 @@ BEGIN_FTR_SECTION
/* Return SRR1 from power7_nap() */
mfspr r3,SPRN_SRR1
- beq cr3,2f
- b power7_wakeup_noloss
-2: b power7_wakeup_loss
-
- /* Fast Sleep wakeup on PowerNV */
-8: GET_PACA(r13)
- b power7_wakeup_tb_loss
+ blt cr3,2f
+ b power7_wakeup_loss
+2: b power7_wakeup_noloss
9:
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 6b3404b..82d164b 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -258,6 +258,35 @@ _GLOBAL(power7_winkle)
b power7_powersave_common
/* No return */
+/*
+ * Called from reset vector. Check whether we have woken up with
+ * hypervisor state loss. If yes, restore hypervisor state and return
+ * back to reset vector.
+ */
+_GLOBAL(power7_restore_hyp_resource)
+ /*
+ * Check if last bit of HSPGR0 is set. This indicates whether we are
+ * waking up from winkle.
+ */
+ GET_PACA(r13)
+ clrldi r5,r13,63
+ clrrdi r13,r13,1
+ cmpwi cr4,r5,1
+ mtspr SPRN_HSPRG0,r13
+
+ lbz r0,PACA_THREAD_IDLE_STATE(r13)
+ cmpwi cr2,r0,PNV_THREAD_NAP
+ bgt cr2,power7_wakeup_tb_loss /* Either sleep or Winkle */
+
+ /*
+ * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
+ * up from nap. At this stage CR3 shouldn't contains 'gt' since that
+ * indicates we are waking with hypervisor state loss from nap.
+ */
+ bgt cr3,.
+
+ blr
+
_GLOBAL(power7_wakeup_tb_loss)
ld r2,PACATOC(r13);
ld r1,PACAR1(r13)
@@ -266,11 +295,13 @@ _GLOBAL(power7_wakeup_tb_loss)
* and they are restored before switching to the process context. Hence
* until they are restored, they are free to be used.
*
- * Save SRR1 in a NVGPR as it might be clobbered in opal_call_realmode
- * (called in CHECK_HMI_INTERRUPT). SRR1 is required to determine the
- * wakeup reason if we branch to kvm_start_guest.
+ * Save SRR1 and LR in NVGPRs as they might be clobbered in
+ * opal_call_realmode (called in CHECK_HMI_INTERRUPT). SRR1 is required
+ * to determine the wakeup reason if we branch to kvm_start_guest. LR
+ * is required to return back to reset vector after hypervisor state
+ * restore is complete.
*/
-
+ mflr r17
mfspr r16,SPRN_SRR1
BEGIN_FTR_SECTION
CHECK_HMI_INTERRUPT
@@ -420,33 +451,9 @@ common_exit:
hypervisor_state_restored:
- li r5,PNV_THREAD_RUNNING
- stb r5,PACA_THREAD_IDLE_STATE(r13)
-
mtspr SPRN_SRR1,r16
-#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
- li r0,KVM_HWTHREAD_IN_KERNEL
- stb r0,HSTATE_HWTHREAD_STATE(r13)
- /* Order setting hwthread_state vs. testing hwthread_req */
- sync
- lbz r0,HSTATE_HWTHREAD_REQ(r13)
- cmpwi r0,0
- beq 6f
- b kvm_start_guest
-6:
-#endif
-
- REST_NVGPRS(r1)
- REST_GPR(2, r1)
- ld r3,_CCR(r1)
- ld r4,_MSR(r1)
- ld r5,_NIP(r1)
- addi r1,r1,INT_FRAME_SIZE
- mtcr r3
- mfspr r3,SPRN_SRR1 /* Return SRR1 */
- mtspr SPRN_SRR1,r4
- mtspr SPRN_SRR0,r5
- rfid
+ mtlr r17
+ blr
fastsleep_workaround_at_exit:
li r3,1
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 6:29 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic Shreyas B. Prabhu
` (5 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
CPU-idle related code like context save/restore functions idle_power7.S
can reused for adding stop instruction support. Move this
code to a new commonly accessible location.
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/idle_power7.S | 144 ----------------------------
arch/powerpc/kernel/idle_power_common.S | 160 ++++++++++++++++++++++++++++++++
3 files changed, 161 insertions(+), 144 deletions(-)
create mode 100644 arch/powerpc/kernel/idle_power_common.S
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 2da380f..b877b84 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o
+obj-$(CONFIG_PPC_POWERNV) += idle_power_common.o
procfs-y := proc_powerpc.o
obj-$(CONFIG_PROC_FS) += $(procfs-y)
rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 82d164b..594e1c5 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -68,80 +68,6 @@ core_idle_lock_held:
lwarx r15,0,r14
blr
-/*
- * Pass requested state in r3:
- * r3 - PNV_THREAD_NAP/SLEEP/WINKLE
- *
- * To check IRQ_HAPPENED in r4
- * 0 - don't check
- * 1 - check
- */
-_GLOBAL(power7_powersave_common)
- /* Use r3 to pass state nap/sleep/winkle */
- /* NAP is a state loss, we create a regs frame on the
- * stack, fill it up with the state we care about and
- * stick a pointer to it in PACAR1. We really only
- * need to save PC, some CR bits and the NV GPRs,
- * but for now an interrupt frame will do.
- */
- mflr r0
- std r0,16(r1)
- stdu r1,-INT_FRAME_SIZE(r1)
- std r0,_LINK(r1)
- std r0,_NIP(r1)
-
- /* Hard disable interrupts */
- mfmsr r9
- rldicl r9,r9,48,1
- rotldi r9,r9,16
- mtmsrd r9,1 /* hard-disable interrupts */
-
- /* Check if something happened while soft-disabled */
- lbz r0,PACAIRQHAPPENED(r13)
- andi. r0,r0,~PACA_IRQ_HARD_DIS@l
- beq 1f
- cmpwi cr0,r4,0
- beq 1f
- addi r1,r1,INT_FRAME_SIZE
- ld r0,16(r1)
- li r3,0 /* Return 0 (no nap) */
- mtlr r0
- blr
-
-1: /* We mark irqs hard disabled as this is the state we'll
- * be in when returning and we need to tell arch_local_irq_restore()
- * about it
- */
- li r0,PACA_IRQ_HARD_DIS
- stb r0,PACAIRQHAPPENED(r13)
-
- /* We haven't lost state ... yet */
- li r0,0
- stb r0,PACA_NAPSTATELOST(r13)
-
- /* Continue saving state */
- SAVE_GPR(2, r1)
- SAVE_NVGPRS(r1)
- mfcr r4
- std r4,_CCR(r1)
- std r9,_MSR(r1)
- std r1,PACAR1(r13)
-
- /*
- * Go to real mode to do the nap, as required by the architecture.
- * Also, we need to be in real mode before setting hwthread_state,
- * because as soon as we do that, another thread can switch
- * the MMU context to the guest.
- */
- LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
- li r6, MSR_RI
- andc r6, r9, r6
- LOAD_REG_ADDR(r7, power7_enter_nap_mode)
- mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
- mtspr SPRN_SRR0, r7
- mtspr SPRN_SRR1, r5
- rfid
-
.globl power7_enter_nap_mode
power7_enter_nap_mode:
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -258,35 +184,6 @@ _GLOBAL(power7_winkle)
b power7_powersave_common
/* No return */
-/*
- * Called from reset vector. Check whether we have woken up with
- * hypervisor state loss. If yes, restore hypervisor state and return
- * back to reset vector.
- */
-_GLOBAL(power7_restore_hyp_resource)
- /*
- * Check if last bit of HSPGR0 is set. This indicates whether we are
- * waking up from winkle.
- */
- GET_PACA(r13)
- clrldi r5,r13,63
- clrrdi r13,r13,1
- cmpwi cr4,r5,1
- mtspr SPRN_HSPRG0,r13
-
- lbz r0,PACA_THREAD_IDLE_STATE(r13)
- cmpwi cr2,r0,PNV_THREAD_NAP
- bgt cr2,power7_wakeup_tb_loss /* Either sleep or Winkle */
-
- /*
- * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
- * up from nap. At this stage CR3 shouldn't contains 'gt' since that
- * indicates we are waking with hypervisor state loss from nap.
- */
- bgt cr3,.
-
- blr
-
_GLOBAL(power7_wakeup_tb_loss)
ld r2,PACATOC(r13);
ld r1,PACAR1(r13)
@@ -461,44 +358,3 @@ fastsleep_workaround_at_exit:
li r0,OPAL_CONFIG_CPU_IDLE_STATE
bl opal_call_realmode
b timebase_resync
-
-/*
- * R3 here contains the value that will be returned to the caller
- * of power7_nap.
- */
-_GLOBAL(power7_wakeup_loss)
- ld r1,PACAR1(r13)
-BEGIN_FTR_SECTION
- CHECK_HMI_INTERRUPT
-END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
- REST_NVGPRS(r1)
- REST_GPR(2, r1)
- ld r6,_CCR(r1)
- ld r4,_MSR(r1)
- ld r5,_NIP(r1)
- addi r1,r1,INT_FRAME_SIZE
- mtcr r6
- mtspr SPRN_SRR1,r4
- mtspr SPRN_SRR0,r5
- rfid
-
-/*
- * R3 here contains the value that will be returned to the caller
- * of power7_nap.
- */
-_GLOBAL(power7_wakeup_noloss)
- lbz r0,PACA_NAPSTATELOST(r13)
- cmpwi r0,0
- bne power7_wakeup_loss
-BEGIN_FTR_SECTION
- CHECK_HMI_INTERRUPT
-END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
- ld r1,PACAR1(r13)
- ld r6,_CCR(r1)
- ld r4,_MSR(r1)
- ld r5,_NIP(r1)
- addi r1,r1,INT_FRAME_SIZE
- mtcr r6
- mtspr SPRN_SRR1,r4
- mtspr SPRN_SRR0,r5
- rfid
diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
new file mode 100644
index 0000000..05954ae
--- /dev/null
+++ b/arch/powerpc/kernel/idle_power_common.S
@@ -0,0 +1,160 @@
+#include <asm/cputable.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/ppc-opcode.h>
+#include <asm/hw_irq.h>
+#include <asm/kvm_book3s_asm.h>
+#include <asm/opal.h>
+#include <asm/cpuidle.h>
+#include <asm/exception-64s.h>
+#include <asm/book3s/64/mmu-hash.h>
+
+#undef DEBUG
+
+ .text
+
+/*
+ * Pass requested state in r3:
+ * r3 - PNV_THREAD_NAP/SLEEP/WINKLE
+ *
+ * To check IRQ_HAPPENED in r4
+ * 0 - don't check
+ * 1 - check
+ */
+_GLOBAL(power7_powersave_common)
+ /* Use r3 to pass state nap/sleep/winkle */
+ /* NAP is a state loss, we create a regs frame on the
+ * stack, fill it up with the state we care about and
+ * stick a pointer to it in PACAR1. We really only
+ * need to save PC, some CR bits and the NV GPRs,
+ * but for now an interrupt frame will do.
+ */
+ mflr r0
+ std r0,16(r1)
+ stdu r1,-INT_FRAME_SIZE(r1)
+ std r0,_LINK(r1)
+ std r0,_NIP(r1)
+
+ /* Hard disable interrupts */
+ mfmsr r9
+ rldicl r9,r9,48,1
+ rotldi r9,r9,16
+ mtmsrd r9,1 /* hard-disable interrupts */
+
+ /* Check if something happened while soft-disabled */
+ lbz r0,PACAIRQHAPPENED(r13)
+ andi. r0,r0,~PACA_IRQ_HARD_DIS@l
+ beq 1f
+ cmpwi cr0,r4,0
+ beq 1f
+ addi r1,r1,INT_FRAME_SIZE
+ ld r0,16(r1)
+ li r3,0 /* Return 0 (no nap) */
+ mtlr r0
+ blr
+
+1: /* We mark irqs hard disabled as this is the state we'll
+ * be in when returning and we need to tell arch_local_irq_restore()
+ * about it
+ */
+ li r0,PACA_IRQ_HARD_DIS
+ stb r0,PACAIRQHAPPENED(r13)
+
+ /* We haven't lost state ... yet */
+ li r0,0
+ stb r0,PACA_NAPSTATELOST(r13)
+
+ /* Continue saving state */
+ SAVE_GPR(2, r1)
+ SAVE_NVGPRS(r1)
+ mfcr r4
+ std r4,_CCR(r1)
+ std r9,_MSR(r1)
+ std r1,PACAR1(r13)
+
+ /*
+ * Go to real mode to do the nap, as required by the architecture.
+ * Also, we need to be in real mode before setting hwthread_state,
+ * because as soon as we do that, another thread can switch
+ * the MMU context to the guest.
+ */
+ LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
+ li r6, MSR_RI
+ andc r6, r9, r6
+ LOAD_REG_ADDR(r7, power7_enter_nap_mode)
+ mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
+ mtspr SPRN_SRR0, r7
+ mtspr SPRN_SRR1, r5
+ rfid
+ /* No return */
+
+/*
+ * Called from reset vector. Check whether we have woken up with
+ * hypervisor state loss. If yes, restore hypervisor state and return
+ * back to reset vector.
+ */
+_GLOBAL(power7_restore_hyp_resource)
+ /*
+ * Check if last bit of HSPGR0 is set. This indicates whether we are
+ * waking up from winkle.
+ */
+ GET_PACA(r13)
+ clrldi r5,r13,63
+ clrrdi r13,r13,1
+ cmpwi cr4,r5,1
+ mtspr SPRN_HSPRG0,r13
+
+ lbz r0,PACA_THREAD_IDLE_STATE(r13)
+ cmpwi cr2,r0,PNV_THREAD_NAP
+ bgt cr2,power7_wakeup_tb_loss /* Either sleep or Winkle */
+
+ /*
+ * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
+ * up from nap. At this stage CR3 shouldn't contains 'gt' since that
+ * indicates we are waking with hypervisor state loss from nap.
+ */
+ bgt cr3,.
+
+ blr
+
+/*
+ * R3 here contains the value that will be returned to the caller
+ * of power7_nap.
+ */
+_GLOBAL(power7_wakeup_loss)
+ ld r1,PACAR1(r13)
+BEGIN_FTR_SECTION
+ CHECK_HMI_INTERRUPT
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+ REST_NVGPRS(r1)
+ REST_GPR(2, r1)
+ ld r6,_CCR(r1)
+ ld r4,_MSR(r1)
+ ld r5,_NIP(r1)
+ addi r1,r1,INT_FRAME_SIZE
+ mtcr r6
+ mtspr SPRN_SRR1,r4
+ mtspr SPRN_SRR0,r5
+ rfid
+
+/*
+ * R3 here contains the value that will be returned to the caller
+ * of power7_nap.
+ */
+_GLOBAL(power7_wakeup_noloss)
+ lbz r0,PACA_NAPSTATELOST(r13)
+ cmpwi r0,0
+ bne power7_wakeup_loss
+BEGIN_FTR_SECTION
+ CHECK_HMI_INTERRUPT
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+ ld r1,PACAR1(r13)
+ ld r6,_CCR(r1)
+ ld r4,_MSR(r1)
+ ld r5,_NIP(r1)
+ addi r1,r1,INT_FRAME_SIZE
+ mtcr r6
+ mtspr SPRN_SRR1,r4
+ mtspr SPRN_SRR0,r5
+ rfid
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (2 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 6:37 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h Shreyas B. Prabhu
` (4 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
power7_powersave_common does common steps needed before entering idle
state and eventually changes MSR to MSR_IDLE and does rfid to
power7_enter_nap_mode.
Make it more generic by passing the rfid address as a function parameter.
Also make function name more generic.
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/kernel/idle_power7.S | 11 +++++++----
arch/powerpc/kernel/idle_power_common.S | 11 ++++++-----
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 594e1c5..1ea71d4 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -169,19 +169,22 @@ _GLOBAL(power7_idle)
_GLOBAL(power7_nap)
mr r4,r3
li r3,PNV_THREAD_NAP
- b power7_powersave_common
+ LOAD_REG_ADDR(r5, power7_enter_nap_mode)
+ b power_powersave_common
/* No return */
_GLOBAL(power7_sleep)
li r3,PNV_THREAD_SLEEP
li r4,1
- b power7_powersave_common
+ LOAD_REG_ADDR(r5, power7_enter_nap_mode)
+ b power_powersave_common
/* No return */
_GLOBAL(power7_winkle)
- li r3,3
+ li r3,PNV_THREAD_WINKLE
li r4,1
- b power7_powersave_common
+ LOAD_REG_ADDR(r5, power7_enter_nap_mode)
+ b power_powersave_common
/* No return */
_GLOBAL(power7_wakeup_tb_loss)
diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
index 05954ae..ff7a541 100644
--- a/arch/powerpc/kernel/idle_power_common.S
+++ b/arch/powerpc/kernel/idle_power_common.S
@@ -21,8 +21,10 @@
* To check IRQ_HAPPENED in r4
* 0 - don't check
* 1 - check
+ *
+ * Address to 'rfid' to in r5
*/
-_GLOBAL(power7_powersave_common)
+_GLOBAL(power_powersave_common)
/* Use r3 to pass state nap/sleep/winkle */
/* NAP is a state loss, we create a regs frame on the
* stack, fill it up with the state we care about and
@@ -79,13 +81,12 @@ _GLOBAL(power7_powersave_common)
* because as soon as we do that, another thread can switch
* the MMU context to the guest.
*/
- LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
+ LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
li r6, MSR_RI
andc r6, r9, r6
- LOAD_REG_ADDR(r7, power7_enter_nap_mode)
mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
- mtspr SPRN_SRR0, r7
- mtspr SPRN_SRR1, r5
+ mtspr SPRN_SRR0, r5
+ mtspr SPRN_SRR1, r7
rfid
/* No return */
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (3 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-19 14:27 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized Shreyas B. Prabhu
` (3 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
Move idle related macros to a common location asm/cpuidle.h so that
they can be used for stop instruction support.
Signed-off-by: Shreyas B. Prabhy <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/cpuidle.h | 27 +++++++++++++++++++++++++++
arch/powerpc/kernel/idle_power7.S | 26 --------------------------
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h
index d2f99ca..faa97b7 100644
--- a/arch/powerpc/include/asm/cpuidle.h
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -17,4 +17,31 @@ extern u32 pnv_fastsleep_workaround_at_exit[];
#endif
+/* Idle state entry routines */
+#ifdef CONFIG_PPC_P7_NAP
+#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
+ /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
+ std r0,0(r1); \
+ ptesync; \
+ ld r0,0(r1); \
+1: cmp cr0,r0,r0; \
+ bne 1b; \
+ IDLE_INST; \
+ b .
+#endif /* CONFIG_PPC_P7_NAP */
+
+/*
+ * Use unused space in the interrupt stack to save and restore
+ * registers for deep-idle support.
+ */
+#define _SDR1 GPR3
+#define _RPR GPR4
+#define _SPURR GPR5
+#define _PURR GPR6
+#define _TSCR GPR7
+#define _DSCR GPR8
+#define _AMOR GPR9
+#define _WORT GPR10
+#define _WORC GPR11
+
#endif
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 1ea71d4..6a24769 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -24,32 +24,6 @@
#undef DEBUG
-/*
- * Use unused space in the interrupt stack to save and restore
- * registers for winkle support.
- */
-#define _SDR1 GPR3
-#define _RPR GPR4
-#define _SPURR GPR5
-#define _PURR GPR6
-#define _TSCR GPR7
-#define _DSCR GPR8
-#define _AMOR GPR9
-#define _WORT GPR10
-#define _WORC GPR11
-
-/* Idle state entry routines */
-
-#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
- /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
- std r0,0(r1); \
- ptesync; \
- ld r0,0(r1); \
-1: cmp cr0,r0,r0; \
- bne 1b; \
- IDLE_INST; \
- b .
-
.text
/*
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (4 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 6:45 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction Shreyas B. Prabhu
` (2 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
pnv_init_idle_states discovers supported idle states from the
device tree and does the required initialization. Set power_save
function pointer only after this initialization is done
Signed-off-by: Shreyas B. Prabhy <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/idle.c | 3 +++
arch/powerpc/platforms/powernv/setup.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index fcc8b68..fbb09fb 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -285,6 +285,9 @@ static int __init pnv_init_idle_states(void)
}
pnv_alloc_idle_core_states();
+
+ if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
+ ppc_md.power_save = power7_idle;
out_free:
kfree(flags);
out:
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 1acb0c7..c9685b6 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -312,7 +312,7 @@ define_machine(powernv) {
.get_proc_freq = pnv_get_proc_freq,
.progress = pnv_progress,
.machine_shutdown = pnv_shutdown,
- .power_save = power7_idle,
+ .power_save = NULL,
.calibrate_decr = generic_calibrate_decr,
#ifdef CONFIG_KEXEC
.kexec_cpu_down = pnv_kexec_cpu_down,
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (5 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 17:57 ` Gautham R Shenoy
2016-05-20 5:25 ` Paul Mackerras
2016-05-03 8:24 ` [PATCH v2 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined Shreyas B. Prabhu
8 siblings, 2 replies; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
PSSCR has following key fields
Bits 0:3 - Power-Saving Level Status. This field indicates the lowest
power-saving state the thread entered since stop instruction was last
executed.
Bit 42 - Enable State Loss
0 - No state is lost irrespective of other fields
1 - Allows state loss
Bits 44:47 - Power-Saving Level Limit
This limits the power-saving level that can be entered into.
Bits 60:63 - Requested Level
Used to specify which power-saving level must be entered on executing
stop instruction
This patch adds support for stop instruction and PSSCR handling.
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/cpuidle.h | 2 +
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerpc/include/asm/machdep.h | 1 +
arch/powerpc/include/asm/opal-api.h | 11 +-
arch/powerpc/include/asm/paca.h | 4 +
arch/powerpc/include/asm/ppc-opcode.h | 4 +
arch/powerpc/include/asm/processor.h | 1 +
arch/powerpc/include/asm/reg.h | 11 ++
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/asm-offsets.c | 4 +
arch/powerpc/kernel/idle_power7.S | 2 +-
arch/powerpc/kernel/idle_power_common.S | 26 +++-
arch/powerpc/kernel/idle_power_stop.S | 221 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/Kconfig | 4 +
arch/powerpc/platforms/powernv/Kconfig | 1 +
arch/powerpc/platforms/powernv/idle.c | 80 +++++++++--
16 files changed, 358 insertions(+), 17 deletions(-)
create mode 100644 arch/powerpc/kernel/idle_power_stop.S
diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h
index faa97b7..6d20583 100644
--- a/arch/powerpc/include/asm/cpuidle.h
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -13,6 +13,8 @@
#ifndef __ASSEMBLY__
extern u32 pnv_fastsleep_workaround_at_entry[];
extern u32 pnv_fastsleep_workaround_at_exit[];
+
+extern u64 pnv_first_deep_stop_state;
#endif
#endif
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 72b6225..d318d43 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -162,7 +162,7 @@ struct kvmppc_book3s_shadow_vcpu {
/* Values for kvm_state */
#define KVM_HWTHREAD_IN_KERNEL 0
-#define KVM_HWTHREAD_IN_NAP 1
+#define KVM_HWTHREAD_IN_IDLE 1
#define KVM_HWTHREAD_IN_KVM 2
#endif /* __ASM_KVM_BOOK3S_ASM_H__ */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index fd22442..ca4b116 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -261,6 +261,7 @@ struct machdep_calls {
extern void e500_idle(void);
extern void power4_idle(void);
extern void power7_idle(void);
+extern void power_stop0(void);
extern void ppc6xx_idle(void);
extern void book3e_idle(void);
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index f8faaae..3b978ba 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -162,13 +162,20 @@
/* Device tree flags */
-/* Flags set in power-mgmt nodes in device tree if
- * respective idle states are supported in the platform.
+/*
+ * Flags set in power-mgmt nodes in device tree describing
+ * idle states that are supported in the platform.
*/
+
+#define OPAL_PM_TIMEBASE_STOP 0x00000002
+#define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
+#define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
#define OPAL_PM_NAP_ENABLED 0x00010000
#define OPAL_PM_SLEEP_ENABLED 0x00020000
#define OPAL_PM_WINKLE_ENABLED 0x00040000
#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
+#define OPAL_PM_STOP_INST_FAST 0x00100000
+#define OPAL_PM_STOP_INST_DEEP 0x00200000
/*
* OPAL_CONFIG_CPU_IDLE_STATE parameters
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 546540b..bf48b7e 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -171,6 +171,10 @@ struct paca_struct {
/* Mask to denote subcore sibling threads */
u8 subcore_sibling_mask;
#endif
+#ifdef CONFIG_PPC_STOP_INST
+ /* Template for PSSCR with EC, ESL, TR, PSLL, MTL fields set */
+ u64 thread_psscr;
+#endif
#ifdef CONFIG_PPC_BOOK3S_64
/* Exclusive emergency stack pointer for machine check exception. */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 7ab04fc..f66747f 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -198,6 +198,8 @@
#define PPC_INST_SLEEP 0x4c0003a4
#define PPC_INST_WINKLE 0x4c0003e4
+#define PPC_INST_STOP 0x4c0002e4
+
/* A2 specific instructions */
#define PPC_INST_ERATWE 0x7c0001a6
#define PPC_INST_ERATRE 0x7c000166
@@ -368,6 +370,8 @@
#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
+#define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
+
/* BHRB instructions */
#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 009fab1..7f92fc8 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -457,6 +457,7 @@ extern int powersave_nap; /* set if nap mode can be used in idle loop */
extern unsigned long power7_nap(int check_irq);
extern unsigned long power7_sleep(void);
extern unsigned long power7_winkle(void);
+extern unsigned long power_stop(unsigned long state);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f5f4c66..f74c6a1 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -145,6 +145,16 @@
#define MSR_64BIT 0
#endif
+/* Power Management - PSSCR Fields */
+#define PSSCR_RL_MASK 0x0000000F
+#define PSSCR_MTL_MASK 0x000000F0
+#define PSSCR_TR_MASK 0x00000300
+#define PSSCR_PSLL_MASK 0x000F0000
+#define PSSCR_EC 0x00100000
+#define PSSCR_ESL 0x00200000
+#define PSSCR_SD 0x00400000
+
+
/* Floating Point Status and Control Register (FPSCR) Fields */
#define FPSCR_FX 0x80000000 /* FPU exception summary */
#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
@@ -288,6 +298,7 @@
#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
#define SPRN_PMSR 0x355 /* Power Management Status Reg */
#define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */
+#define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register */
#define SPRN_PMCR 0x374 /* Power Management Control Register */
/* HFSCR and FSCR bit numbers are the same */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index b877b84..052224e 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o
obj-$(CONFIG_PPC_POWERNV) += idle_power_common.o
+obj-$(CONFIG_PPC_STOP_INST) += idle_power_stop.o
procfs-y := proc_powerpc.o
obj-$(CONFIG_PROC_FS) += $(procfs-y)
rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 0d0183d..33191b1 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -771,6 +771,10 @@ int main(void)
offsetof(struct paca_struct, thread_mask));
DEFINE(PACA_SUBCORE_SIBLING_MASK,
offsetof(struct paca_struct, subcore_sibling_mask));
+#ifdef CONFIG_PPC_STOP_INST
+ DEFINE(PACA_THREAD_PSSCR,
+ offsetof(struct paca_struct, thread_psscr));
+#endif
#endif
DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 6a24769..d85f834 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -46,7 +46,7 @@ core_idle_lock_held:
power7_enter_nap_mode:
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
/* Tell KVM we're napping */
- li r4,KVM_HWTHREAD_IN_NAP
+ li r4,KVM_HWTHREAD_IN_IDLE
stb r4,HSTATE_HWTHREAD_STATE(r13)
#endif
stb r3,PACA_THREAD_IDLE_STATE(r13)
diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
index ff7a541..f260fa8 100644
--- a/arch/powerpc/kernel/idle_power_common.S
+++ b/arch/powerpc/kernel/idle_power_common.S
@@ -96,11 +96,35 @@ _GLOBAL(power_powersave_common)
* back to reset vector.
*/
_GLOBAL(power7_restore_hyp_resource)
+ GET_PACA(r13)
+BEGIN_FTR_SECTION_NESTED(888)
+ /*
+ * POWER ISA 3. Use PSSCR to determine if we
+ * are waking up from deep idle state
+ */
+ LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
+ ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
+
+ mfspr r5,SPRN_PSSCR
+ /*
+ * 0-4 bits correspond to Power-Saving Level Status
+ * which indicates the idle state we are waking up from
+ */
+ rldicl r5,r5,4,60
+ cmpd r5,r4
+ bge power_stop_wakeup_hyp_loss
/*
+ * Waking up without hypervisor state loss. Return to
+ * reset vector
+ */
+ blr
+
+END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300,CPU_FTR_ARCH_300,888)
+ /*
+ * POWER ISA 2.07 or less.
* Check if last bit of HSPGR0 is set. This indicates whether we are
* waking up from winkle.
*/
- GET_PACA(r13)
clrldi r5,r13,63
clrrdi r13,r13,1
cmpwi cr4,r5,1
diff --git a/arch/powerpc/kernel/idle_power_stop.S b/arch/powerpc/kernel/idle_power_stop.S
new file mode 100644
index 0000000..6c86c56
--- /dev/null
+++ b/arch/powerpc/kernel/idle_power_stop.S
@@ -0,0 +1,221 @@
+#include <linux/threads.h>
+
+#include <asm/processor.h>
+#include <asm/cputable.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/ppc-opcode.h>
+#include <asm/hw_irq.h>
+#include <asm/kvm_book3s_asm.h>
+#include <asm/opal.h>
+#include <asm/cpuidle.h>
+#include <asm/book3s/64/mmu-hash.h>
+#include <asm/exception-64s.h>
+
+#undef DEBUG
+
+/*
+ * rA - Requested stop state
+ * rB - Spare reg that can be used
+ */
+#define PSSCR_REQUEST_STATE(rA, rB) \
+ ld rB, PACA_THREAD_PSSCR(r13); \
+ or rB,rB,rA; \
+ mtspr SPRN_PSSCR, rB; \
+
+ .text
+
+ .globl power_enter_stop
+power_enter_stop:
+#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
+ /* Tell KVM we're napping */
+ li r4,KVM_HWTHREAD_IN_IDLE
+ stb r4,HSTATE_HWTHREAD_STATE(r13)
+#endif
+ LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
+ ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
+ cmpd cr3,r3,r4
+ bge 2f
+ IDLE_STATE_ENTER_SEQ(PPC_STOP)
+2:
+ lbz r7,PACA_THREAD_MASK(r13)
+ ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
+
+lwarx_loop1:
+ lwarx r15,0,r14
+ andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
+ bnel core_idle_lock_held
+ andc r15,r15,r7 /* Clear thread bit */
+
+ andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
+ stwcx. r15,0,r14
+ bne- lwarx_loop1
+
+ /*
+ * Note all register i.e per-core, per-subcore or per-thread is saved
+ * here since any thread in the core might wake up first
+ */
+ mfspr r3,SPRN_RPR
+ std r3,_RPR(r1)
+ mfspr r3,SPRN_SPURR
+ std r3,_SPURR(r1)
+ mfspr r3,SPRN_PURR
+ std r3,_PURR(r1)
+ mfspr r3,SPRN_TSCR
+ std r3,_TSCR(r1)
+ mfspr r3,SPRN_DSCR
+ std r3,_DSCR(r1)
+ mfspr r3,SPRN_AMOR
+ std r3,_AMOR(r1)
+
+ IDLE_STATE_ENTER_SEQ(PPC_STOP)
+
+
+_GLOBAL(power_stop)
+ PSSCR_REQUEST_STATE(r3,r4)
+ li r4, 1
+ LOAD_REG_ADDR(r5,power_enter_stop)
+ b power_powersave_common
+
+_GLOBAL(power_stop0)
+ li r3,0
+ li r4,1
+ LOAD_REG_ADDR(r5,power_enter_stop)
+ PSSCR_REQUEST_STATE(r3,r4)
+ b power_powersave_common
+
+_GLOBAL(power_stop_wakeup_hyp_loss)
+ ld r2,PACATOC(r13);
+ ld r1,PACAR1(r13)
+ /*
+ * Before entering any idle state, the NVGPRs are saved in the stack
+ * and they are restored before switching to the process context. Hence
+ * until they are restored, they are free to be used.
+ *
+ * Save SRR1 in a NVGPR as it might be clobbered in opal_call_realmode
+ * (called in CHECK_HMI_INTERRUPT). SRR1 is required to determine the
+ * wakeup reason if we branch to kvm_start_guest.
+ */
+ mflr r17
+ mfspr r16,SPRN_SRR1
+BEGIN_FTR_SECTION
+ CHECK_HMI_INTERRUPT
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+
+ lbz r7,PACA_THREAD_MASK(r13)
+ ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
+lwarx_loop2:
+ lwarx r15,0,r14
+ andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
+ /*
+ * Lock bit is set in one of the 2 cases-
+ * a. In the stop enter path, the last thread is executing
+ * fastsleep workaround code.
+ * b. In the wake up path, another thread is resyncing timebase or
+ * restoring context
+ * In either case loop until the lock bit is cleared.
+ */
+ bne core_idle_lock_held
+
+ cmpwi cr2,r15,0
+ lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
+ and r4,r4,r15
+ cmpwi cr1,r4,0 /* Check if first in subcore */
+
+ or r15,r15,r7 /* Set thread bit */
+
+ beq cr1,first_thread_in_subcore
+
+ /* Not first thread in subcore to wake up */
+ stwcx. r15,0,r14
+ bne- lwarx_loop2
+ isync
+ b common_exit
+
+core_idle_lock_held:
+ HMT_LOW
+core_idle_lock_loop:
+ lwz r15,0(14)
+ andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
+ bne core_idle_lock_loop
+ HMT_MEDIUM
+ b lwarx_loop2
+
+first_thread_in_subcore:
+ /* First thread in subcore to wakeup */
+ ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
+ stwcx. r15,0,r14
+ bne- lwarx_loop2
+ isync
+
+ /*
+ * If waking up from sleep, subcore state is not lost. Hence
+ * skip subcore state restore
+ */
+ bne cr4,subcore_state_restored
+
+ /* Restore per-subcore state */
+ ld r4,_RPR(r1)
+ mtspr SPRN_RPR,r4
+ ld r4,_AMOR(r1)
+ mtspr SPRN_AMOR,r4
+
+subcore_state_restored:
+ /*
+ * Check if the thread is also the first thread in the core. If not,
+ * skip to clear_lock.
+ */
+ bne cr2,clear_lock
+
+first_thread_in_core:
+
+timebase_resync:
+ /* Do timebase resync if we are waking up from sleep. Use cr3 value
+ * set in exceptions-64s.S */
+ ble cr3,clear_lock
+ /* Time base re-sync */
+ li r0,OPAL_RESYNC_TIMEBASE
+ bl opal_call_realmode;
+
+ /*
+ * If waking up from sleep, per core state is not lost, skip to
+ * clear_lock.
+ */
+ bne cr4,clear_lock
+
+ /* Restore per core state */
+ ld r4,_TSCR(r1)
+ mtspr SPRN_TSCR,r4
+
+clear_lock:
+ andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
+ lwsync
+ stw r15,0(r14)
+
+common_exit:
+ /*
+ * Common to all threads.
+ *
+ * If waking up from sleep, hypervisor state is not lost. Hence
+ * skip hypervisor state restore.
+ */
+ bne cr4,hypervisor_state_restored
+
+ /* Waking up from deep idle state */
+
+ /* Restore per thread state */
+ bl __restore_cpu_power8
+
+ ld r4,_SPURR(r1)
+ mtspr SPRN_SPURR,r4
+ ld r4,_PURR(r1)
+ mtspr SPRN_PURR,r4
+ ld r4,_DSCR(r1)
+ mtspr SPRN_DSCR,r4
+
+hypervisor_state_restored:
+
+ mtspr SPRN_SRR1,r16
+ mtlr r17
+ blr
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 46a3533..5fd9611 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -196,6 +196,10 @@ config PPC_P7_NAP
bool
default n
+config PPC_STOP_INST
+ bool
+ default n
+
config PPC_INDIRECT_PIO
bool
select GENERIC_IOMAP
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 604190c..9f65d4a 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -5,6 +5,7 @@ config PPC_POWERNV
select PPC_XICS
select PPC_ICP_NATIVE
select PPC_P7_NAP
+ select PPC_STOP_INST
select PPC_PCI_CHOICE if EMBEDDED
select EPAPR_BOOT
select PPC_INDIRECT_PIO
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index fbb09fb..45717ab 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -29,7 +29,7 @@
static u32 supported_cpuidle_states;
-int pnv_save_sprs_for_winkle(void)
+int pnv_save_sprs_for_deep_states(void)
{
int cpu;
int rc;
@@ -50,15 +50,19 @@ int pnv_save_sprs_for_winkle(void)
uint64_t pir = get_hard_smp_processor_id(cpu);
uint64_t hsprg0_val = (uint64_t)&paca[cpu];
- /*
- * HSPRG0 is used to store the cpu's pointer to paca. Hence last
- * 3 bits are guaranteed to be 0. Program slw to restore HSPRG0
- * with 63rd bit set, so that when a thread wakes up at 0x100 we
- * can use this bit to distinguish between fastsleep and
- * deep winkle.
- */
- hsprg0_val |= 1;
-
+ if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
+ /*
+ * HSPRG0 is used to store the cpu's pointer to paca.
+ * Hence last 3 bits are guaranteed to be 0. Program
+ * slw to restore HSPRG0 with 63rd bit set, so that
+ * when a thread wakes up at 0x100 we can use this bit
+ * to distinguish between fastsleep and deep winkle.
+ * This is not necessary with stop/psscr since PLS
+ * field of psscr indicates which state we are waking
+ * up from.
+ */
+ hsprg0_val |= 1;
+ }
rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
if (rc != 0)
return rc;
@@ -130,8 +134,8 @@ static void pnv_alloc_idle_core_states(void)
update_subcore_sibling_mask();
- if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED)
- pnv_save_sprs_for_winkle();
+ if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)
+ pnv_save_sprs_for_deep_states();
}
u32 pnv_get_supported_cpuidle_states(void)
@@ -230,11 +234,18 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
show_fastsleep_workaround_applyonce,
store_fastsleep_workaround_applyonce);
+/*
+ * First deep stop state. Used to figure out when to save/restore
+ * hypervisor context.
+ */
+u64 pnv_first_deep_stop_state;
+
static int __init pnv_init_idle_states(void)
{
struct device_node *power_mgt;
int dt_idle_states;
u32 *flags;
+ u64 *psscr_val = NULL;
int i;
supported_cpuidle_states = 0;
@@ -264,6 +275,30 @@ static int __init pnv_init_idle_states(void)
goto out_free;
}
+ if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+ psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
+ GFP_KERNEL);
+ if (of_property_read_u64_array(power_mgt,
+ "ibm,cpu-idle-state-psscr",
+ psscr_val, dt_idle_states)) {
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
+ goto out_free_psscr;
+ }
+
+ /*
+ * Set pnv_first_deep_stop_state to the first stop level
+ * to cause hypervisor state loss
+ */
+ pnv_first_deep_stop_state = 0xF;
+ for (i = 0; i < dt_idle_states; i++) {
+ u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK;
+
+ if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
+ (pnv_first_deep_stop_state > psscr_rl))
+ pnv_first_deep_stop_state = psscr_rl;
+ }
+ }
+
for (i = 0; i < dt_idle_states; i++)
supported_cpuidle_states |= flags[i];
@@ -286,8 +321,29 @@ static int __init pnv_init_idle_states(void)
pnv_alloc_idle_core_states();
+ if (supported_cpuidle_states & OPAL_PM_STOP_INST_FAST)
+ for_each_possible_cpu(i) {
+
+ u64 psscr_init_val = PSSCR_ESL | PSSCR_EC |
+ PSSCR_PSLL_MASK | PSSCR_TR_MASK |
+ PSSCR_MTL_MASK;
+
+ paca[i].thread_psscr = psscr_init_val;
+ /*
+ * Memory barrier to ensure that the writes to PACA
+ * goes through before ppc_md.power_save is updated
+ * below.
+ */
+ mb();
+ }
+
if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
ppc_md.power_save = power7_idle;
+ else if (supported_cpuidle_states & OPAL_PM_STOP_INST_FAST)
+ ppc_md.power_save = power_stop0;
+
+out_free_psscr:
+ kfree(psscr_val);
out_free:
kfree(flags);
out:
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (6 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined Shreyas B. Prabhu
8 siblings, 0 replies; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe
Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu,
Rafael J. Wysocki, Daniel Lezcano, linux-pm
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
Supported idle states and value to be written to PSSCR register to enter
any idle state is exposed via ibm,cpu-idle-state-names and
ibm,cpu-idle-state-psscr respectively. To enter an idle state,
platform provided power_stop() needs to be invoked with the appropriate
PSSCR value.
This patch adds support for this new mechanism in cpuidle powernv driver.
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-pm@vger.kernel.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
drivers/cpuidle/cpuidle-powernv.c | 57 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index e12dc30..efe5221 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -21,6 +21,7 @@
#include <asm/runlatch.h>
#define MAX_POWERNV_IDLE_STATES 8
+#define MAX_IDLE_STATE_NAME_LEN 10
struct cpuidle_driver powernv_idle_driver = {
.name = "powernv_idle",
@@ -29,9 +30,11 @@ struct cpuidle_driver powernv_idle_driver = {
static int max_idle_state;
static struct cpuidle_state *cpuidle_state_table;
+
+static u64 stop_psscr_table[MAX_POWERNV_IDLE_STATES];
+
static u64 snooze_timeout;
static bool snooze_timeout_en;
-
static int snooze_loop(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -139,6 +142,15 @@ static struct notifier_block setup_hotplug_notifier = {
.notifier_call = powernv_cpuidle_add_cpu_notifier,
};
+static int stop_loop(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ ppc64_runlatch_off();
+ power_stop(stop_psscr_table[index]);
+ ppc64_runlatch_on();
+ return index;
+}
/*
* powernv_cpuidle_driver_init()
*/
@@ -169,6 +181,8 @@ static int powernv_add_idle_states(void)
int nr_idle_states = 1; /* Snooze */
int dt_idle_states;
u32 *latency_ns, *residency_ns, *flags;
+ u64 *psscr_val = NULL;
+ const char *names[MAX_POWERNV_IDLE_STATES];
int i, rc;
/* Currently we have snooze statically defined */
@@ -201,6 +215,23 @@ static int powernv_add_idle_states(void)
goto out_free_latency;
}
+ rc = of_property_read_string_array(power_mgt,
+ "ibm,cpu-idle-state-names", names, dt_idle_states);
+ if (rc < -1) {
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-names in DT\n");
+ goto out_free_latency;
+ }
+
+ if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+ psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
+ GFP_KERNEL);
+ rc = of_property_read_u64_array(power_mgt,
+ "ibm,cpu-idle-state-psscr", psscr_val, dt_idle_states);
+ if (rc < -1) {
+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
+ goto out_free_psscr;
+ }
+ }
residency_ns = kzalloc(sizeof(*residency_ns) * dt_idle_states, GFP_KERNEL);
rc = of_property_read_u32_array(power_mgt,
"ibm,cpu-idle-state-residency-ns", residency_ns, dt_idle_states);
@@ -218,6 +249,16 @@ static int powernv_add_idle_states(void)
powernv_states[nr_idle_states].flags = 0;
powernv_states[nr_idle_states].target_residency = 100;
powernv_states[nr_idle_states].enter = &nap_loop;
+ } else if ((flags[i] & OPAL_PM_STOP_INST_FAST) &&
+ !(flags[i] & OPAL_PM_TIMEBASE_STOP)) {
+ strncpy(powernv_states[nr_idle_states].name,
+ (char *)names[i], MAX_IDLE_STATE_NAME_LEN);
+ strncpy(powernv_states[nr_idle_states].desc,
+ (char *)names[i], MAX_IDLE_STATE_NAME_LEN);
+ powernv_states[nr_idle_states].flags = 0;
+
+ powernv_states[nr_idle_states].enter = &stop_loop;
+ stop_psscr_table[nr_idle_states] = psscr_val[i];
}
/*
@@ -233,6 +274,18 @@ static int powernv_add_idle_states(void)
powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
powernv_states[nr_idle_states].target_residency = 300000;
powernv_states[nr_idle_states].enter = &fastsleep_loop;
+ } else if ((flags[i] & OPAL_PM_STOP_INST_DEEP) &&
+ (flags[i] & OPAL_PM_TIMEBASE_STOP)) {
+
+ strncpy(powernv_states[nr_idle_states].name,
+ (char *)names[i], MAX_IDLE_STATE_NAME_LEN);
+ strncpy(powernv_states[nr_idle_states].desc,
+ (char *)names[i], MAX_IDLE_STATE_NAME_LEN);
+
+ powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
+
+ powernv_states[nr_idle_states].enter = &stop_loop;
+ stop_psscr_table[nr_idle_states] = psscr_val[i];
}
#endif
powernv_states[nr_idle_states].exit_latency =
@@ -247,6 +300,8 @@ static int powernv_add_idle_states(void)
}
kfree(residency_ns);
+out_free_psscr:
+ kfree(psscr_val);
out_free_latency:
kfree(latency_ns);
out_free_flags:
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
` (7 preceding siblings ...)
2016-05-03 8:24 ` [PATCH v2 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
@ 2016-05-03 8:24 ` Shreyas B. Prabhu
2016-05-18 18:07 ` Gautham R Shenoy
8 siblings, 1 reply; 26+ messages in thread
From: Shreyas B. Prabhu @ 2016-05-03 8:24 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, paulus, linux-kernel, mikey, Shreyas B. Prabhu
If hardware supports stop state, use the deepest stop state when
the cpu is offlined.
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/idle.c | 15 +++++++++++++--
arch/powerpc/platforms/powernv/powernv.h | 1 +
arch/powerpc/platforms/powernv/smp.c | 4 +++-
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index 45717ab..cce4780 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -240,6 +240,11 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
*/
u64 pnv_first_deep_stop_state;
+/*
+ * Deepest stop idle state. Used when a cpu is offlined
+ */
+u64 pnv_deepest_stop_state;
+
static int __init pnv_init_idle_states(void)
{
struct device_node *power_mgt;
@@ -286,8 +291,11 @@ static int __init pnv_init_idle_states(void)
}
/*
- * Set pnv_first_deep_stop_state to the first stop level
- * to cause hypervisor state loss
+ * Set pnv_first_deep_stop_state and pnv_deepest_stop_state.
+ * pnv_first_deep_stop_state should be set to the first stop
+ * level to cause hypervisor state loss.
+ * pnv_deepest_stop_state should be set to the deepest stop
+ * stop state.
*/
pnv_first_deep_stop_state = 0xF;
for (i = 0; i < dt_idle_states; i++) {
@@ -296,6 +304,9 @@ static int __init pnv_init_idle_states(void)
if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
(pnv_first_deep_stop_state > psscr_rl))
pnv_first_deep_stop_state = psscr_rl;
+
+ if (pnv_deepest_stop_state < psscr_rl)
+ pnv_deepest_stop_state = psscr_rl;
}
}
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index 6dbc0a1..da7c843 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -18,6 +18,7 @@ static inline void pnv_pci_shutdown(void) { }
#endif
extern u32 pnv_get_supported_cpuidle_states(void);
+extern u64 pnv_deepest_stop_state;
extern void pnv_lpc_init(void);
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index ad7b1a3..f69ceb6 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -182,7 +182,9 @@ static void pnv_smp_cpu_kill_self(void)
ppc64_runlatch_off();
- if (idle_states & OPAL_PM_WINKLE_ENABLED)
+ if (cpu_has_feature(CPU_FTR_ARCH_300))
+ srr1 = power_stop(pnv_deepest_stop_state);
+ else if (idle_states & OPAL_PM_WINKLE_ENABLED)
srr1 = power7_winkle();
else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
(idle_states & OPAL_PM_SLEEP_ENABLED_ER1))
--
2.4.11
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header
2016-05-03 8:24 ` [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header Shreyas B. Prabhu
@ 2016-05-18 4:35 ` Gautham R Shenoy
2016-05-18 7:21 ` Shreyas B Prabhu
0 siblings, 1 reply; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 4:35 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:30PM +0530, Shreyas B. Prabhu wrote:
> CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move
> the macro to a common location (exception-64s.h)
> This patch does not change any functionality.
>
I suppose this code movement is to facilitate the invocation of
CHECK_HMI_INTERRUPT in some later patch ? In this case you could
add this to the commit message.
Otherwise,
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/exception-64s.h | 18 ++++++++++++++++++
> arch/powerpc/kernel/idle_power7.S | 20 +-------------------
> 2 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
> index 93ae809..6a625af 100644
> --- a/arch/powerpc/include/asm/exception-64s.h
> +++ b/arch/powerpc/include/asm/exception-64s.h
> @@ -545,4 +545,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
> #define FINISH_NAP
> #endif
>
> +#define CHECK_HMI_INTERRUPT \
> + mfspr r0,SPRN_SRR1; \
> +BEGIN_FTR_SECTION_NESTED(66); \
> + rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
> +FTR_SECTION_ELSE_NESTED(66); \
> + rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
> +ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
> + cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
> + bne 20f; \
> + /* Invoke opal call to handle hmi */ \
> + ld r2,PACATOC(r13); \
> + ld r1,PACAR1(r13); \
> + std r3,ORIG_GPR3(r1); /* Save original r3 */ \
> + li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
> + bl opal_call_realmode; \
> + ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
> +20: nop;
> +
> #endif /* _ASM_POWERPC_EXCEPTION_H */
> diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
> index 470ceeb..6b3404b 100644
> --- a/arch/powerpc/kernel/idle_power7.S
> +++ b/arch/powerpc/kernel/idle_power7.S
> @@ -19,6 +19,7 @@
> #include <asm/kvm_book3s_asm.h>
> #include <asm/opal.h>
> #include <asm/cpuidle.h>
> +#include <asm/exception-64s.h>
> #include <asm/book3s/64/mmu-hash.h>
>
> #undef DEBUG
> @@ -257,25 +258,6 @@ _GLOBAL(power7_winkle)
> b power7_powersave_common
> /* No return */
>
> -#define CHECK_HMI_INTERRUPT \
> - mfspr r0,SPRN_SRR1; \
> -BEGIN_FTR_SECTION_NESTED(66); \
> - rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
> -FTR_SECTION_ELSE_NESTED(66); \
> - rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
> -ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
> - cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
> - bne 20f; \
> - /* Invoke opal call to handle hmi */ \
> - ld r2,PACATOC(r13); \
> - ld r1,PACAR1(r13); \
> - std r3,ORIG_GPR3(r1); /* Save original r3 */ \
> - li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
> - bl opal_call_realmode; \
> - ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
> -20: nop;
> -
> -
> _GLOBAL(power7_wakeup_tb_loss)
> ld r2,PACATOC(r13);
> ld r1,PACAR1(r13)
> --
> 2.4.11
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function
2016-05-03 8:24 ` [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function Shreyas B. Prabhu
@ 2016-05-18 6:25 ` Gautham R Shenoy
2016-05-18 7:07 ` Shreyas B Prabhu
2016-05-20 1:45 ` Paul Mackerras
1 sibling, 1 reply; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 6:25 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
Hi Shreyas,
On Tue, May 03, 2016 at 01:54:31PM +0530, Shreyas B. Prabhu wrote:
> In the current code, when the thread wakes up in reset vector, some
> of the state restore code and check for whether a thread needs to
> branch to kvm is duplicated. Reorder the code such that this
> duplication is avoided.
>
> At a higher level this is what the change looks like-
I have manually verified that the code flow in the new patch is has
the same effect as whatever we were doing earlier. There a couple of
comments inline.
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index 7716ceb..7ebfbb0 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -107,25 +107,8 @@ BEGIN_FTR_SECTION
> beq 9f
>
> cmpwi cr3,r13,2
> + bl power7_restore_hyp_resource
>
> - /*
> - * Check if last bit of HSPGR0 is set. This indicates whether we are
> - * waking up from winkle.
> - */
> - GET_PACA(r13)
> - clrldi r5,r13,63
> - clrrdi r13,r13,1
> - cmpwi cr4,r5,1
> - mtspr SPRN_HSPRG0,r13
> -
> - lbz r0,PACA_THREAD_IDLE_STATE(r13)
> - cmpwi cr2,r0,PNV_THREAD_NAP
> - bgt cr2,8f /* Either sleep or Winkle */
> -
> - /* Waking up from nap should not cause hypervisor state loss */
> - bgt cr3,.
> -
> - /* Waking up from nap */
> li r0,PNV_THREAD_RUNNING
> stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
>
> @@ -143,13 +126,9 @@ BEGIN_FTR_SECTION
>
> /* Return SRR1 from power7_nap() */
> mfspr r3,SPRN_SRR1
> - beq cr3,2f
> - b power7_wakeup_noloss
> -2: b power7_wakeup_loss
> -
> - /* Fast Sleep wakeup on PowerNV */
> -8: GET_PACA(r13)
In the old code, we do a GET_PACA(r13) before invoking the
power7_wakeup_tb_loss. In the new code we don't. Can you explain
this omission ?
[..snip..]
> @@ -420,33 +451,9 @@ common_exit:
>
> hypervisor_state_restored:
>
> - li r5,PNV_THREAD_RUNNING
> - stb r5,PACA_THREAD_IDLE_STATE(r13)
> -
> mtspr SPRN_SRR1,r16
> -#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> - li r0,KVM_HWTHREAD_IN_KERNEL
> - stb r0,HSTATE_HWTHREAD_STATE(r13)
> - /* Order setting hwthread_state vs. testing hwthread_req */
> - sync
> - lbz r0,HSTATE_HWTHREAD_REQ(r13)
> - cmpwi r0,0
> - beq 6f
> - b kvm_start_guest
> -6:
> -#endif
> -
> - REST_NVGPRS(r1)
> - REST_GPR(2, r1)
> - ld r3,_CCR(r1)
> - ld r4,_MSR(r1)
> - ld r5,_NIP(r1)
> - addi r1,r1,INT_FRAME_SIZE
> - mtcr r3
> - mfspr r3,SPRN_SRR1 /* Return SRR1 */
> - mtspr SPRN_SRR1,r4
> - mtspr SPRN_SRR0,r5
> - rfid
> + mtlr r17
> + blr
Perhaps you could add a comment against this blr to indicate that we
go back to the reset vector right after the call to
power7_restore_hyp_resource.
>
> fastsleep_workaround_at_exit:
> li r3,1
> --
> 2.4.11
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location
2016-05-03 8:24 ` [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location Shreyas B. Prabhu
@ 2016-05-18 6:29 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 6:29 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, mikey, linuxppc-dev, linux-kernel
Hi Shreyas,
On Tue, May 03, 2016 at 01:54:32PM +0530, Shreyas B. Prabhu wrote:
> CPU-idle related code like context save/restore functions idle_power7.S
> can reused for adding stop instruction support. Move this
> code to a new commonly accessible location.
[..snip..]
> diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
> new file mode 100644
> index 0000000..05954ae
> --- /dev/null
> +++ b/arch/powerpc/kernel/idle_power_common.S
Since the new file is derived from idle_power7.S, you should add a
comment here to indicate that this shares the copyright history with
the original file.
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic
2016-05-03 8:24 ` [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic Shreyas B. Prabhu
@ 2016-05-18 6:37 ` Gautham R Shenoy
2016-05-18 6:51 ` Shreyas B Prabhu
0 siblings, 1 reply; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 6:37 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
Hi Shreyas,
On Tue, May 03, 2016 at 01:54:33PM +0530, Shreyas B. Prabhu wrote:
> power7_powersave_common does common steps needed before entering idle
> state and eventually changes MSR to MSR_IDLE and does rfid to
> power7_enter_nap_mode.
>
> Make it more generic by passing the rfid address as a function parameter.
> Also make function name more generic.
[..snip..]
>
> _GLOBAL(power7_winkle)
> - li r3,3
> + li r3,PNV_THREAD_WINKLE
This particular change above can go as an independent patch.
>
> _GLOBAL(power7_wakeup_tb_loss)
> diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
> index 05954ae..ff7a541 100644
> --- a/arch/powerpc/kernel/idle_power_common.S
> +++ b/arch/powerpc/kernel/idle_power_common.S
> @@ -21,8 +21,10 @@
> * To check IRQ_HAPPENED in r4
> * 0 - don't check
> * 1 - check
> + *
> + * Address to 'rfid' to in r5
> */
> -_GLOBAL(power7_powersave_common)
> +_GLOBAL(power_powersave_common)
> /* Use r3 to pass state nap/sleep/winkle */
> /* NAP is a state loss, we create a regs frame on the
> * stack, fill it up with the state we care about and
> @@ -79,13 +81,12 @@ _GLOBAL(power7_powersave_common)
> * because as soon as we do that, another thread can switch
> * the MMU context to the guest.
> */
> - LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
> + LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
> li r6, MSR_RI
> andc r6, r9, r6
> - LOAD_REG_ADDR(r7, power7_enter_nap_mode)
> mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
> - mtspr SPRN_SRR0, r7
> - mtspr SPRN_SRR1, r5
> + mtspr SPRN_SRR0, r5
> + mtspr SPRN_SRR1, r7
> rfid
> /* No return */
Any particular reason why you swapped the roles of r5 and r7 ?
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized
2016-05-03 8:24 ` [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized Shreyas B. Prabhu
@ 2016-05-18 6:45 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 6:45 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:35PM +0530, Shreyas B. Prabhu wrote:
> pnv_init_idle_states discovers supported idle states from the
> device tree and does the required initialization. Set power_save
> function pointer only after this initialization is done
>
> Signed-off-by: Shreyas B. Prabhy <shreyas@linux.vnet.ibm.com>
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/powernv/idle.c | 3 +++
> arch/powerpc/platforms/powernv/setup.c | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
> index fcc8b68..fbb09fb 100644
> --- a/arch/powerpc/platforms/powernv/idle.c
> +++ b/arch/powerpc/platforms/powernv/idle.c
> @@ -285,6 +285,9 @@ static int __init pnv_init_idle_states(void)
> }
>
> pnv_alloc_idle_core_states();
> +
> + if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
> + ppc_md.power_save = power7_idle;
> out_free:
> kfree(flags);
> out:
> diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
> index 1acb0c7..c9685b6 100644
> --- a/arch/powerpc/platforms/powernv/setup.c
> +++ b/arch/powerpc/platforms/powernv/setup.c
> @@ -312,7 +312,7 @@ define_machine(powernv) {
> .get_proc_freq = pnv_get_proc_freq,
> .progress = pnv_progress,
> .machine_shutdown = pnv_shutdown,
> - .power_save = power7_idle,
> + .power_save = NULL,
> .calibrate_decr = generic_calibrate_decr,
> #ifdef CONFIG_KEXEC
> .kexec_cpu_down = pnv_kexec_cpu_down,
> --
> 2.4.11
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic
2016-05-18 6:37 ` Gautham R Shenoy
@ 2016-05-18 6:51 ` Shreyas B Prabhu
2016-05-19 14:26 ` Gautham R Shenoy
0 siblings, 1 reply; 26+ messages in thread
From: Shreyas B Prabhu @ 2016-05-18 6:51 UTC (permalink / raw)
To: ego; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On 05/18/2016 12:07 PM, Gautham R Shenoy wrote:
> Hi Shreyas,
>
> On Tue, May 03, 2016 at 01:54:33PM +0530, Shreyas B. Prabhu wrote:
>> power7_powersave_common does common steps needed before entering idle
>> state and eventually changes MSR to MSR_IDLE and does rfid to
>> power7_enter_nap_mode.
>>
>> Make it more generic by passing the rfid address as a function parameter.
>> Also make function name more generic.
>
> [..snip..]
>
>>
>> _GLOBAL(power7_winkle)
>> - li r3,3
>> + li r3,PNV_THREAD_WINKLE
>
> This particular change above can go as an independent patch.
Okay.
>
>>
>> _GLOBAL(power7_wakeup_tb_loss)
>> diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
>> index 05954ae..ff7a541 100644
>> --- a/arch/powerpc/kernel/idle_power_common.S
>> +++ b/arch/powerpc/kernel/idle_power_common.S
>> @@ -21,8 +21,10 @@
>> * To check IRQ_HAPPENED in r4
>> * 0 - don't check
>> * 1 - check
>> + *
>> + * Address to 'rfid' to in r5
>> */
>> -_GLOBAL(power7_powersave_common)
>> +_GLOBAL(power_powersave_common)
>> /* Use r3 to pass state nap/sleep/winkle */
>> /* NAP is a state loss, we create a regs frame on the
>> * stack, fill it up with the state we care about and
>> @@ -79,13 +81,12 @@ _GLOBAL(power7_powersave_common)
>> * because as soon as we do that, another thread can switch
>> * the MMU context to the guest.
>> */
>> - LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
>> + LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
>> li r6, MSR_RI
>> andc r6, r9, r6
>> - LOAD_REG_ADDR(r7, power7_enter_nap_mode)
>> mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
>> - mtspr SPRN_SRR0, r7
>> - mtspr SPRN_SRR1, r5
>> + mtspr SPRN_SRR0, r5
>> + mtspr SPRN_SRR1, r7
>> rfid
>> /* No return */
>
> Any particular reason why you swapped the roles of r5 and r7 ?
>
With this patch, r5 which is the third parameter to
power_powersave_common contains the return address that needs to be
written to SRR0. So here I'm keeping r5 unaltered and using r7 for the MSR.
Thanks,
Shreyas
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function
2016-05-18 6:25 ` Gautham R Shenoy
@ 2016-05-18 7:07 ` Shreyas B Prabhu
2016-05-19 14:24 ` Gautham R Shenoy
0 siblings, 1 reply; 26+ messages in thread
From: Shreyas B Prabhu @ 2016-05-18 7:07 UTC (permalink / raw)
To: ego; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
Hi Gautham,
On 05/18/2016 11:55 AM, Gautham R Shenoy wrote:
> Hi Shreyas,
>
> On Tue, May 03, 2016 at 01:54:31PM +0530, Shreyas B. Prabhu wrote:
>> In the current code, when the thread wakes up in reset vector, some
>> of the state restore code and check for whether a thread needs to
>> branch to kvm is duplicated. Reorder the code such that this
>> duplication is avoided.
>>
>> At a higher level this is what the change looks like-
>
> I have manually verified that the code flow in the new patch is has
> the same effect as whatever we were doing earlier. There a couple of
> comments inline.
>
Thanks for the review!
>> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
>> index 7716ceb..7ebfbb0 100644
>> --- a/arch/powerpc/kernel/exceptions-64s.S
>> +++ b/arch/powerpc/kernel/exceptions-64s.S
>> @@ -107,25 +107,8 @@ BEGIN_FTR_SECTION
>> beq 9f
>>
>> cmpwi cr3,r13,2
>> + bl power7_restore_hyp_resource
>>
>> - /*
>> - * Check if last bit of HSPGR0 is set. This indicates whether we are
>> - * waking up from winkle.
>> - */
>> - GET_PACA(r13)
>> - clrldi r5,r13,63
>> - clrrdi r13,r13,1
>> - cmpwi cr4,r5,1
>> - mtspr SPRN_HSPRG0,r13
>> -
>> - lbz r0,PACA_THREAD_IDLE_STATE(r13)
>> - cmpwi cr2,r0,PNV_THREAD_NAP
>> - bgt cr2,8f /* Either sleep or Winkle */
>> -
>> - /* Waking up from nap should not cause hypervisor state loss */
>> - bgt cr3,.
>> -
>> - /* Waking up from nap */
>> li r0,PNV_THREAD_RUNNING
>> stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
>>
>> @@ -143,13 +126,9 @@ BEGIN_FTR_SECTION
>>
>> /* Return SRR1 from power7_nap() */
>> mfspr r3,SPRN_SRR1
>> - beq cr3,2f
>> - b power7_wakeup_noloss
>> -2: b power7_wakeup_loss
>> -
>> - /* Fast Sleep wakeup on PowerNV */
>> -8: GET_PACA(r13)
>
> In the old code, we do a GET_PACA(r13) before invoking the
> power7_wakeup_tb_loss. In the new code we don't. Can you explain
> this omission ?
GET_PACA(13) is the called in the beginning of
power7_restore_hyp_resource. So r13 contains pointer to PACA when
power7_wakeup_tb_loss invoked later in the same function.
>
>
> [..snip..]
>
>> @@ -420,33 +451,9 @@ common_exit:
>>
>> hypervisor_state_restored:
>>
>> - li r5,PNV_THREAD_RUNNING
>> - stb r5,PACA_THREAD_IDLE_STATE(r13)
>> -
>> mtspr SPRN_SRR1,r16
>> -#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
>> - li r0,KVM_HWTHREAD_IN_KERNEL
>> - stb r0,HSTATE_HWTHREAD_STATE(r13)
>> - /* Order setting hwthread_state vs. testing hwthread_req */
>> - sync
>> - lbz r0,HSTATE_HWTHREAD_REQ(r13)
>> - cmpwi r0,0
>> - beq 6f
>> - b kvm_start_guest
>> -6:
>> -#endif
>> -
>> - REST_NVGPRS(r1)
>> - REST_GPR(2, r1)
>> - ld r3,_CCR(r1)
>> - ld r4,_MSR(r1)
>> - ld r5,_NIP(r1)
>> - addi r1,r1,INT_FRAME_SIZE
>> - mtcr r3
>> - mfspr r3,SPRN_SRR1 /* Return SRR1 */
>> - mtspr SPRN_SRR1,r4
>> - mtspr SPRN_SRR0,r5
>> - rfid
>> + mtlr r17
>> + blr
>
>
> Perhaps you could add a comment against this blr to indicate that we
> go back to the reset vector right after the call to
> power7_restore_hyp_resource.
Ok. I'll do that.
>
>>
>> fastsleep_workaround_at_exit:
>> li r3,1
>> --
>> 2.4.11
>>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header
2016-05-18 4:35 ` Gautham R Shenoy
@ 2016-05-18 7:21 ` Shreyas B Prabhu
0 siblings, 0 replies; 26+ messages in thread
From: Shreyas B Prabhu @ 2016-05-18 7:21 UTC (permalink / raw)
To: ego; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On 05/18/2016 10:05 AM, Gautham R Shenoy wrote:
> On Tue, May 03, 2016 at 01:54:30PM +0530, Shreyas B. Prabhu wrote:
>> CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move
>> the macro to a common location (exception-64s.h)
>> This patch does not change any functionality.
>>
>
> I suppose this code movement is to facilitate the invocation of
> CHECK_HMI_INTERRUPT in some later patch ? In this case you could
> add this to the commit message.
>
Ok. I'll do that.
> Otherwise,
> Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Thanks for the review.
>> ---
>> arch/powerpc/include/asm/exception-64s.h | 18 ++++++++++++++++++
>> arch/powerpc/kernel/idle_power7.S | 20 +-------------------
>> 2 files changed, 19 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
>> index 93ae809..6a625af 100644
>> --- a/arch/powerpc/include/asm/exception-64s.h
>> +++ b/arch/powerpc/include/asm/exception-64s.h
>> @@ -545,4 +545,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
>> #define FINISH_NAP
>> #endif
>>
>> +#define CHECK_HMI_INTERRUPT \
>> + mfspr r0,SPRN_SRR1; \
>> +BEGIN_FTR_SECTION_NESTED(66); \
>> + rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
>> +FTR_SECTION_ELSE_NESTED(66); \
>> + rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
>> +ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
>> + cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
>> + bne 20f; \
>> + /* Invoke opal call to handle hmi */ \
>> + ld r2,PACATOC(r13); \
>> + ld r1,PACAR1(r13); \
>> + std r3,ORIG_GPR3(r1); /* Save original r3 */ \
>> + li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
>> + bl opal_call_realmode; \
>> + ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
>> +20: nop;
>> +
>> #endif /* _ASM_POWERPC_EXCEPTION_H */
>> diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
>> index 470ceeb..6b3404b 100644
>> --- a/arch/powerpc/kernel/idle_power7.S
>> +++ b/arch/powerpc/kernel/idle_power7.S
>> @@ -19,6 +19,7 @@
>> #include <asm/kvm_book3s_asm.h>
>> #include <asm/opal.h>
>> #include <asm/cpuidle.h>
>> +#include <asm/exception-64s.h>
>> #include <asm/book3s/64/mmu-hash.h>
>>
>> #undef DEBUG
>> @@ -257,25 +258,6 @@ _GLOBAL(power7_winkle)
>> b power7_powersave_common
>> /* No return */
>>
>> -#define CHECK_HMI_INTERRUPT \
>> - mfspr r0,SPRN_SRR1; \
>> -BEGIN_FTR_SECTION_NESTED(66); \
>> - rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
>> -FTR_SECTION_ELSE_NESTED(66); \
>> - rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
>> -ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
>> - cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
>> - bne 20f; \
>> - /* Invoke opal call to handle hmi */ \
>> - ld r2,PACATOC(r13); \
>> - ld r1,PACAR1(r13); \
>> - std r3,ORIG_GPR3(r1); /* Save original r3 */ \
>> - li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
>> - bl opal_call_realmode; \
>> - ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
>> -20: nop;
>> -
>> -
>> _GLOBAL(power7_wakeup_tb_loss)
>> ld r2,PACATOC(r13);
>> ld r1,PACAR1(r13)
>> --
>> 2.4.11
>>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction
2016-05-03 8:24 ` [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction Shreyas B. Prabhu
@ 2016-05-18 17:57 ` Gautham R Shenoy
2016-05-20 5:25 ` Paul Mackerras
1 sibling, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 17:57 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
Hi Shreyas,
On Tue, May 03, 2016 at 01:54:36PM +0530, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
> a) new instruction named stop is added. This instruction replaces
> instructions like nap, sleep, rvwinkle.
> b) new per thread SPR named PSSCR is added which controls the behavior
> of stop instruction.
>
> PSSCR has following key fields
> Bits 0:3 - Power-Saving Level Status. This field indicates the lowest
> power-saving state the thread entered since stop instruction was last
> executed.
>
> Bit 42 - Enable State Loss
> 0 - No state is lost irrespective of other fields
> 1 - Allows state loss
>
> Bits 44:47 - Power-Saving Level Limit
> This limits the power-saving level that can be entered into.
>
> Bits 60:63 - Requested Level
> Used to specify which power-saving level must be entered on executing
> stop instruction
>
> This patch adds support for stop instruction and PSSCR handling.
>
> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
[..snip..]
> diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
> index 6a24769..d85f834 100644
> --- a/arch/powerpc/kernel/idle_power7.S
> +++ b/arch/powerpc/kernel/idle_power7.S
> @@ -46,7 +46,7 @@ core_idle_lock_held:
> power7_enter_nap_mode:
> #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> /* Tell KVM we're napping */
> - li r4,KVM_HWTHREAD_IN_NAP
> + li r4,KVM_HWTHREAD_IN_IDLE
> stb r4,HSTATE_HWTHREAD_STATE(r13)
> #endif
> stb r3,PACA_THREAD_IDLE_STATE(r13)
> diff --git a/arch/powerpc/kernel/idle_power_common.S b/arch/powerpc/kernel/idle_power_common.S
> index ff7a541..f260fa8 100644
> --- a/arch/powerpc/kernel/idle_power_common.S
> +++ b/arch/powerpc/kernel/idle_power_common.S
> @@ -96,11 +96,35 @@ _GLOBAL(power_powersave_common)
> * back to reset vector.
> */
> _GLOBAL(power7_restore_hyp_resource)
> + GET_PACA(r13)
> +BEGIN_FTR_SECTION_NESTED(888)
> + /*
> + * POWER ISA 3. Use PSSCR to determine if we
> + * are waking up from deep idle state
> + */
> + LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
> + ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
> +
> + mfspr r5,SPRN_PSSCR
> + /*
> + * 0-4 bits correspond to Power-Saving Level Status
> + * which indicates the idle state we are waking up from
> + */
> + rldicl r5,r5,4,60
> + cmpd r5,r4
> + bge power_stop_wakeup_hyp_loss
> /*
> + * Waking up without hypervisor state loss. Return to
> + * reset vector
> + */
> + blr
> +
> +END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300,CPU_FTR_ARCH_300,888)
> + /*
> + * POWER ISA 2.07 or less.
> * Check if last bit of HSPGR0 is set. This indicates whether we are
> * waking up from winkle.
> */
> - GET_PACA(r13)
> clrldi r5,r13,63
> clrrdi r13,r13,1
> cmpwi cr4,r5,1
> diff --git a/arch/powerpc/kernel/idle_power_stop.S b/arch/powerpc/kernel/idle_power_stop.S
> new file mode 100644
> index 0000000..6c86c56
> --- /dev/null
> +++ b/arch/powerpc/kernel/idle_power_stop.S
> @@ -0,0 +1,221 @@
> +#include <linux/threads.h>
> +
> +#include <asm/processor.h>
> +#include <asm/cputable.h>
> +#include <asm/thread_info.h>
> +#include <asm/ppc_asm.h>
> +#include <asm/asm-offsets.h>
> +#include <asm/ppc-opcode.h>
> +#include <asm/hw_irq.h>
> +#include <asm/kvm_book3s_asm.h>
> +#include <asm/opal.h>
> +#include <asm/cpuidle.h>
> +#include <asm/book3s/64/mmu-hash.h>
> +#include <asm/exception-64s.h>
> +
> +#undef DEBUG
> +
> +/*
> + * rA - Requested stop state
> + * rB - Spare reg that can be used
> + */
> +#define PSSCR_REQUEST_STATE(rA, rB) \
> + ld rB, PACA_THREAD_PSSCR(r13); \
> + or rB,rB,rA; \
> + mtspr SPRN_PSSCR, rB; \
> +
> + .text
> +
> + .globl power_enter_stop
> +power_enter_stop:
> +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> + /* Tell KVM we're napping */
> + li r4,KVM_HWTHREAD_IN_IDLE
> + stb r4,HSTATE_HWTHREAD_STATE(r13)
> +#endif
> + LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
> + ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
> + cmpd cr3,r3,r4
It is not clear what r3 is supposed to contain at this point. I think
it should contain the requested stop state. But I might be wrong!
Perhaps a comment above power_enter_stop can clarify that.
> + bge 2f
> + IDLE_STATE_ENTER_SEQ(PPC_STOP)
> +2:
> + lbz r7,PACA_THREAD_MASK(r13)
> + ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
> +
> +lwarx_loop1:
> + lwarx r15,0,r14
> + andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
> + bnel core_idle_lock_held
The definition of core_idle_lock_held below jumps to lwarx_loop2
instead of doing a blr once it observed that the LOCK_BIT is no longer
set. This doesn't seem correct since the purpose of
core_idle_lock_held is to spin until the LOCK_BIT is cleared and then
resume whatever we were supposed to do next.
Can you clarify this part ?
> + andc r15,r15,r7 /* Clear thread bit */
> +
> + andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
> + stwcx. r15,0,r14
> + bne- lwarx_loop1
> +
> + /*
> + * Note all register i.e per-core, per-subcore or per-thread is saved
> + * here since any thread in the core might wake up first
> + */
> + mfspr r3,SPRN_RPR
> + std r3,_RPR(r1)
> + mfspr r3,SPRN_SPURR
> + std r3,_SPURR(r1)
> + mfspr r3,SPRN_PURR
> + std r3,_PURR(r1)
> + mfspr r3,SPRN_TSCR
> + std r3,_TSCR(r1)
> + mfspr r3,SPRN_DSCR
> + std r3,_DSCR(r1)
> + mfspr r3,SPRN_AMOR
> + std r3,_AMOR(r1)
> +
> + IDLE_STATE_ENTER_SEQ(PPC_STOP)
> +
> +
> +_GLOBAL(power_stop)
> + PSSCR_REQUEST_STATE(r3,r4)
> + li r4, 1
> + LOAD_REG_ADDR(r5,power_enter_stop)
> + b power_powersave_common
> +
> +_GLOBAL(power_stop0)
> + li r3,0
> + li r4,1
> + LOAD_REG_ADDR(r5,power_enter_stop)
> + PSSCR_REQUEST_STATE(r3,r4)
r4 will get clobbered at this point. Move PSSCR_REQUEST_STATE before
"li r4,1".
Also why cant this simply call "power_stop" having set r3
to 0 ?
> + b power_powersave_common
> +
> +_GLOBAL(power_stop_wakeup_hyp_loss)
> + ld r2,PACATOC(r13);
> + ld r1,PACAR1(r13)
> + /*
> + * Before entering any idle state, the NVGPRs are saved in the stack
> + * and they are restored before switching to the process context. Hence
> + * until they are restored, they are free to be used.
> + *
> + * Save SRR1 in a NVGPR as it might be clobbered in opal_call_realmode
> + * (called in CHECK_HMI_INTERRUPT). SRR1 is required to determine the
> + * wakeup reason if we branch to kvm_start_guest.
> + */
Retain the comment from an earlier patch explaning why LR is being
cached in r17.
> + mflr r17
> + mfspr r16,SPRN_SRR1
> +BEGIN_FTR_SECTION
> + CHECK_HMI_INTERRUPT
> +END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
> +
> + lbz r7,PACA_THREAD_MASK(r13)
> + ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
> +lwarx_loop2:
> + lwarx r15,0,r14
> + andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
> + /*
> + * Lock bit is set in one of the 2 cases-
> + * a. In the stop enter path, the last thread is executing
> + * fastsleep workaround code.
> + * b. In the wake up path, another thread is resyncing timebase or
> + * restoring context
> + * In either case loop until the lock bit is cleared.
> + */
> + bne core_idle_lock_held
> +
> + cmpwi cr2,r15,0
> + lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
> + and r4,r4,r15
> + cmpwi cr1,r4,0 /* Check if first in subcore */
> +
> + or r15,r15,r7 /* Set thread bit */
> +
> + beq cr1,first_thread_in_subcore
> +
> + /* Not first thread in subcore to wake up */
> + stwcx. r15,0,r14
> + bne- lwarx_loop2
> + isync
> + b common_exit
The code from lwarx_loop2 till the end of the definition of
common_exit is the same as the lwarx_loop2 to common_exit in
idle_power7.S. Well, except for a minor bit in the manner in which
return from core_idle_lock_held is handled and the fact that we're not
defining pnv_fastsleep_workaround_at_exit immediately in
first_thread_in_core. I prefer the original version where
core_idle_lock_held does a blr instead of explicitly jumping back to
lwarx_loop2 since it can be invoked safely from multiple places.
Can we move this to a common place and invoke it from these two places
instead of duplicating the code ?
> +
> +core_idle_lock_held:
> + HMT_LOW
> +core_idle_lock_loop:
> + lwz r15,0(14)
> + andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
> + bne core_idle_lock_loop
> + HMT_MEDIUM
> + b lwarx_loop2
> +
> +first_thread_in_subcore:
> + /* First thread in subcore to wakeup */
> + ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
> + stwcx. r15,0,r14
> + bne- lwarx_loop2
> + isync
> +
> + /*
> + * If waking up from sleep, subcore state is not lost. Hence
> + * skip subcore state restore
> + */
> + bne cr4,subcore_state_restored
> +
> + /* Restore per-subcore state */
> + ld r4,_RPR(r1)
> + mtspr SPRN_RPR,r4
> + ld r4,_AMOR(r1)
> + mtspr SPRN_AMOR,r4
> +
> +subcore_state_restored:
> + /*
> + * Check if the thread is also the first thread in the core. If not,
> + * skip to clear_lock.
> + */
> + bne cr2,clear_lock
> +
> +first_thread_in_core:
I suppose we don't need the pnv_fastsleep_workaround_at_exit at this
point anymore.
> +
> +timebase_resync:
> + /* Do timebase resync if we are waking up from sleep. Use cr3 value
> + * set in exceptions-64s.S */
> + ble cr3,clear_lock
> + /* Time base re-sync */
> + li r0,OPAL_RESYNC_TIMEBASE
> + bl opal_call_realmode;
> +
> + /*
> + * If waking up from sleep, per core state is not lost, skip to
> + * clear_lock.
> + */
> + bne cr4,clear_lock
> +
> + /* Restore per core state */
> + ld r4,_TSCR(r1)
> + mtspr SPRN_TSCR,r4
> +
> +clear_lock:
> + andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
> + lwsync
> + stw r15,0(r14)
> +
> +common_exit:
> + /*
> + * Common to all threads.
> + *
> + * If waking up from sleep, hypervisor state is not lost. Hence
> + * skip hypervisor state restore.
> + */
> + bne cr4,hypervisor_state_restored
> +
> + /* Waking up from deep idle state */
> +
> + /* Restore per thread state */
> + bl __restore_cpu_power8
> +
> + ld r4,_SPURR(r1)
> + mtspr SPRN_SPURR,r4
> + ld r4,_PURR(r1)
> + mtspr SPRN_PURR,r4
> + ld r4,_DSCR(r1)
> + mtspr SPRN_DSCR,r4
> +
> +hypervisor_state_restored:
> +
> + mtspr SPRN_SRR1,r16
> + mtlr r17
> + blr
[..snip..]
> @@ -264,6 +275,30 @@ static int __init pnv_init_idle_states(void)
> goto out_free;
> }
>
> + if (cpu_has_feature(CPU_FTR_ARCH_300)) {
> + psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
> + GFP_KERNEL);
Need to handle the case whe the kcalloc fails to allocate memory for
psscr_val here.
> + if (of_property_read_u64_array(power_mgt,
> + "ibm,cpu-idle-state-psscr",
> + psscr_val, dt_idle_states)) {
> + pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
> + goto out_free_psscr;
> + }
The remainder of the patch looks ok.
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined
2016-05-03 8:24 ` [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined Shreyas B. Prabhu
@ 2016-05-18 18:07 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-18 18:07 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:38PM +0530, Shreyas B. Prabhu wrote:
> If hardware supports stop state, use the deepest stop state when
>
> the cpu is offlined.
>
> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function
2016-05-18 7:07 ` Shreyas B Prabhu
@ 2016-05-19 14:24 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-19 14:24 UTC (permalink / raw)
To: Shreyas B Prabhu; +Cc: ego, mpe, linuxppc-dev, paulus, linux-kernel, mikey
Hi Shreyas,
On Wed, May 18, 2016 at 12:37:56PM +0530, Shreyas B Prabhu wrote:
[..snip..]
> >> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> >> index 7716ceb..7ebfbb0 100644
> >> --- a/arch/powerpc/kernel/exceptions-64s.S
> >> +++ b/arch/powerpc/kernel/exceptions-64s.S
> >> @@ -107,25 +107,8 @@ BEGIN_FTR_SECTION
> >> beq 9f
> >>
> >> cmpwi cr3,r13,2
> >> + bl power7_restore_hyp_resource
> >>
> >> - /*
> >> - * Check if last bit of HSPGR0 is set. This indicates whether we are
> >> - * waking up from winkle.
> >> - */
> >> - GET_PACA(r13)
> >> - clrldi r5,r13,63
> >> - clrrdi r13,r13,1
> >> - cmpwi cr4,r5,1
> >> - mtspr SPRN_HSPRG0,r13
> >> -
> >> - lbz r0,PACA_THREAD_IDLE_STATE(r13)
> >> - cmpwi cr2,r0,PNV_THREAD_NAP
> >> - bgt cr2,8f /* Either sleep or Winkle */
> >> -
> >> - /* Waking up from nap should not cause hypervisor state loss */
> >> - bgt cr3,.
> >> -
> >> - /* Waking up from nap */
> >> li r0,PNV_THREAD_RUNNING
> >> stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
> >>
> >> @@ -143,13 +126,9 @@ BEGIN_FTR_SECTION
> >>
> >> /* Return SRR1 from power7_nap() */
> >> mfspr r3,SPRN_SRR1
> >> - beq cr3,2f
> >> - b power7_wakeup_noloss
> >> -2: b power7_wakeup_loss
> >> -
> >> - /* Fast Sleep wakeup on PowerNV */
> >> -8: GET_PACA(r13)
> >
> > In the old code, we do a GET_PACA(r13) before invoking the
> > power7_wakeup_tb_loss. In the new code we don't. Can you explain
> > this omission ?
>
> GET_PACA(13) is the called in the beginning of
> power7_restore_hyp_resource. So r13 contains pointer to PACA when
> power7_wakeup_tb_loss invoked later in the same function.
Ah, I see it now. So the GET_PACA(r13) at 8: was anyway redundant in
the older code.
You can add my Reviewed-by: to this patch.
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic
2016-05-18 6:51 ` Shreyas B Prabhu
@ 2016-05-19 14:26 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-19 14:26 UTC (permalink / raw)
To: Shreyas B Prabhu; +Cc: ego, mpe, linuxppc-dev, paulus, linux-kernel, mikey
On Wed, May 18, 2016 at 12:21:17PM +0530, Shreyas B Prabhu wrote:
> With this patch, r5 which is the third parameter to
> power_powersave_common contains the return address that needs to be
> written to SRR0. So here I'm keeping r5 unaltered and using r7 for the MSR.
Ok.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
>
> Thanks,
> Shreyas
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h
2016-05-03 8:24 ` [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h Shreyas B. Prabhu
@ 2016-05-19 14:27 ` Gautham R Shenoy
0 siblings, 0 replies; 26+ messages in thread
From: Gautham R Shenoy @ 2016-05-19 14:27 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, paulus, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:34PM +0530, Shreyas B. Prabhu wrote:
> Move idle related macros to a common location asm/cpuidle.h so that
> they can be used for stop instruction support.
>
> Signed-off-by: Shreyas B. Prabhy <shreyas@linux.vnet.ibm.com>
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
--
Thanks and Regards
gautham.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function
2016-05-03 8:24 ` [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function Shreyas B. Prabhu
2016-05-18 6:25 ` Gautham R Shenoy
@ 2016-05-20 1:45 ` Paul Mackerras
1 sibling, 0 replies; 26+ messages in thread
From: Paul Mackerras @ 2016-05-20 1:45 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:31PM +0530, Shreyas B. Prabhu wrote:
> In the current code, when the thread wakes up in reset vector, some
> of the state restore code and check for whether a thread needs to
> branch to kvm is duplicated. Reorder the code such that this
> duplication is avoided.
This is a nice cleanup. The one minor comment I have is that since
power7_restore_hyp_resource has some unusual entry requirements (such
as requiring cr3 to be set a certain way), those requirements should
be documented in the comment just about the function entry point. I
didn't see any unusual exit conditions, but if there are any they
should be documented too.
Reviewed-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction
2016-05-03 8:24 ` [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction Shreyas B. Prabhu
2016-05-18 17:57 ` Gautham R Shenoy
@ 2016-05-20 5:25 ` Paul Mackerras
2016-05-20 6:16 ` Shreyas B Prabhu
1 sibling, 1 reply; 26+ messages in thread
From: Paul Mackerras @ 2016-05-20 5:25 UTC (permalink / raw)
To: Shreyas B. Prabhu; +Cc: mpe, linuxppc-dev, linux-kernel, mikey
On Tue, May 03, 2016 at 01:54:36PM +0530, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
> a) new instruction named stop is added. This instruction replaces
> instructions like nap, sleep, rvwinkle.
> b) new per thread SPR named PSSCR is added which controls the behavior
> of stop instruction.
>
> PSSCR has following key fields
> Bits 0:3 - Power-Saving Level Status. This field indicates the lowest
> power-saving state the thread entered since stop instruction was last
> executed.
>
> Bit 42 - Enable State Loss
> 0 - No state is lost irrespective of other fields
> 1 - Allows state loss
>
> Bits 44:47 - Power-Saving Level Limit
> This limits the power-saving level that can be entered into.
>
> Bits 60:63 - Requested Level
> Used to specify which power-saving level must be entered on executing
> stop instruction
>
> This patch adds support for stop instruction and PSSCR handling.
I notice that you have duplicated a whole lot of assembly code
relating to synchronizing between threads going into and out of
power-saving modes, saving/restoring SPRs, resyncing the timebase, and
so on.
Two questions arise:
- Are we really going to have to do all of that in the same way for
POWER9 as we did for POWER8? You even copied over a comment about
the fastsleep workaround, which I really hope we won't have to do on
POWER9. Also, on POWER9, the threads are much more independent, so
I was not expecting that there would still be shared registers.
- If we do have to do all that, could we use the same code as on
POWER8 rather than having another copy of all that code?
Paul.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction
2016-05-20 5:25 ` Paul Mackerras
@ 2016-05-20 6:16 ` Shreyas B Prabhu
0 siblings, 0 replies; 26+ messages in thread
From: Shreyas B Prabhu @ 2016-05-20 6:16 UTC (permalink / raw)
To: Paul Mackerras
Cc: mpe, linuxppc-dev, linux-kernel, mikey, ego >> Gautham R. Shenoy
On 05/20/2016 10:55 AM, Paul Mackerras wrote:
> On Tue, May 03, 2016 at 01:54:36PM +0530, Shreyas B. Prabhu wrote:
>> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>> a) new instruction named stop is added. This instruction replaces
>> instructions like nap, sleep, rvwinkle.
>> b) new per thread SPR named PSSCR is added which controls the behavior
>> of stop instruction.
>>
>> PSSCR has following key fields
>> Bits 0:3 - Power-Saving Level Status. This field indicates the lowest
>> power-saving state the thread entered since stop instruction was last
>> executed.
>>
>> Bit 42 - Enable State Loss
>> 0 - No state is lost irrespective of other fields
>> 1 - Allows state loss
>>
>> Bits 44:47 - Power-Saving Level Limit
>> This limits the power-saving level that can be entered into.
>>
>> Bits 60:63 - Requested Level
>> Used to specify which power-saving level must be entered on executing
>> stop instruction
>>
>> This patch adds support for stop instruction and PSSCR handling.
>
> I notice that you have duplicated a whole lot of assembly code
> relating to synchronizing between threads going into and out of
> power-saving modes, saving/restoring SPRs, resyncing the timebase, and
> so on.
>
> Two questions arise:
>
> - Are we really going to have to do all of that in the same way for
> POWER9 as we did for POWER8? You even copied over a comment about
> the fastsleep workaround, which I really hope we won't have to do on
> POWER9. Also, on POWER9, the threads are much more independent, so
> I was not expecting that there would still be shared registers.
Copying of comment regarding fastsleep workaround was an oversight. It
will not be necessary in POWER9. I'll fix that in the next version.
The need for synchronizing between threads going into and out of
power-saving modes still exists. Resyncing timebase and restoring few
registers still have to be done once per core.
>
> - If we do have to do all that, could we use the same code as on
> POWER8 rather than having another copy of all that code?
>
While we could use the same code I felt that handling POWER8 and POWER9
cases in the same file might make the code more complicated.
Gautham suggested we can use the same POWER8 code and use FTR sections
wherever POWER8 and POWER9 deviate. If you feel that is better I can
implement that in the next version.
Thanks,
Shreyas
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2016-05-20 7:04 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-03 8:24 [PATCH v2 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header Shreyas B. Prabhu
2016-05-18 4:35 ` Gautham R Shenoy
2016-05-18 7:21 ` Shreyas B Prabhu
2016-05-03 8:24 ` [PATCH v2 2/9] powerpc/kvm: make hypervisor state restore a function Shreyas B. Prabhu
2016-05-18 6:25 ` Gautham R Shenoy
2016-05-18 7:07 ` Shreyas B Prabhu
2016-05-19 14:24 ` Gautham R Shenoy
2016-05-20 1:45 ` Paul Mackerras
2016-05-03 8:24 ` [PATCH v2 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location Shreyas B. Prabhu
2016-05-18 6:29 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 4/9] powerpc/powernv: Make power7_powersave_common more generic Shreyas B. Prabhu
2016-05-18 6:37 ` Gautham R Shenoy
2016-05-18 6:51 ` Shreyas B Prabhu
2016-05-19 14:26 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 5/9] powerpc/powernv: Move idle related macros to cpuidle.h Shreyas B. Prabhu
2016-05-19 14:27 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 6/9] powerpc/powernv: set power_save func after the idle states are initialized Shreyas B. Prabhu
2016-05-18 6:45 ` Gautham R Shenoy
2016-05-03 8:24 ` [PATCH v2 7/9] powerpc/powernv: Add platform support for stop instruction Shreyas B. Prabhu
2016-05-18 17:57 ` Gautham R Shenoy
2016-05-20 5:25 ` Paul Mackerras
2016-05-20 6:16 ` Shreyas B Prabhu
2016-05-03 8:24 ` [PATCH v2 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states Shreyas B. Prabhu
2016-05-03 8:24 ` [PATCH v2 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined Shreyas B. Prabhu
2016-05-18 18:07 ` Gautham R Shenoy
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