From: Paul Burton <paul.burton@imgtec.com>
To: <linux-mips@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
Thomas Gleixner <tglx@linutronix.de>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 16/26] irqchip: mips-cpu: Prepare for non-legacy IRQ domains
Date: Fri, 26 Aug 2016 16:37:15 +0100 [thread overview]
Message-ID: <20160826153725.11629-17-paul.burton@imgtec.com> (raw)
In-Reply-To: <20160826153725.11629-1-paul.burton@imgtec.com>
The various struct irq_chip callbacks in the MIPS CPU interrupt
controller driver have been calculating the hardware interrupt number by
subtracting MIPS_CPU_IRQ_BASE from the virq number. This presumes a
linear mapping beginning from MIPS_CPU_IRQ_BASE, and this will not hold
once an IPI IRQ domain is introduced. Switch to using the hwirq field of
struct irq_data which already contains the hardware interrupt number
instead of attempting to calculate it.
Similarly, plat_irq_dispatch calculated the virq number by adding
MIPS_CPU_IRQ_BASE to the hardware interrupt number. Ready this for the
introduction of an IPI IRQ domain by instead using irq_linear_revmap.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
drivers/irqchip/irq-mips-cpu.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index e6b4136..338de92 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -39,15 +39,17 @@
#include <asm/mipsmtregs.h>
#include <asm/setup.h>
+static struct irq_domain *irq_domain;
+
static inline void unmask_mips_irq(struct irq_data *d)
{
- set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+ set_c0_status(IE_SW0 << d->hwirq);
irq_enable_hazard();
}
static inline void mask_mips_irq(struct irq_data *d)
{
- clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_status(IE_SW0 << d->hwirq);
irq_disable_hazard();
}
@@ -70,7 +72,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << d->hwirq);
evpe(vpflags);
unmask_mips_irq(d);
return 0;
@@ -83,7 +85,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
static void mips_mt_cpu_irq_ack(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(C_SW0 << d->hwirq);
evpe(vpflags);
mask_mips_irq(d);
}
@@ -103,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
asmlinkage void __weak plat_irq_dispatch(void)
{
unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
+ unsigned int virq;
int irq;
if (!pending) {
@@ -113,7 +116,8 @@ asmlinkage void __weak plat_irq_dispatch(void)
pending >>= CAUSEB_IP;
while (pending) {
irq = fls(pending) - 1;
- do_IRQ(MIPS_CPU_IRQ_BASE + irq);
+ virq = irq_linear_revmap(irq_domain, irq);
+ do_IRQ(virq);
pending &= ~BIT(irq);
}
}
@@ -145,15 +149,14 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
static void __init __mips_cpu_irq_init(struct device_node *of_node)
{
- struct irq_domain *domain;
-
/* Mask interrupts. */
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
- &mips_cpu_intc_irq_domain_ops, NULL);
- if (!domain)
+ irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ &mips_cpu_intc_irq_domain_ops,
+ NULL);
+ if (!irq_domain)
panic("Failed to add irqdomain for MIPS CPU");
}
--
2.9.3
next prev parent reply other threads:[~2016-08-26 15:42 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-26 15:36 [PATCH 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
2016-08-26 15:37 ` [PATCH 01/26] MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC Paul Burton
2016-08-26 15:37 ` [PATCH 02/26] MIPS: PCI: Make pcibios_set_cache_line_size an initcall Paul Burton
2016-08-26 15:37 ` [PATCH 03/26] MIPS: PCI: Inline pcibios_assign_all_busses Paul Burton
2016-08-26 15:37 ` [PATCH 04/26] MIPS: PCI: Split pci.c into pci.c & pci-legacy.c Paul Burton
2016-08-26 15:37 ` [PATCH 05/26] MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY Paul Burton
2016-08-26 15:37 ` [PATCH 06/26] MIPS: PCI: Support generic drivers Paul Burton
2016-08-26 15:37 ` [PATCH 07/26] MIPS: Sanitise coherentio semantics Paul Burton
2016-08-26 15:37 ` [PATCH 08/26] MIPS: dma-default: Don't check hw_coherentio if device is non-coherent Paul Burton
2016-08-26 15:37 ` [PATCH 09/26] MIPS: Support per-device DMA coherence Paul Burton
2016-08-26 15:37 ` [PATCH 10/26] MIPS: Print CM error reports upon bus errors Paul Burton
2016-08-26 15:37 ` [PATCH 11/26] dt-bindings: Document mti,mips-cpc binding Paul Burton
2016-09-02 12:34 ` Rob Herring
2016-09-02 13:59 ` Paul Burton
2016-08-26 15:37 ` [PATCH 12/26] MIPS: CPC: Provide a default mips_cpc_default_phys_base Paul Burton
2016-08-26 15:37 ` [PATCH 13/26] dt-bindings: Document mti,mips-cdmm binding Paul Burton
2016-09-02 12:38 ` Rob Herring
2016-08-26 15:37 ` [PATCH 14/26] MIPS: CDMM: Allow CDMM base address to be specified via DT Paul Burton
2016-08-26 15:37 ` [PATCH 15/26] irqchip: mips-cpu: Replace magic 0x100 with IE_SW0 Paul Burton
2016-08-26 15:37 ` Paul Burton [this message]
2016-08-26 15:37 ` [PATCH 17/26] irqchip: mips-cpu: Introduce IPI IRQ domain support Paul Burton
2016-08-26 15:37 ` [PATCH 18/26] MIPS: smp-mt: Use CPU interrupt controller " Paul Burton
2016-08-26 15:37 ` [PATCH 19/26] MIPS: Stengthen IPI IRQ domain sanity check Paul Burton
2016-08-26 15:37 ` [PATCH 20/26] MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 Paul Burton
2016-08-26 15:37 ` [PATCH 21/26] MIPS: Support generating Flattened Image Trees (.itb) Paul Burton
2016-08-26 15:37 ` [PATCH 22/26] MIPS: generic: Introduce generic DT-based board support Paul Burton
2017-11-19 3:43 ` [22/26] " Guenter Roeck
2017-11-20 10:25 ` James Hogan
2017-11-20 14:03 ` Guenter Roeck
2017-11-21 0:02 ` [PATCH] MIPS: Fix CPS SMP NS16550 UART defaults James Hogan
2017-11-21 3:32 ` Guenter Roeck
2017-12-25 17:43 ` Guenter Roeck
2016-08-26 15:37 ` [PATCH 23/26] MIPS: generic: Convert SEAD-3 to a generic board Paul Burton
2016-08-26 15:37 ` [PATCH 24/26] dt-bindings: Document img,boston-clock binding Paul Burton
2016-08-26 17:44 ` Stephen Boyd
2016-08-30 15:53 ` Paul Burton
2016-09-02 12:54 ` Rob Herring
2016-09-02 13:33 ` Paul Burton
2016-08-26 15:37 ` [PATCH 25/26] clk: boston: Add a driver for MIPS Boston board clocks Paul Burton
2016-08-26 17:41 ` Stephen Boyd
2016-08-30 15:06 ` Paul Burton
2016-08-26 15:37 ` [PATCH 26/26] MIPS: generic: Support MIPS Boston development boards Paul Burton
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