* [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
@ 2016-12-21 11:49 ` Bjorn Andersson
2017-01-07 1:07 ` John Stultz
2016-12-21 11:49 ` [PATCH 3/5] ARM: dts: qcom: apq8064-sony-yuga: Enable riva-pil Bjorn Andersson
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, John Stultz
Add nodes for the Riva PIL, IRIS RF module, BT and WiFI services exposed
by the Riva firmware and the related memory reserve.
Also provides pinctrl nodes for devices enabling the riva-pil.
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 18 +++++++++
arch/arm/boot/dts/qcom-apq8064.dtsi | 69 +++++++++++++++++++++++++++++++-
2 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 6b801e7e57a2..5c023e649882 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -284,4 +284,22 @@
bias-disable = <0>;
};
};
+
+ riva_fm_pin_a: riva-fm-active {
+ pins = "gpio14", "gpio15";
+ function = "riva_fm";
+ };
+
+ riva_bt_pin_a: riva-bt-active {
+ pins = "gpio16", "gpio17";
+ function = "riva_bt";
+ };
+
+ riva_wlan_pin_a: riva-wlan-active {
+ pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
+ function = "riva_wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 78bf155a52f3..3dc7a7aa3450 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -21,6 +21,11 @@
reg = <0x80000000 0x200000>;
no-map;
};
+
+ wcnss_mem: wcnss@8f000000 {
+ reg = <0x8f000000 0x700000>;
+ no-map;
+ };
};
cpus {
@@ -179,7 +184,7 @@
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
@@ -1419,6 +1424,68 @@
};
};
};
+
+ riva: riva-pil@3204000 {
+ compatible = "qcom,riva-pil";
+
+ reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal";
+
+ memory-region = <&wcnss_mem>;
+
+ vddcx-supply = <&pm8921_s3>;
+ vddmx-supply = <&pm8921_l24>;
+ vddpx-supply = <&pm8921_s4>;
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3660";
+
+ clocks = <&cxo_board>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8921_l4>;
+ vddrfa-supply = <&pm8921_s2>;
+ vddpa-supply = <&pm8921_l10>;
+ vdddig-supply = <&pm8921_lvs2>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&l2cc 8 25>;
+ qcom,smd-edge = <6>;
+
+ label = "riva";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&riva>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
};
};
#include "qcom-apq8064-pins.dtsi"
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node
2016-12-21 11:49 ` [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node Bjorn Andersson
@ 2017-01-07 1:07 ` John Stultz
0 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2017-01-07 1:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, linux-soc,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, lkml
On Wed, Dec 21, 2016 at 3:49 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> Add nodes for the Riva PIL, IRIS RF module, BT and WiFI services exposed
> by the Riva firmware and the related memory reserve.
>
> Also provides pinctrl nodes for devices enabling the riva-pil.
>
> Cc: John Stultz <john.stultz@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: John Stultz <john.stultz@linaro.org>
thanks
-john
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/5] ARM: dts: qcom: apq8064-sony-yuga: Enable riva-pil
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
2016-12-21 11:49 ` [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node Bjorn Andersson
@ 2016-12-21 11:49 ` Bjorn Andersson
2016-12-21 11:49 ` [PATCH 4/5] ARM: dts: qcom: sd600-eval: pm8921_s2 regulator properties Bjorn Andersson
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, John Stultz
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
index ebd675ca94b4..a34ba3555454 100644
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
@@ -390,5 +390,12 @@
pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] ARM: dts: qcom: sd600-eval: pm8921_s2 regulator properties
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
2016-12-21 11:49 ` [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node Bjorn Andersson
2016-12-21 11:49 ` [PATCH 3/5] ARM: dts: qcom: apq8064-sony-yuga: Enable riva-pil Bjorn Andersson
@ 2016-12-21 11:49 ` Bjorn Andersson
2016-12-21 11:49 ` [PATCH 5/5] ARM: dts: qcom: sd600eval: Enable riva-pil Bjorn Andersson
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel
Add the missing properties for pm8921 smps2.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index 39ae2bc8cb08..b7dcab28642d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -74,6 +74,14 @@
bias-pull-down;
};
+ s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
+
s3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] ARM: dts: qcom: sd600eval: Enable riva-pil
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
` (2 preceding siblings ...)
2016-12-21 11:49 ` [PATCH 4/5] ARM: dts: qcom: sd600-eval: pm8921_s2 regulator properties Bjorn Andersson
@ 2016-12-21 11:49 ` Bjorn Andersson
2016-12-29 3:14 ` [1/5] ARM: dts: qcom: apq8064: Add missing scm clock Andy Gross
2017-01-07 1:10 ` [PATCH 1/5] " John Stultz
5 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index b7dcab28642d..8fee42901a3d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -355,5 +355,12 @@
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [1/5] ARM: dts: qcom: apq8064: Add missing scm clock
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
` (3 preceding siblings ...)
2016-12-21 11:49 ` [PATCH 5/5] ARM: dts: qcom: sd600eval: Enable riva-pil Bjorn Andersson
@ 2016-12-29 3:14 ` Andy Gross
2017-01-07 1:10 ` [PATCH 1/5] " John Stultz
5 siblings, 0 replies; 10+ messages in thread
From: Andy Gross @ 2016-12-29 3:14 UTC (permalink / raw)
To: Bjorn Andersson
Cc: David Brown, Mark Rutland, devicetree, linux-arm-msm,
linux-kernel, Rob Herring, John Stultz, linux-soc,
linux-arm-kernel
On Wed, Dec 21, 2016 at 03:49:35AM -0800, Bjorn Andersson wrote:
> As per the device tree binding the apq8064 scm node requires the core
> clock to be specified, so add this.
>
> Cc: John Stultz <john.stultz@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 268bd470c865..78bf155a52f3 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -303,6 +303,9 @@
> firmware {
> scm {
> compatible = "qcom,scm-apq8064";
> +
> + clocks = <&gcc CE3_CORE_CLK>;
> + clock-names = "core";
Isn't this supposed to be the DFAB clk? The RPM one? I think that's why we let
the clock just fall through optionally before the recent changes that broke
this.
Regards,
Andy
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock
2016-12-21 11:49 [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock Bjorn Andersson
` (4 preceding siblings ...)
2016-12-29 3:14 ` [1/5] ARM: dts: qcom: apq8064: Add missing scm clock Andy Gross
@ 2017-01-07 1:10 ` John Stultz
2017-01-07 3:01 ` Andy Gross
5 siblings, 1 reply; 10+ messages in thread
From: John Stultz @ 2017-01-07 1:10 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, linux-soc,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, lkml
On Wed, Dec 21, 2016 at 3:49 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> As per the device tree binding the apq8064 scm node requires the core
> clock to be specified, so add this.
>
> Cc: John Stultz <john.stultz@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 268bd470c865..78bf155a52f3 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -303,6 +303,9 @@
> firmware {
> scm {
> compatible = "qcom,scm-apq8064";
> +
> + clocks = <&gcc CE3_CORE_CLK>;
> + clock-names = "core";
Tested-by: John Stultz <john.stultz@linaro.org>
I know Bjorn has a new version of this patch that uses the
RPM_DAYTONA_FABRIC_CLK value, but that one results in problems with
usb gadget functionality on my Nexus7. This one seems to work ok
though.
thanks
-john
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock
2017-01-07 1:10 ` [PATCH 1/5] " John Stultz
@ 2017-01-07 3:01 ` Andy Gross
2017-01-07 7:30 ` Bjorn Andersson
0 siblings, 1 reply; 10+ messages in thread
From: Andy Gross @ 2017-01-07 3:01 UTC (permalink / raw)
To: John Stultz
Cc: Bjorn Andersson, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, linux-soc,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, lkml
On Fri, Jan 06, 2017 at 05:10:44PM -0800, John Stultz wrote:
> On Wed, Dec 21, 2016 at 3:49 AM, Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
> > As per the device tree binding the apq8064 scm node requires the core
> > clock to be specified, so add this.
> >
> > Cc: John Stultz <john.stultz@linaro.org>
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > index 268bd470c865..78bf155a52f3 100644
> > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > @@ -303,6 +303,9 @@
> > firmware {
> > scm {
> > compatible = "qcom,scm-apq8064";
> > +
> > + clocks = <&gcc CE3_CORE_CLK>;
> > + clock-names = "core";
>
>
> Tested-by: John Stultz <john.stultz@linaro.org>
>
> I know Bjorn has a new version of this patch that uses the
> RPM_DAYTONA_FABRIC_CLK value, but that one results in problems with
> usb gadget functionality on my Nexus7. This one seems to work ok
> though.
Odd. Is the usb gadget using the daytona but not getting a reference? I wonder
if this is related to not having the bus driver running the bus clk enablement
and frequencies.
Andy
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock
2017-01-07 3:01 ` Andy Gross
@ 2017-01-07 7:30 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2017-01-07 7:30 UTC (permalink / raw)
To: Andy Gross
Cc: John Stultz, David Brown, Rob Herring, Mark Rutland,
linux-arm-msm, linux-soc,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, lkml
On Fri 06 Jan 19:01 PST 2017, Andy Gross wrote:
> On Fri, Jan 06, 2017 at 05:10:44PM -0800, John Stultz wrote:
> > On Wed, Dec 21, 2016 at 3:49 AM, Bjorn Andersson
> > <bjorn.andersson@linaro.org> wrote:
> > > As per the device tree binding the apq8064 scm node requires the core
> > > clock to be specified, so add this.
> > >
> > > Cc: John Stultz <john.stultz@linaro.org>
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > > arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > index 268bd470c865..78bf155a52f3 100644
> > > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > @@ -303,6 +303,9 @@
> > > firmware {
> > > scm {
> > > compatible = "qcom,scm-apq8064";
> > > +
> > > + clocks = <&gcc CE3_CORE_CLK>;
> > > + clock-names = "core";
> >
> >
> > Tested-by: John Stultz <john.stultz@linaro.org>
> >
> > I know Bjorn has a new version of this patch that uses the
> > RPM_DAYTONA_FABRIC_CLK value, but that one results in problems with
> > usb gadget functionality on my Nexus7. This one seems to work ok
> > though.
>
> Odd. Is the usb gadget using the daytona but not getting a reference? I wonder
> if this is related to not having the bus driver running the bus clk enablement
> and frequencies.
>
The fact that we now reference the Daytona clock means that we're also
telling the RPM to disable it, so that might very well be the case.
Unfortunately I can't find any block diagram for 8064 to show what hangs
off the Daytona, so I'm not sure in what way USB should reference it.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 10+ messages in thread