[PATCH v2 0/6] Updates for Marvell Switch SoCs

[PATCH v2 0/6] Updates for Marvell Switch SoCs

[Chris Packham]

Shortly after I posted my last series I got access to a more recent
Marvell SDK which had some device tree support for the switch SoCs I'd
been wanting. It was still based on an older kernel but it was a huge
improvement over what came before.

Patch 1/6 is a typo I noticed after my initial series was applied.

Patch 2/6 is a bit of a cleanup. I did initially struggle with how to
access individual parts of the DFX block as well as retaining a handle on
the entire thing for the switch driver to use.

Patch 3/6 is a re-jig of the dtsi files which is needed by 5/6. This is
required because I need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.

Patch 4/6, 5/6 are split from the previous versions.

Patch 6/6 is the device tree portion of a change already in clk-next.

Chris Packham (6):
  ARM: dts: Fix typo in armada-xp-98dx4251
    Changes in v2
    - new
    Changes in v3:
    - none
  ARM: dts: armada-xp-98dx3236: combine dfx server nodes
    Changes in v2:
    - none
    Changes in v3:
    - none
  ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
    Changes in v2:
    - Update root compatible strings in armada-xp-98dx3336.dtsi,
      armada-xp-98dx4251.dtsi, armada-xp-db-dxbc2.dts and
      armada-xp-db-xc3-24g4xg.dts
    Changes in v3:
    - none
  ARM: dts: mvebu: Add binding for mv98dx3236-soc-id
    Changes in v3:
    - new, split from driver
  ARM: mvebu: Add driver for mv98dx3236-soc-id
    Changes in v2:
    - none
    Changes in v3:
    - split from dts changes
  ARM: dts: mvebu: Move mv98dx3236 clock bindings
    Changes in v2:
    - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support"
    Changes in v3:
    - Clarify why the old location was wrong (but worked).


 .../bindings/arm/marvell/mv98dx3236-soc-id.txt     |  14 ++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
 .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
 .../devicetree/bindings/net/marvell,prestera.txt   |  13 +-
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 213 ++++++++++++++++-----
 arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |   2 +-
 arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |   2 +-
 arch/arm/boot/dts/armada-xp-db-dxbc2.dts           |   2 +-
 arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts      |   2 +-
 arch/arm/mach-mvebu/mvebu-soc-id.c                 |  43 ++++-
 10 files changed, 242 insertions(+), 67 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt

-- 
2.11.0.24.ge6920cf

[PATCH v3 1/6] ARM: dts: Fix typo in armada-xp-98dx4251

[Chris Packham]

The compatible should be 98dx4251 not 98dx4521.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - new
    Changes in v3:
    - none

 arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index 4b0533a4ccb7..b9d9b269efb4 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -49,7 +49,7 @@
 
 / {
 	model = "Marvell 98DX4251 SoC";
-	compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	cpus {
 		cpu@1 {
-- 
2.11.0.24.ge6920cf

Re: [PATCH v3 1/6] ARM: dts: Fix typo in armada-xp-98dx4251

[Rob Herring]

On Thu, Feb 16, 2017 at 09:50:35PM +1300, Chris Packham wrote:
> The compatible should be 98dx4251 not 98dx4521.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> 
> Notes:
>     Changes in v2:
>     - new
>     Changes in v3:
>     - none
> 
>  arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 2/6] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

[Chris Packham]

Rather than having a separate node for the dfx server add a reg property
to the parent node. This give some compatibility with the Marvell
supplied SDK.

As no upstream driver currently exists for this block and support for
this SoC is still quite fresh in the kernel it should not be necessary
to retain a backwards compatible binding.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - none
    Changes in v3:
    - update commit message to indicate backwards incompatible change and
      why it's OK
    - retain dfx-server compatible string

 Documentation/devicetree/bindings/net/marvell,prestera.txt | 13 +++++--------
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  | 10 +++-------
 2 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
index 5fbab29718e8..c329608fa887 100644
--- a/Documentation/devicetree/bindings/net/marvell,prestera.txt
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -32,19 +32,16 @@ DFX Server bindings
 -------------------
 
 Required properties:
-- compatible: must be "marvell,dfx-server"
+- compatible: must be "marvell,dfx-server", "simple-bus"
+- ranges: describes the address mapping of a memory-mapped bus.
 - reg: address and length of the register set for the device.
 
 Example:
 
-dfx-registers {
-	compatible = "simple-bus";
+dfx-server {
+	compatible = "marvell,dfx-server", "simple-bus";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
-
-	dfx: dfx@0 {
-		compatible = "marvell,dfx-server";
-		reg = <0 0x100000>;
-	};
+	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 };
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index f6a03dcee5ef..7eaa7da84770 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -195,11 +195,12 @@
 			};
 		};
 
-		dfxr: dfx-registers@ac000000 {
-			compatible = "simple-bus";
+		dfx: dfx-server@ac000000 {
+			compatible = "marvell,dfx-server", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
 			dfx_coredivclk: corediv-clock@f8268 {
 				compatible = "marvell,mv98dx3236-corediv-clock";
@@ -208,11 +209,6 @@
 				clocks = <&mainpll>;
 				clock-output-names = "nand";
 			};
-
-			dfx: dfx@0 {
-				compatible = "marvell,dfx-server";
-				reg = <0 0x100000>;
-			};
 		};
 
 		switch: switch@a8000000 {
-- 
2.11.0.24.ge6920cf

Re: [PATCH v3 2/6] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

[Rob Herring]

On Thu, Feb 16, 2017 at 09:50:36PM +1300, Chris Packham wrote:
> Rather than having a separate node for the dfx server add a reg property
> to the parent node. This give some compatibility with the Marvell
> supplied SDK.
> 
> As no upstream driver currently exists for this block and support for
> this SoC is still quite fresh in the kernel it should not be necessary
> to retain a backwards compatible binding.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> 
> Notes:
>     Changes in v2:
>     - none
>     Changes in v3:
>     - update commit message to indicate backwards incompatible change and
>       why it's OK
>     - retain dfx-server compatible string
> 
>  Documentation/devicetree/bindings/net/marvell,prestera.txt | 13 +++++--------
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  | 10 +++-------
>  2 files changed, 8 insertions(+), 15 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 3/6] ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236

[Chris Packham]

The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - Update root compatible strings in armada-xp-98dx3336.dtsi,
      armada-xp-98dx4251.dtsi, armada-xp-db-dxbc2.dts and
      armada-xp-db-xc3-24g4xg.dts
    Changes in v3:
    - none

 arch/arm/boot/dts/armada-xp-98dx3236.dtsi     | 194 ++++++++++++++++++++------
 arch/arm/boot/dts/armada-xp-98dx3336.dtsi     |   2 +-
 arch/arm/boot/dts/armada-xp-98dx4251.dtsi     |   2 +-
 arch/arm/boot/dts/armada-xp-db-dxbc2.dts      |   2 +-
 arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts |   2 +-
 5 files changed, 155 insertions(+), 47 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 7eaa7da84770..5e7245524d46 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -45,11 +45,14 @@
  * common to all Armada XP SoCs.
  */
 
-#include "armada-xp.dtsi"
+#include "armada-370-xp.dtsi"
 
 / {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
 	model = "Marvell 98DX3236 SoC";
-	compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
 	aliases {
 		gpio0 = &gpio0;
@@ -72,12 +75,19 @@
 	};
 
 	soc {
+		compatible = "marvell,armadaxp-mbus", "simple-bus";
+
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
 			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
 			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
 
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+		};
+
 		/*
 		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
 		 */
@@ -117,31 +127,92 @@
 		};
 
 		internal-regs {
+			sdramc@1400 {
+				compatible = "marvell,armada-xp-sdram-controller";
+				reg = <0x1400 0x500>;
+			};
+
+			L2: l2-cache@8000 {
+				compatible = "marvell,aurora-system-cache";
+				reg = <0x08000 0x1000>;
+				cache-id-part = <0x100>;
+				cache-level = <2>;
+				cache-unified;
+				wt-override;
+			};
+
+			gpio0: gpio@18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <82>, <83>, <84>, <85>;
+			};
+
+			/* does not exist */
+			gpio1: gpio@18140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18140 0x40>;
+				status = "disabled";
+			};
+
+			gpio2: gpio@18180 { /* rework some properties */
+				compatible = "marvell,orion-gpio";
+				reg = <0x18180 0x40>;
+				ngpios = <1>; /* only gpio #32 */
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <87>;
+			};
+
+			systemc: system-controller@18200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0x18200 0x500>;
+			};
+
+			gateclk: clock-gating-control@18220 {
+				compatible = "marvell,armada-xp-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
 			coreclk: mvebu-sar@18230 {
 				compatible = "marvell,mv98dx3236-core-clock";
+				reg = <0x18230 0x08>;
+				#clock-cells = <1>;
 			};
 
 			cpuclk: clock-complex@18700 {
+				#clock-cells = <1>;
 				compatible = "marvell,mv98dx3236-cpu-clock";
+				reg = <0x18700 0x24>, <0x1c054 0x10>;
+				clocks = <&coreclk 1>;
 			};
 
 			corediv-clock@18740 {
 				status = "disabled";
 			};
 
-			xor@60900 {
-				status = "disabled";
+			cpu-config@21000 {
+				compatible = "marvell,armada-xp-cpu-config";
+				reg = <0x21000 0x8>;
 			};
 
-			crypto@90000 {
-				status = "disabled";
+			ethernet@70000 {
+				compatible = "marvell,armada-xp-neta";
 			};
 
-			xor@f0900 {
-				status = "disabled";
+			ethernet@74000 {
+				compatible = "marvell,armada-xp-neta";
 			};
 
-			xor@f0800 {
+			xor1: xor@f0800 {
 				compatible = "marvell,orion-xor";
 				reg = <0xf0800 0x100
 				       0xf0a00 0x100>;
@@ -161,37 +232,28 @@
 				};
 			};
 
-			gpio0: gpio@18100 {
-				compatible = "marvell,orion-gpio";
-				reg = <0x18100 0x40>;
-				ngpios = <32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <82>, <83>, <84>, <85>;
-			};
-
-			/* does not exist */
-			gpio1: gpio@18140 {
-				compatible = "marvell,orion-gpio";
-				reg = <0x18140 0x40>;
-				status = "disabled";
+			nand: nand@d0000 {
+				clocks = <&dfx_coredivclk 0>;
 			};
 
-			gpio2: gpio@18180 { /* rework some properties */
-				compatible = "marvell,orion-gpio";
-				reg = <0x18180 0x40>;
-				ngpios = <1>; /* only gpio #32 */
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <87>;
-			};
+			xor0: xor@f0900 {
+				compatible = "marvell,orion-xor";
+				reg = <0xF0900 0x100
+				       0xF0B00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
 
-			nand: nand@d0000 {
-				clocks = <&dfx_coredivclk 0>;
+				xor00 {
+					interrupts = <94>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <95>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
 			};
 		};
 
@@ -225,6 +287,53 @@
 			};
 		};
 	};
+
+	clocks {
+		/* 25 MHz reference crystal */
+		refclk: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+};
+
+&i2c0 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11100 0x100>;
+};
+
+&mpic {
+	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+	compatible = "marvell,armada-xp-timer";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+	compatible = "marvell,armada-xp-wdt";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+	reg = <0x20800 0x20>;
+};
+
+&usb0 {
+	clocks = <&gateclk 18>;
+};
+
+&usb1 {
+	clocks = <&gateclk 19>;
 };
 
 &pinctrl {
@@ -237,14 +346,13 @@
 	};
 };
 
-&sdio {
-	status = "disabled";
+&spi0 {
+	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
 };
 
-&crypto_sram0 {
+&sdio {
 	status = "disabled";
 };
 
-&crypto_sram1 {
-	status = "disabled";
-};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index e1580afdc260..a0d81bd7312b 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -49,7 +49,7 @@
 
 / {
 	model = "Marvell 98DX3336 SoC";
-	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
 	cpus {
 		cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index b9d9b269efb4..51de91b31a9d 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -49,7 +49,7 @@
 
 / {
 	model = "Marvell 98DX4251 SoC";
-	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
 	cpus {
 		cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index 605d855b0147..f624894c2ab6 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -58,7 +58,7 @@
 
 / {
 	model = "Marvell Bobcat2 Evaluation Board";
-	compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 4e07cb6ed800..06fce35d7491 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -58,7 +58,7 @@
 
 / {
 	model = "DB-XC3-24G4XG";
-	compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
-- 
2.11.0.24.ge6920cf

[PATCH v3 4/6] ARM: dts: mvebu: Add binding for mv98dx3236-soc-id

[Chris Packham]

The DFX server on the 98dx3236 and compatible SoCs has an ID register.
Add documentation and a binding for this.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v3:
    - new, split from driver

 .../devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt  | 14 ++++++++++++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  |  5 +++++
 2 files changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt b/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
new file mode 100644
index 000000000000..ed08cb126a83
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
@@ -0,0 +1,14 @@
+Marvell 98dx3236 SoC ID
+---------------------------------------------------------------
+
+Required properties:
+
+- compatible: Should be "marvell,mv98dx3236-soc-id".
+
+- reg: should be the register base and length as documented in the
+  datasheet for the Device ID Status
+
+soc-id@f8244 {
+	compatible = "marvell,mv98dx3236-soc-id";
+	reg = <0xf8244 0x4>;
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 5e7245524d46..6b81f7363d53 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -264,6 +264,11 @@
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
+			soc-id@f8244 {
+				compatible = "marvell,mv98dx3236-soc-id";
+				reg = <0xf8244 0x4>;
+			};
+
 			dfx_coredivclk: corediv-clock@f8268 {
 				compatible = "marvell,mv98dx3236-corediv-clock";
 				reg = <0xf8268 0xc>;
-- 
2.11.0.24.ge6920cf

Re: [PATCH v3 4/6] ARM: dts: mvebu: Add binding for mv98dx3236-soc-id

[Rob Herring]

On Thu, Feb 16, 2017 at 09:50:38PM +1300, Chris Packham wrote:
> The DFX server on the 98dx3236 and compatible SoCs has an ID register.
> Add documentation and a binding for this.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> 
> Notes:
>     Changes in v3:
>     - new, split from driver
> 
>  .../devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt  | 14 ++++++++++++++
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  |  5 +++++
>  2 files changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

[Chris Packham]

The DFX server on the 98dx3236 and compatible SoCs has an ID register
that provides revision information that the PCI based ID register
doesn't have. Use this if it's available.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - none
    Changes in v3:
    - split from dts changes

 arch/arm/mach-mvebu/mvebu-soc-id.c | 43 +++++++++++++++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index a99434bcee84..b4c94a57f358 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -34,6 +34,9 @@
 #define SOC_ID_MASK	    0xFFFF0000
 #define SOC_REV_MASK	    0xFF
 
+#define MV98DX3236_DEV_ID_MASK	0xFF00
+#define MV98DX3236_REV_MASK	0xF
+
 static u32 soc_dev_id;
 static u32 soc_rev;
 static bool is_id_valid;
@@ -45,6 +48,11 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
 	{},
 };
 
+static const struct of_device_id mvebu_mv98dx3236_of_match_table[] = {
+	{ .compatible = "marvell,mv98dx3236-soc-id", },
+	{},
+};
+
 int mvebu_get_soc_id(u32 *dev, u32 *rev)
 {
 	if (is_id_valid) {
@@ -131,15 +139,44 @@ static int __init get_soc_id_by_pci(void)
 	return ret;
 }
 
+static int __init mvebu_dfx_get_soc_id(u32 *dev, u32 *rev)
+{
+	struct device_node *np;
+	void __iomem *base;
+
+	np = of_find_matching_node(NULL, mvebu_mv98dx3236_of_match_table);
+	if (!np)
+		return -ENODEV;
+
+	base = of_iomap(np, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	/* SoC ID */
+	*dev = (readl(base) >> 12) & MV98DX3236_DEV_ID_MASK;
+	/* SoC revision */
+	*rev = (readl(base) >> 28) & MV98DX3236_REV_MASK;
+
+	iounmap(base);
+	of_node_put(np);
+
+	return 0;
+}
+
 static int __init mvebu_soc_id_init(void)
 {
 
 	/*
-	 * First try to get the ID and the revision by the system
-	 * register and use PCI registers only if it is not possible
+	 * First try to get the ID and the revision by from system controller
+	 * register, then try the DFX register (if applicable), finally read it
+	 * from PCI registers.
 	 */
-	if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev)) {
+	if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev))
+		is_id_valid = true;
+	else if (!mvebu_dfx_get_soc_id(&soc_dev_id, &soc_rev))
 		is_id_valid = true;
+
+	if (is_id_valid) {
 		pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
 		return 0;
 	}
-- 
2.11.0.24.ge6920cf

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

[Arnd Bergmann]

On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
> The DFX server on the 98dx3236 and compatible SoCs has an ID register
> that provides revision information that the PCI based ID register
> doesn't have. Use this if it's available.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> 

How about putting this new code into a separate driver in
drivers/soc/? I don't think you need the early probing we have
here, and not that much is shared otherwise.

	Arnd

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

[Chris Packham]

Hi Arnd,
On 17/02/17 02:28, Arnd Bergmann wrote:
> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
>> The DFX server on the 98dx3236 and compatible SoCs has an ID register
>> that provides revision information that the PCI based ID register
>> doesn't have. Use this if it's available.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>
>
> How about putting this new code into a separate driver in
> drivers/soc/? I don't think you need the early probing we have
> here, and not that much is shared otherwise.
>

Not putting it there means we'll get the pci fall-back behaviour which 
will result in a incorrect rev value. Having said that no callers of 
mvebu_get_soc_id() currently care about these specific SoCs so not 
having the right rev is not an issue at the moment.

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

[Arnd Bergmann]

On Fri, Feb 17, 2017 at 5:22 AM, Chris Packham
<Chris.Packham@alliedtelesis.co.nz> wrote:
> Hi Arnd,
> On 17/02/17 02:28, Arnd Bergmann wrote:
>> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
>>> The DFX server on the 98dx3236 and compatible SoCs has an ID register
>>> that provides revision information that the PCI based ID register
>>> doesn't have. Use this if it's available.
>>>
>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>
>>
>> How about putting this new code into a separate driver in
>> drivers/soc/? I don't think you need the early probing we have
>> here, and not that much is shared otherwise.
>>
>
> Not putting it there means we'll get the pci fall-back behaviour which
> will result in a incorrect rev value. Having said that no callers of
> mvebu_get_soc_id() currently care about these specific SoCs so not
> having the right rev is not an issue at the moment.

We should still care about incorrect IDs as they are shown to user space,
which could start relying on it in theory.

However, the PCI ID should only be used on chips that have a PCI
host with an ID known to be correct, so maybe we can restrict
get_soc_id_by_pci() in a way that the mvebu_pcie_of_match_table
matching does not trigger on chips on which we don't want it to.

     Arnd

Re: [PATCH v3 5/6] ARM: mvebu: Add driver for mv98dx3236-soc-id

[Chris Packham]

On 18/02/17 05:17, Arnd Bergmann wrote:
> On Fri, Feb 17, 2017 at 5:22 AM, Chris Packham
> <Chris.Packham@alliedtelesis.co.nz> wrote:
>> Hi Arnd,
>> On 17/02/17 02:28, Arnd Bergmann wrote:
>>> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
>>>> The DFX server on the 98dx3236 and compatible SoCs has an ID register
>>>> that provides revision information that the PCI based ID register
>>>> doesn't have. Use this if it's available.
>>>>
>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>>
>>>
>>> How about putting this new code into a separate driver in
>>> drivers/soc/? I don't think you need the early probing we have
>>> here, and not that much is shared otherwise.
>>>
>>
>> Not putting it there means we'll get the pci fall-back behaviour which
>> will result in a incorrect rev value. Having said that no callers of
>> mvebu_get_soc_id() currently care about these specific SoCs so not
>> having the right rev is not an issue at the moment.
>
> We should still care about incorrect IDs as they are shown to user space,
> which could start relying on it in theory.
>
> However, the PCI ID should only be used on chips that have a PCI
> host with an ID known to be correct, so maybe we can restrict
> get_soc_id_by_pci() in a way that the mvebu_pcie_of_match_table
> matching does not trigger on chips on which we don't want it to.
>

I think we'd need to add some kind of soc-id-from-pci node to indicate 
devices where the best ID is from the PCI registers. We'd also need to 
worry about backwards compatibility etc.

For now since nothing is relying on the rev and the SoC ID is correct 
coming from the PCI registers I'm happy to sit on this patch until a 
need to get the rev arises.

[PATCH v3 6/6] ARM: dts: mvebu: Move mv98dx3236 clock bindings

[Chris Packham]

Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.

Moving the binding to the DFX block enables support for different clock
strapping options in hardware.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support"
    Changes in v3:
    - Clarify why the old location was wrong (but worked).

 .../devicetree/bindings/clock/mvebu-core-clock.txt         |  7 +++++++
 .../devicetree/bindings/clock/mvebu-gated-clock.txt        | 11 +++++++++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  | 14 +++++++-------
 3 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index eb985a633d59..796c260c183d 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
  4 = dclk    (SDRAM Interface Clock)
  5 = refclk  (Reference Clock)
 
+The following is a list of provided IDs and clock names on 98dx3236:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = ddrclk   (DDR clock)
+ 3 = mpll    (MPLL Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -49,6 +55,7 @@ Required properties:
 	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
 	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
 	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
+	"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 5142efc8099d..de562da2ae77 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -119,6 +119,16 @@ ID	Clock	Peripheral
 29	sata1lnk
 30	sata1	SATA Host 1
 
+The following is a list of provided IDs for 98dx3236:
+ID	Clock	Peripheral
+-----------------------------------
+3	ge1	Gigabit Ethernet 1
+4	ge0	Gigabit Ethernet 0
+5	pex0	PCIe Cntrl 0
+17	sdio	SDHCI Host
+18	usb0	USB Host 0
+22	xor0	XOR DMA 0
+
 The following is a list of provided IDs for Dove:
 ID	Clock	Peripheral
 -----------------------------------
@@ -169,6 +179,7 @@ Required properties:
 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
+	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
 	"marvell,dove-gating-clock" - for Dove SoC clock gating
 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
 - reg : shall be the register address of the Clock Gating Control register
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 6b81f7363d53..fe60a751c786 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -176,18 +176,12 @@
 			};
 
 			gateclk: clock-gating-control@18220 {
-				compatible = "marvell,armada-xp-gating-clock";
+				compatible = "marvell,mv98dx3236-gating-clock";
 				reg = <0x18220 0x4>;
 				clocks = <&coreclk 0>;
 				#clock-cells = <1>;
 			};
 
-			coreclk: mvebu-sar@18230 {
-				compatible = "marvell,mv98dx3236-core-clock";
-				reg = <0x18230 0x08>;
-				#clock-cells = <1>;
-			};
-
 			cpuclk: clock-complex@18700 {
 				#clock-cells = <1>;
 				compatible = "marvell,mv98dx3236-cpu-clock";
@@ -264,6 +258,12 @@
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
+			coreclk: mvebu-sar@f8204 {
+				compatible = "marvell,mv98dx3236-core-clock";
+				reg = <0xf8204 0x4>;
+				#clock-cells = <1>;
+			};
+
 			soc-id@f8244 {
 				compatible = "marvell,mv98dx3236-soc-id";
 				reg = <0xf8244 0x4>;
-- 
2.11.0.24.ge6920cf

Re: [PATCH v3 6/6] ARM: dts: mvebu: Move mv98dx3236 clock bindings

[Rob Herring]

On Thu, Feb 16, 2017 at 09:50:40PM +1300, Chris Packham wrote:
> Previously the coreclk binding for the 98dx3236 SoC was inherited from
> the armada-370/xp. This block is present in as much as it is possible to
> read from the register location without causing any harm. However the
> actual sampled at reset values are reflected in the DFX block.
> 
> Moving the binding to the DFX block enables support for different clock
> strapping options in hardware.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> 
> Notes:
>     Changes in v2:
>     - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support"
>     Changes in v3:
>     - Clarify why the old location was wrong (but worked).
> 
>  .../devicetree/bindings/clock/mvebu-core-clock.txt         |  7 +++++++
>  .../devicetree/bindings/clock/mvebu-gated-clock.txt        | 11 +++++++++++
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  | 14 +++++++-------
>  3 files changed, 25 insertions(+), 7 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 0/6] Updates for Marvell Switch SoCs

[Gregory CLEMENT]

Hi Chris,
 
 On jeu., févr. 16 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:

> Shortly after I posted my last series I got access to a more recent
> Marvell SDK which had some device tree support for the switch SoCs I'd
> been wanting. It was still based on an older kernel but it was a huge
> improvement over what came before.
>
> Patch 1/6 is a typo I noticed after my initial series was applied.
>
> Patch 2/6 is a bit of a cleanup. I did initially struggle with how to
> access individual parts of the DFX block as well as retaining a handle on
> the entire thing for the switch driver to use.
>
> Patch 3/6 is a re-jig of the dtsi files which is needed by 5/6. This is
> required because I need to use the coreclk label on a different node. It
> also means I don't have to disable nodes for blocks that only exist on
> the Armada-XP.
>
> Patch 4/6, 5/6 are split from the previous versions.
>
> Patch 6/6 is the device tree portion of a change already in clk-next.


I applied patches 2, 3 and 6 on mvebu/dt with the acked-by from Rob when
he gave it.

Patch 1 is already part of 4.11-rc1.

For patch 4 and 5 I understand that either we don't need it or it should
be a updated version so I skipped them.

Thanks,

Gregory

>
> Chris Packham (6):
>   ARM: dts: Fix typo in armada-xp-98dx4251
>     Changes in v2
>     - new
>     Changes in v3:
>     - none
>   ARM: dts: armada-xp-98dx3236: combine dfx server nodes
>     Changes in v2:
>     - none
>     Changes in v3:
>     - none
>   ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
>     Changes in v2:
>     - Update root compatible strings in armada-xp-98dx3336.dtsi,
>       armada-xp-98dx4251.dtsi, armada-xp-db-dxbc2.dts and
>       armada-xp-db-xc3-24g4xg.dts
>     Changes in v3:
>     - none
>   ARM: dts: mvebu: Add binding for mv98dx3236-soc-id
>     Changes in v3:
>     - new, split from driver
>   ARM: mvebu: Add driver for mv98dx3236-soc-id
>     Changes in v2:
>     - none
>     Changes in v3:
>     - split from dts changes
>   ARM: dts: mvebu: Move mv98dx3236 clock bindings
>     Changes in v2:
>     - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support"
>     Changes in v3:
>     - Clarify why the old location was wrong (but worked).
>
>
>  .../bindings/arm/marvell/mv98dx3236-soc-id.txt     |  14 ++
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>  .../devicetree/bindings/net/marvell,prestera.txt   |  13 +-
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 213 ++++++++++++++++-----
>  arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |   2 +-
>  arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |   2 +-
>  arch/arm/boot/dts/armada-xp-db-dxbc2.dts           |   2 +-
>  arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts      |   2 +-
>  arch/arm/mach-mvebu/mvebu-soc-id.c                 |  43 ++++-
>  10 files changed, 242 insertions(+), 67 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
>
> -- 
> 2.11.0.24.ge6920cf

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v2 0/6] Updates for Marvell Switch SoCs

[Chris Packham]

Hi Gregory,

On 08/03/17 06:10, Gregory CLEMENT wrote:
> Hi Chris,
>
>  On jeu., févr. 16 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
>> Shortly after I posted my last series I got access to a more recent
>> Marvell SDK which had some device tree support for the switch SoCs I'd
>> been wanting. It was still based on an older kernel but it was a huge
>> improvement over what came before.
>>
>> Patch 1/6 is a typo I noticed after my initial series was applied.
>>
>> Patch 2/6 is a bit of a cleanup. I did initially struggle with how to
>> access individual parts of the DFX block as well as retaining a handle on
>> the entire thing for the switch driver to use.
>>
>> Patch 3/6 is a re-jig of the dtsi files which is needed by 5/6. This is
>> required because I need to use the coreclk label on a different node. It
>> also means I don't have to disable nodes for blocks that only exist on
>> the Armada-XP.
>>
>> Patch 4/6, 5/6 are split from the previous versions.
>>
>> Patch 6/6 is the device tree portion of a change already in clk-next.
>
>
> I applied patches 2, 3 and 6 on mvebu/dt with the acked-by from Rob when
> he gave it.
>
> Patch 1 is already part of 4.11-rc1.
>
> For patch 4 and 5 I understand that either we don't need it or it should
> be a updated version so I skipped them.
>

That's correct, thanks.