From: Palmer Dabbelt <palmer@dabbelt.com>
To: linux-arch@vger.kernel.org
To: linux-kernel@vger.kernel.org
To: Arnd Bergmann <arnd@arndb.de>
To: olof@lixom.net
Cc: albert@sifive.com
Cc: patches@groups.riscv.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 14/17] RISC-V: lib files
Date: Tue, 6 Jun 2017 16:00:04 -0700 [thread overview]
Message-ID: <20170606230007.19101-15-palmer@dabbelt.com> (raw)
In-Reply-To: <20170606230007.19101-1-palmer@dabbelt.com>
Most of these files are based off code in GCC, but the delay code is
mostly from ARM.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
---
arch/riscv/lib/Makefile | 5 ++
arch/riscv/lib/delay.c | 107 ++++++++++++++++++++++++++++++++++++++++
arch/riscv/lib/memcpy.S | 98 +++++++++++++++++++++++++++++++++++++
arch/riscv/lib/memset.S | 118 ++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/lib/uaccess.S | 125 +++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/lib/udivdi3.S | 39 +++++++++++++++
6 files changed, 492 insertions(+)
create mode 100644 arch/riscv/lib/Makefile
create mode 100644 arch/riscv/lib/delay.c
create mode 100644 arch/riscv/lib/memcpy.S
create mode 100644 arch/riscv/lib/memset.S
create mode 100644 arch/riscv/lib/uaccess.S
create mode 100644 arch/riscv/lib/udivdi3.S
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
new file mode 100644
index 000000000000..120c38e77a46
--- /dev/null
+++ b/arch/riscv/lib/Makefile
@@ -0,0 +1,5 @@
+lib-y := delay.o memcpy.o memset.o uaccess.o
+
+ifeq ($(CONFIG_64BIT),)
+lib-y += udivdi3.o
+endif
diff --git a/arch/riscv/lib/delay.c b/arch/riscv/lib/delay.c
new file mode 100644
index 000000000000..ceff08a5b762
--- /dev/null
+++ b/arch/riscv/lib/delay.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/param.h>
+#include <linux/timex.h>
+#include <linux/export.h>
+
+/*
+ * This is copies from arch/arm/include/asm/delay.h
+ *
+ * Loop (or tick) based delay:
+ *
+ * loops = loops_per_jiffy * jiffies_per_sec * delay_us / us_per_sec
+ *
+ * where:
+ *
+ * jiffies_per_sec = HZ
+ * us_per_sec = 1000000
+ *
+ * Therefore the constant part is HZ / 1000000 which is a small
+ * fractional number. To make this usable with integer math, we
+ * scale up this constant by 2^31, perform the actual multiplication,
+ * and scale the result back down by 2^31 with a simple shift:
+ *
+ * loops = (loops_per_jiffy * delay_us * UDELAY_MULT) >> 31
+ *
+ * where:
+ *
+ * UDELAY_MULT = 2^31 * HZ / 1000000
+ * = (2^31 / 1000000) * HZ
+ * = 2147.483648 * HZ
+ * = 2147 * HZ + 483648 * HZ / 1000000
+ *
+ * 31 is the biggest scale shift value that won't overflow 32 bits for
+ * delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000.
+ */
+#define MAX_UDELAY_US 2000
+#define MAX_UDELAY_HZ 1000
+#define UDELAY_MULT (2147UL * HZ + 483648UL * HZ / 1000000UL)
+#define UDELAY_SHIFT 31
+
+#if HZ > MAX_UDELAY_HZ
+#error "HZ > MAX_UDELAY_HZ"
+#endif
+
+/* RISC-V supports both UDELAY and NDELAY. This is largely the same as above,
+ * but with different constants. I added 10 bits to the shift to get this, but
+ * the result is that I need a 64-bit multiply, which is slow on 32-bit
+ * platforms.
+ *
+ * NDELAY_MULT = 2^41 * HZ / 1000000000
+ * = (2^41 / 1000000000) * HZ
+ * = 2199.02325555 * HZ
+ * = 2199 * HZ + 23255550 * HZ / 1000000000
+ *
+ * The maximum here is to avoid 64-bit overflow, but it isn't checked as it
+ * won't happen.
+ */
+#define MAX_NDELAY_NS (1ULL << 42)
+#define MAX_NDELAY_HZ MAX_UDELAY_HZ
+#define NDELAY_MULT ((unsigned long long)(2199ULL * HZ + 23255550ULL * HZ / 1000000000ULL))
+#define NDELAY_SHIFT 41
+
+#if HZ > MAX_NDELAY_HZ
+#error "HZ > MAX_NDELAY_HZ"
+#endif
+
+void __delay(unsigned long cycles)
+{
+ u64 t0 = get_cycles();
+
+ while ((unsigned long)(get_cycles() - t0) < cycles)
+ cpu_relax();
+}
+
+void udelay(unsigned long usecs)
+{
+ unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
+
+ if (usecs > MAX_UDELAY_US) {
+ __delay((u64)usecs * riscv_timebase / 1000000ULL);
+ return;
+ }
+
+ __delay(ucycles >> UDELAY_SHIFT);
+}
+EXPORT_SYMBOL(udelay);
+
+void ndelay(unsigned long nsecs)
+{
+ /* This doesn't bother checking for overflow, as it won't happen (it's
+ * an hour) of delay. */
+ unsigned long long ncycles = nsecs * lpj_fine * NDELAY_MULT;
+ __delay(ncycles >> NDELAY_SHIFT);
+}
+EXPORT_SYMBOL(ndelay);
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
new file mode 100644
index 000000000000..5b576cf041eb
--- /dev/null
+++ b/arch/riscv/lib/memcpy.S
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memcpy(void *, const void *, size_t) */
+ENTRY(memcpy)
+ move t6, a0 /* Preserve return value */
+
+ /* Defer to byte-oriented copy for small sizes */
+ sltiu a3, a2, 128
+ bnez a3, 4f
+ /* Use word-oriented copy only if low-order bits match */
+ andi a3, t6, SZREG-1
+ andi a4, a1, SZREG-1
+ bne a3, a4, 4f
+
+ beqz a3, 2f /* Skip if already aligned */
+ /* Round to nearest double word-aligned address
+ greater than or equal to start address */
+ andi a3, a1, ~(SZREG-1)
+ addi a3, a3, SZREG
+ /* Handle initial misalignment */
+ sub a4, a3, a1
+1:
+ lb a5, 0(a1)
+ addi a1, a1, 1
+ sb a5, 0(t6)
+ addi t6, t6, 1
+ bltu a1, a3, 1b
+ sub a2, a2, a4 /* Update count */
+
+2:
+ andi a4, a2, ~((16*SZREG)-1)
+ beqz a4, 4f
+ add a3, a1, a4
+3:
+ REG_L a4, 0(a1)
+ REG_L a5, SZREG(a1)
+ REG_L a6, 2*SZREG(a1)
+ REG_L a7, 3*SZREG(a1)
+ REG_L t0, 4*SZREG(a1)
+ REG_L t1, 5*SZREG(a1)
+ REG_L t2, 6*SZREG(a1)
+ REG_L t3, 7*SZREG(a1)
+ REG_L t4, 8*SZREG(a1)
+ REG_L t5, 9*SZREG(a1)
+ REG_S a4, 0(t6)
+ REG_S a5, SZREG(t6)
+ REG_S a6, 2*SZREG(t6)
+ REG_S a7, 3*SZREG(t6)
+ REG_S t0, 4*SZREG(t6)
+ REG_S t1, 5*SZREG(t6)
+ REG_S t2, 6*SZREG(t6)
+ REG_S t3, 7*SZREG(t6)
+ REG_S t4, 8*SZREG(t6)
+ REG_S t5, 9*SZREG(t6)
+ REG_L a4, 10*SZREG(a1)
+ REG_L a5, 11*SZREG(a1)
+ REG_L a6, 12*SZREG(a1)
+ REG_L a7, 13*SZREG(a1)
+ REG_L t0, 14*SZREG(a1)
+ REG_L t1, 15*SZREG(a1)
+ addi a1, a1, 16*SZREG
+ REG_S a4, 10*SZREG(t6)
+ REG_S a5, 11*SZREG(t6)
+ REG_S a6, 12*SZREG(t6)
+ REG_S a7, 13*SZREG(t6)
+ REG_S t0, 14*SZREG(t6)
+ REG_S t1, 15*SZREG(t6)
+ addi t6, t6, 16*SZREG
+ bltu a1, a3, 3b
+ andi a2, a2, (16*SZREG)-1 /* Update count */
+
+4:
+ /* Handle trailing misalignment */
+ beqz a2, 6f
+ add a3, a1, a2
+5:
+ lb a4, 0(a1)
+ addi a1, a1, 1
+ sb a4, 0(t6)
+ addi t6, t6, 1
+ bltu a1, a3, 5b
+6:
+ ret
+END(memcpy)
diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S
new file mode 100644
index 000000000000..d83c38099653
--- /dev/null
+++ b/arch/riscv/lib/memset.S
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memset(void *, int, size_t) */
+ENTRY(memset)
+ move t0, a0 /* Preserve return value */
+
+ /* Defer to byte-oriented fill for small sizes */
+ sltiu a3, a2, 16
+ bnez a3, 4f
+
+ /* Round to nearest XLEN-aligned address
+ greater than or equal to start address */
+ addi a3, t0, SZREG-1
+ andi a3, a3, ~(SZREG-1)
+ beq a3, t0, 2f /* Skip if already aligned */
+ /* Handle initial misalignment */
+ sub a4, a3, t0
+1:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 1b
+ sub a2, a2, a4 /* Update count */
+
+2: /* Duff's device with 32 XLEN stores per iteration */
+ /* Broadcast value into all bytes */
+ andi a1, a1, 0xff
+ slli a3, a1, 8
+ or a1, a3, a1
+ slli a3, a1, 16
+ or a1, a3, a1
+#ifdef CONFIG_64BIT
+ slli a3, a1, 32
+ or a1, a3, a1
+#endif
+
+ /* Calculate end address */
+ andi a4, a2, ~(SZREG-1)
+ add a3, t0, a4
+
+ andi a4, a4, 31*SZREG /* Calculate remainder */
+ beqz a4, 3f /* Shortcut if no remainder */
+ neg a4, a4
+ addi a4, a4, 32*SZREG /* Calculate initial offset */
+
+ /* Adjust start address with offset */
+ sub t0, t0, a4
+
+ /* Jump into loop body */
+ /* Assumes 32-bit instruction lengths */
+ la a5, 3f
+#ifdef CONFIG_64BIT
+ srli a4, a4, 1
+#endif
+ add a5, a5, a4
+ jr a5
+3:
+ REG_S a1, 0(t0)
+ REG_S a1, SZREG(t0)
+ REG_S a1, 2*SZREG(t0)
+ REG_S a1, 3*SZREG(t0)
+ REG_S a1, 4*SZREG(t0)
+ REG_S a1, 5*SZREG(t0)
+ REG_S a1, 6*SZREG(t0)
+ REG_S a1, 7*SZREG(t0)
+ REG_S a1, 8*SZREG(t0)
+ REG_S a1, 9*SZREG(t0)
+ REG_S a1, 10*SZREG(t0)
+ REG_S a1, 11*SZREG(t0)
+ REG_S a1, 12*SZREG(t0)
+ REG_S a1, 13*SZREG(t0)
+ REG_S a1, 14*SZREG(t0)
+ REG_S a1, 15*SZREG(t0)
+ REG_S a1, 16*SZREG(t0)
+ REG_S a1, 17*SZREG(t0)
+ REG_S a1, 18*SZREG(t0)
+ REG_S a1, 19*SZREG(t0)
+ REG_S a1, 20*SZREG(t0)
+ REG_S a1, 21*SZREG(t0)
+ REG_S a1, 22*SZREG(t0)
+ REG_S a1, 23*SZREG(t0)
+ REG_S a1, 24*SZREG(t0)
+ REG_S a1, 25*SZREG(t0)
+ REG_S a1, 26*SZREG(t0)
+ REG_S a1, 27*SZREG(t0)
+ REG_S a1, 28*SZREG(t0)
+ REG_S a1, 29*SZREG(t0)
+ REG_S a1, 30*SZREG(t0)
+ REG_S a1, 31*SZREG(t0)
+ addi t0, t0, 32*SZREG
+ bltu t0, a3, 3b
+ andi a2, a2, SZREG-1 /* Update count */
+
+4:
+ /* Handle trailing misalignment */
+ beqz a2, 6f
+ add a3, t0, a2
+5:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 5b
+6:
+ ret
+END(memset)
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
new file mode 100644
index 000000000000..cba994696aff
--- /dev/null
+++ b/arch/riscv/lib/uaccess.S
@@ -0,0 +1,125 @@
+#include <linux/linkage.h>
+#include <asm/asm.h>
+#include <asm/csr.h>
+
+ .altmacro
+ .macro fixup op reg addr lbl
+ LOCAL _epc
+_epc:
+ \op \reg, \addr
+ .section __ex_table,"a"
+ .balign RISCV_SZPTR
+ RISCV_PTR _epc, \lbl
+ .previous
+ .endm
+
+ENTRY(__copy_user)
+
+#ifdef CONFIG_RV_PUM
+ /* Enable access to user memory */
+ li t6, SR_SUM
+ csrs sstatus, t6
+#endif
+
+ add a3, a1, a2
+ /* Use word-oriented copy only if low-order bits match */
+ andi t0, a0, SZREG-1
+ andi t1, a1, SZREG-1
+ bne t0, t1, 2f
+
+ addi t0, a1, SZREG-1
+ andi t1, a3, ~(SZREG-1)
+ andi t0, t0, ~(SZREG-1)
+ /* a3: terminal address of source region
+ * t0: lowest XLEN-aligned address in source
+ * t1: highest XLEN-aligned address in source
+ */
+ bgeu t0, t1, 2f
+ bltu a1, t0, 4f
+1:
+ fixup REG_L, t2, (a1), 10f
+ fixup REG_S, t2, (a0), 10f
+ addi a1, a1, SZREG
+ addi a0, a0, SZREG
+ bltu a1, t1, 1b
+2:
+ bltu a1, a3, 5f
+
+3:
+#ifdef CONFIG_RV_PUM
+ /* Disable access to user memory */
+ csrc sstatus, t6
+#endif
+ li a0, 0
+ ret
+4: /* Edge case: unalignment */
+ fixup lbu, t2, (a1), 10f
+ fixup sb, t2, (a0), 10f
+ addi a1, a1, 1
+ addi a0, a0, 1
+ bltu a1, t0, 4b
+ j 1b
+5: /* Edge case: remainder */
+ fixup lbu, t2, (a1), 10f
+ fixup sb, t2, (a0), 10f
+ addi a1, a1, 1
+ addi a0, a0, 1
+ bltu a1, a3, 5b
+ j 3b
+ENDPROC(__copy_user)
+
+
+ENTRY(__clear_user)
+
+#ifdef CONFIG_RV_PUM
+ /* Enable access to user memory */
+ li t6, SR_SUM
+ csrs sstatus, t6
+#endif
+
+ add a3, a0, a1
+ addi t0, a0, SZREG-1
+ andi t1, a3, ~(SZREG-1)
+ andi t0, t0, ~(SZREG-1)
+ /* a3: terminal address of target region
+ * t0: lowest doubleword-aligned address in target region
+ * t1: highest doubleword-aligned address in target region
+ */
+ bgeu t0, t1, 2f
+ bltu a0, t0, 4f
+1:
+ fixup REG_S, zero, (a0), 10f
+ addi a0, a0, SZREG
+ bltu a0, t1, 1b
+2:
+ bltu a0, a3, 5f
+
+3:
+#ifdef CONFIG_RV_PUM
+ /* Disable access to user memory */
+ csrc sstatus, t6
+#endif
+ li a0, 0
+ ret
+4: /* Edge case: unalignment */
+ fixup sb, zero, (a0), 10f
+ addi a0, a0, 1
+ bltu a0, t0, 4b
+ j 1b
+5: /* Edge case: remainder */
+ fixup sb, zero, (a0), 10f
+ addi a0, a0, 1
+ bltu a0, a3, 5b
+ j 3b
+ENDPROC(__clear_user)
+
+ .section .fixup,"ax"
+ .balign 4
+10:
+#ifdef CONFIG_RV_PUM
+ /* Disable access to user memory */
+ csrs sstatus, t6
+#endif
+ sub a0, a3, a0
+ ret
+ .previous
diff --git a/arch/riscv/lib/udivdi3.S b/arch/riscv/lib/udivdi3.S
new file mode 100644
index 000000000000..d8a7a1d03615
--- /dev/null
+++ b/arch/riscv/lib/udivdi3.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016-2017 Free Software Foundation, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ .globl __udivdi3
+__udivdi3:
+ mv a2, a1
+ mv a1, a0
+ li a0, -1
+ beqz a2, .L5
+ li a3, 1
+ bgeu a2, a1, .L2
+.L1:
+ blez a2, .L2
+ slli a2, a2, 1
+ slli a3, a3, 1
+ bgtu a1, a2, .L1
+.L2:
+ li a0, 0
+.L3:
+ bltu a1, a2, .L4
+ sub a1, a1, a2
+ or a0, a0, a3
+.L4:
+ srli a3, a3, 1
+ srli a2, a2, 1
+ bnez a3, .L3
+.L5:
+ ret
+
--
2.13.0
next prev parent reply other threads:[~2017-06-06 23:02 UTC|newest]
Thread overview: 200+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-23 0:41 RISC-V Linux Port v1 Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64} Palmer Dabbelt
2017-05-23 11:30 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 10:50 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 17:39 ` Karsten Merker
2017-06-06 17:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt
2017-05-23 1:27 ` Olof Johansson
2017-05-23 1:31 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 5:16 ` [patches] " Olof Johansson
2017-05-23 21:07 ` Benjamin Herrenschmidt
2017-05-23 5:23 ` Olof Johansson
2017-05-23 15:29 ` Palmer Dabbelt
2017-05-23 10:51 ` Geert Uytterhoeven
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-23 11:46 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 11:17 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:20 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 3/7] RISC-V: Device Tree Documentation Palmer Dabbelt
2017-05-23 12:03 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 4/7] RISC-V: arch/riscv/include Palmer Dabbelt
2017-05-23 12:55 ` Arnd Bergmann
2017-05-23 21:23 ` Benjamin Herrenschmidt
2017-06-03 2:00 ` Palmer Dabbelt
2017-06-01 0:56 ` Palmer Dabbelt
2017-06-01 9:00 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 8:54 ` Arnd Bergmann
2017-06-06 19:07 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt
2017-05-23 10:47 ` Geert Uytterhoeven
2017-05-23 22:07 ` Palmer Dabbelt
2017-05-23 11:19 ` Arnd Bergmann
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-26 9:06 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:31 ` Arnd Bergmann
2017-06-06 20:53 ` Palmer Dabbelt
2017-06-07 7:35 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 6/7] RISC-V: arch/riscv/kernel Palmer Dabbelt
2017-05-23 2:11 ` Olof Johansson
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-25 19:51 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:03 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 13:35 ` Arnd Bergmann
2017-06-02 23:56 ` Palmer Dabbelt
2017-06-06 9:01 ` Arnd Bergmann
2017-06-06 20:37 ` Palmer Dabbelt
2017-05-25 17:05 ` Pavel Machek
2017-06-03 3:32 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 7/7] RISC-V: arch/riscv/mm Palmer Dabbelt
2017-05-23 1:28 ` Randy Dunlap
2017-05-23 2:17 ` Olof Johansson
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 1:16 ` RISC-V Linux Port v1 Olof Johansson
2017-05-23 1:25 ` Randy Dunlap
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 6:45 ` Tobias Klauser
2017-05-23 15:44 ` Palmer Dabbelt
2017-05-23 2:16 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-06-06 22:59 ` RISC-V Linux Port v2 Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 01/17] drivers: support PCIe in RISCV Palmer Dabbelt
2017-06-07 7:17 ` Geert Uytterhoeven
2017-06-07 14:25 ` Christoph Hellwig
[not found] ` <CAMgXwTjXZ5dsxmJ2FyWhCRWo-3nyvKUDfhfV0nNC+oakF=AEsA@mail.gmail.com>
2017-06-07 17:40 ` Olof Johansson
2017-06-23 21:47 ` [patches] " Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt Palmer Dabbelt
2017-06-07 7:18 ` Geert Uytterhoeven
2017-06-07 9:24 ` Marc Zyngier
2017-06-07 19:03 ` Wesley Terpstra
2017-06-06 22:59 ` [PATCH 03/17] base: fix order of OF initialization Palmer Dabbelt
2017-06-07 7:07 ` Geert Uytterhoeven
2017-06-07 9:35 ` Mark Rutland
2017-06-07 18:39 ` Wesley Terpstra
2017-06-07 21:10 ` Benjamin Herrenschmidt
2017-06-08 3:49 ` Frank Rowand
2017-06-08 9:05 ` Mark Rutland
2017-06-09 0:37 ` Frank Rowand
2017-06-06 22:59 ` [PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 9:20 ` Will Deacon
2017-06-06 22:59 ` [PATCH 05/17] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 8:01 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-08 8:12 ` Christoph Hellwig
2017-06-08 8:35 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 07/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Palmer Dabbelt
2017-06-07 7:11 ` Geert Uytterhoeven
2017-06-07 10:13 ` Mark Rutland
2017-06-07 18:57 ` Wesley Terpstra
2017-06-07 19:57 ` Rob Herring
2017-06-07 20:31 ` Wesley Terpstra
2017-06-08 10:52 ` Mark Rutland
2017-06-09 21:46 ` Wesley Terpstra
2017-06-09 21:58 ` Wesley Terpstra
2017-06-19 14:30 ` Mark Rutland
2017-06-07 22:27 ` Luis R. Rodriguez
2017-06-06 22:59 ` [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Palmer Dabbelt
2017-06-07 7:12 ` Geert Uytterhoeven
2017-06-07 7:25 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-06-07 9:43 ` Marc Zyngier
2017-06-24 2:02 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 10/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-06-07 7:13 ` Geert Uytterhoeven
2017-06-07 7:55 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-07 10:52 ` Marc Zyngier
2017-06-09 13:47 ` Will Deacon
2017-06-27 1:09 ` Palmer Dabbelt
2017-06-25 20:49 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-06-07 7:14 ` Geert Uytterhoeven
2017-06-06 23:00 ` [PATCH 12/17] tty: New RISC-V SBI Console Driver Palmer Dabbelt
2017-06-07 7:15 ` Geert Uytterhoeven
2017-06-07 7:58 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 13/17] RISC-V: Add include subdirectory Palmer Dabbelt
2017-06-07 8:12 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-24 15:42 ` Benjamin Herrenschmidt
2017-06-24 21:32 ` [patches] " Palmer Dabbelt
2017-06-25 3:01 ` Benjamin Herrenschmidt
2017-06-07 11:54 ` Peter Zijlstra
2017-06-07 12:25 ` Peter Zijlstra
2017-06-07 12:06 ` Peter Zijlstra
2017-06-07 12:18 ` Peter Zijlstra
2017-06-07 12:36 ` Peter Zijlstra
2017-06-07 12:58 ` Peter Zijlstra
2017-06-07 13:16 ` Will Deacon
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-27 0:07 ` Daniel Lustig
2017-06-27 8:48 ` Will Deacon
2017-06-07 16:35 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-07 12:42 ` Peter Zijlstra
2017-06-07 13:17 ` Peter Zijlstra
2017-06-09 8:16 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-06 23:00 ` Palmer Dabbelt [this message]
2017-06-06 23:00 ` [PATCH 15/17] RISC-V: Add mm subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 16/17] RISC-V: Add kernel subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 17/17] RISC-V: Makefile and Kconfig Palmer Dabbelt
2017-06-07 9:23 ` RISC-V Linux Port v2 Will Deacon
2017-06-07 21:54 ` Palmer Dabbelt
2017-06-08 10:26 ` Will Deacon
2017-06-08 18:16 ` Palmer Dabbelt
2017-06-28 18:55 ` RISC-V Linux Port v3 Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt
2017-06-29 9:44 ` Geert Uytterhoeven
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt
2017-06-28 23:32 ` James Hogan
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-29 8:22 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-06-29 8:39 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-30 7:57 ` Tobias Klauser
2017-06-28 18:55 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt
2017-06-28 23:09 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-06-28 21:49 ` Thomas Gleixner
2017-06-28 21:52 ` Thomas Gleixner
2017-06-29 17:22 ` Palmer Dabbelt
2017-06-28 22:42 ` James Hogan
2017-06-29 21:42 ` Palmer Dabbelt
2017-07-03 23:06 ` James Hogan
2017-07-05 16:49 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt
2017-06-28 21:05 ` Karsten Merker
2017-06-28 21:13 ` Palmer Dabbelt
2017-06-28 21:25 ` James Hogan
2017-06-29 16:29 ` Palmer Dabbelt
2017-06-28 22:54 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-07 7:29 ` RISC-V Linux Port v2 David Howells
2017-06-07 21:54 ` Palmer Dabbelt
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