From: Palmer Dabbelt <palmer@dabbelt.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Olof Johansson <olof@lixom.net>
Cc: albert@sifive.com
Cc: patches@groups.riscv.org
Cc: benh@kernel.crashing.org
Subject: Re: [PATCH 13/17] RISC-V: Add include subdirectory
Date: Fri, 23 Jun 2017 19:01:59 -0700 (PDT) [thread overview]
Message-ID: <mhng-002dc1e3-4bff-43d8-b58c-a105e5643aea@palmer-si-x1c4> (raw)
In-Reply-To: <CAK8P3a3LVGTrBxc+GD2gFHKg-YcZ40+z0SJAuFXadqLFDrE=DQ@mail.gmail.com>
On Wed, 07 Jun 2017 01:12:00 PDT (-0700), Arnd Bergmann wrote:
> On Wed, Jun 7, 2017 at 1:00 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> This patch adds the include files for the RISC-V port. These are mostly
>> based on the score port, but there are a lot of arm64-based files as
>> well.
>>
>> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
>
> It might be better to split this up into several parts, as the patch
> is longer than
> most people are willing to review at once.
>
> The uapi should definitely be a separate patch, as it includes the parts that
> cannot be changed any more later. memory management (pgtable, mmu,
> uaccess) would be another part to split out, and possibly all the atomics
> in one separate patch (along with spinlocks and bitops).
OK, we'll do this for the v3.
>
>> +
>> +/* IO barriers. These only fence on the IO bits because they're only required
>> + * to order device access. We're defining mmiowb because our AMO instructions
>> + * (which are used to implement locks) don't specify ordering. From Chapter 7
>> + * of v2.2 of the user ISA:
>> + * "The bits order accesses to one of the two address domains, memory or I/O,
>> + * depending on which address domain the atomic instruction is accessing. No
>> + * ordering constraint is implied to accesses to the other domain, and a FENCE
>> + * instruction should be used to order across both domains."
>> + */
>> +
>> +#define __iormb() __asm__ __volatile__ ("fence i,io" : : : "memory");
>> +#define __iowmb() __asm__ __volatile__ ("fence io,o" : : : "memory");
>> +
>> +#define mmiowb() __asm__ __volatile__ ("fence io,io" : : : "memory");
>> +
>> +/*
>> + * Relaxed I/O memory access primitives. These follow the Device memory
>> + * ordering rules but do not guarantee any ordering relative to Normal memory
>> + * accesses.
>> + */
>> +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
>> +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
>> +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
>> +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
>> +
>> +#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
>> +#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
>> +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
>> +#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
>> +
>> +/*
>> + * I/O memory access primitives. Reads are ordered relative to any
>> + * following Normal memory access. Writes are ordered relative to any prior
>> + * Normal memory access.
>> + */
>> +#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
>> +#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
>> +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
>> +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
>> +
>> +#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
>> +#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
>> +#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
>> +#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
>> +
>> +#include <asm-generic/io.h>
>
> These do not yet contain all the changes we discussed: the relaxed operations
> don't seem to be ordered against one another and the regular accessors
> are not ordered against DMA.
Sorry, I must have forgotten to write this -- I just wanted to push out a v3
patch set without the changes to the atomics so everything else could be looked
at. I wanted to just go through the atomics completely and fix them, as I
found a handful of problems (everything was missing the AQ and RL bits, for
example) and figured it would be best to just get them done right.
I think that's not something for after dinner on a Friday, but hopefully I'll
get to it tomorrow morning.
next prev parent reply other threads:[~2017-06-24 2:02 UTC|newest]
Thread overview: 200+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-23 0:41 RISC-V Linux Port v1 Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64} Palmer Dabbelt
2017-05-23 11:30 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 10:50 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 17:39 ` Karsten Merker
2017-06-06 17:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt
2017-05-23 1:27 ` Olof Johansson
2017-05-23 1:31 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 5:16 ` [patches] " Olof Johansson
2017-05-23 21:07 ` Benjamin Herrenschmidt
2017-05-23 5:23 ` Olof Johansson
2017-05-23 15:29 ` Palmer Dabbelt
2017-05-23 10:51 ` Geert Uytterhoeven
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-23 11:46 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 11:17 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:20 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 3/7] RISC-V: Device Tree Documentation Palmer Dabbelt
2017-05-23 12:03 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 4/7] RISC-V: arch/riscv/include Palmer Dabbelt
2017-05-23 12:55 ` Arnd Bergmann
2017-05-23 21:23 ` Benjamin Herrenschmidt
2017-06-03 2:00 ` Palmer Dabbelt
2017-06-01 0:56 ` Palmer Dabbelt
2017-06-01 9:00 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 8:54 ` Arnd Bergmann
2017-06-06 19:07 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt
2017-05-23 10:47 ` Geert Uytterhoeven
2017-05-23 22:07 ` Palmer Dabbelt
2017-05-23 11:19 ` Arnd Bergmann
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-26 9:06 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:31 ` Arnd Bergmann
2017-06-06 20:53 ` Palmer Dabbelt
2017-06-07 7:35 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 6/7] RISC-V: arch/riscv/kernel Palmer Dabbelt
2017-05-23 2:11 ` Olof Johansson
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-25 19:51 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:03 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 13:35 ` Arnd Bergmann
2017-06-02 23:56 ` Palmer Dabbelt
2017-06-06 9:01 ` Arnd Bergmann
2017-06-06 20:37 ` Palmer Dabbelt
2017-05-25 17:05 ` Pavel Machek
2017-06-03 3:32 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 7/7] RISC-V: arch/riscv/mm Palmer Dabbelt
2017-05-23 1:28 ` Randy Dunlap
2017-05-23 2:17 ` Olof Johansson
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 1:16 ` RISC-V Linux Port v1 Olof Johansson
2017-05-23 1:25 ` Randy Dunlap
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 6:45 ` Tobias Klauser
2017-05-23 15:44 ` Palmer Dabbelt
2017-05-23 2:16 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-06-06 22:59 ` RISC-V Linux Port v2 Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 01/17] drivers: support PCIe in RISCV Palmer Dabbelt
2017-06-07 7:17 ` Geert Uytterhoeven
2017-06-07 14:25 ` Christoph Hellwig
[not found] ` <CAMgXwTjXZ5dsxmJ2FyWhCRWo-3nyvKUDfhfV0nNC+oakF=AEsA@mail.gmail.com>
2017-06-07 17:40 ` Olof Johansson
2017-06-23 21:47 ` [patches] " Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt Palmer Dabbelt
2017-06-07 7:18 ` Geert Uytterhoeven
2017-06-07 9:24 ` Marc Zyngier
2017-06-07 19:03 ` Wesley Terpstra
2017-06-06 22:59 ` [PATCH 03/17] base: fix order of OF initialization Palmer Dabbelt
2017-06-07 7:07 ` Geert Uytterhoeven
2017-06-07 9:35 ` Mark Rutland
2017-06-07 18:39 ` Wesley Terpstra
2017-06-07 21:10 ` Benjamin Herrenschmidt
2017-06-08 3:49 ` Frank Rowand
2017-06-08 9:05 ` Mark Rutland
2017-06-09 0:37 ` Frank Rowand
2017-06-06 22:59 ` [PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 9:20 ` Will Deacon
2017-06-06 22:59 ` [PATCH 05/17] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 8:01 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-08 8:12 ` Christoph Hellwig
2017-06-08 8:35 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 07/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Palmer Dabbelt
2017-06-07 7:11 ` Geert Uytterhoeven
2017-06-07 10:13 ` Mark Rutland
2017-06-07 18:57 ` Wesley Terpstra
2017-06-07 19:57 ` Rob Herring
2017-06-07 20:31 ` Wesley Terpstra
2017-06-08 10:52 ` Mark Rutland
2017-06-09 21:46 ` Wesley Terpstra
2017-06-09 21:58 ` Wesley Terpstra
2017-06-19 14:30 ` Mark Rutland
2017-06-07 22:27 ` Luis R. Rodriguez
2017-06-06 22:59 ` [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Palmer Dabbelt
2017-06-07 7:12 ` Geert Uytterhoeven
2017-06-07 7:25 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-06-07 9:43 ` Marc Zyngier
2017-06-24 2:02 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 10/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-06-07 7:13 ` Geert Uytterhoeven
2017-06-07 7:55 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-07 10:52 ` Marc Zyngier
2017-06-09 13:47 ` Will Deacon
2017-06-27 1:09 ` Palmer Dabbelt
2017-06-25 20:49 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-06-07 7:14 ` Geert Uytterhoeven
2017-06-06 23:00 ` [PATCH 12/17] tty: New RISC-V SBI Console Driver Palmer Dabbelt
2017-06-07 7:15 ` Geert Uytterhoeven
2017-06-07 7:58 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 13/17] RISC-V: Add include subdirectory Palmer Dabbelt
2017-06-07 8:12 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt [this message]
2017-06-24 15:42 ` Benjamin Herrenschmidt
2017-06-24 21:32 ` [patches] " Palmer Dabbelt
2017-06-25 3:01 ` Benjamin Herrenschmidt
2017-06-07 11:54 ` Peter Zijlstra
2017-06-07 12:25 ` Peter Zijlstra
2017-06-07 12:06 ` Peter Zijlstra
2017-06-07 12:18 ` Peter Zijlstra
2017-06-07 12:36 ` Peter Zijlstra
2017-06-07 12:58 ` Peter Zijlstra
2017-06-07 13:16 ` Will Deacon
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-27 0:07 ` Daniel Lustig
2017-06-27 8:48 ` Will Deacon
2017-06-07 16:35 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-07 12:42 ` Peter Zijlstra
2017-06-07 13:17 ` Peter Zijlstra
2017-06-09 8:16 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 14/17] RISC-V: lib files Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 15/17] RISC-V: Add mm subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 16/17] RISC-V: Add kernel subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 17/17] RISC-V: Makefile and Kconfig Palmer Dabbelt
2017-06-07 9:23 ` RISC-V Linux Port v2 Will Deacon
2017-06-07 21:54 ` Palmer Dabbelt
2017-06-08 10:26 ` Will Deacon
2017-06-08 18:16 ` Palmer Dabbelt
2017-06-28 18:55 ` RISC-V Linux Port v3 Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt
2017-06-29 9:44 ` Geert Uytterhoeven
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt
2017-06-28 23:32 ` James Hogan
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-29 8:22 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-06-29 8:39 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-30 7:57 ` Tobias Klauser
2017-06-28 18:55 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt
2017-06-28 23:09 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-06-28 21:49 ` Thomas Gleixner
2017-06-28 21:52 ` Thomas Gleixner
2017-06-29 17:22 ` Palmer Dabbelt
2017-06-28 22:42 ` James Hogan
2017-06-29 21:42 ` Palmer Dabbelt
2017-07-03 23:06 ` James Hogan
2017-07-05 16:49 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt
2017-06-28 21:05 ` Karsten Merker
2017-06-28 21:13 ` Palmer Dabbelt
2017-06-28 21:25 ` James Hogan
2017-06-29 16:29 ` Palmer Dabbelt
2017-06-28 22:54 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-07 7:29 ` RISC-V Linux Port v2 David Howells
2017-06-07 21:54 ` Palmer Dabbelt
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