From: Thomas Gleixner <tglx@linutronix.de>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: peterz@infradead.org, mingo@redhat.com, mcgrof@kernel.org,
viro@zeniv.linux.org.uk, sfr@canb.auug.org.au,
nicolas.dichtel@6wind.com, rmk+kernel@armlinux.org.uk,
msalter@redhat.com, tklauser@distanz.ch, will.deacon@arm.com,
james.hogan@imgtec.com, paul.gortmaker@windriver.com,
linux@roeck-us.net, linux-kernel@vger.kernel.org,
linux-arch@vger.kernel.org, albert@sifive.com
Subject: Re: [PATCH 8/9] RISC-V: User-facing API
Date: Wed, 28 Jun 2017 23:49:44 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.20.1706282336270.1890@nanos> (raw)
In-Reply-To: <20170628185538.1804-9-palmer@dabbelt.com>
On Wed, 28 Jun 2017, Palmer Dabbelt wrote:
> +
> +SYSCALL_DEFINE3(sysriscv_cmpxchg32, unsigned long, arg1, unsigned long, arg2,
> + unsigned long, arg3)
> +{
> + unsigned long flags;
> + unsigned long prev;
> + unsigned int *ptr;
> + unsigned int err;
> +
> + ptr = (unsigned int *)arg1;
Errm. Why isn't arg1 a proper pointer type and the arguments arg2/3 u32?
And please give the arguments a proper name, so it's obvious what is what.
SYSCALL_DEFINE3(sysriscv_cmpxchg32, u32 __user *, ptr, u32 new, u32 old)
Hmm?
> + if (!access_ok(VERIFY_WRITE, ptr, sizeof(unsigned int)))
> + return -EFAULT;
> +
> + preempt_disable();
> + raw_local_irq_save(flags);
Why do you want to disable interrupts here? This is thread context and
accessing user space memory, so the only protection this needs is against
preemption.
> + err = __get_user(prev, ptr);
> + if (likely(!err && prev == arg2))
> + err = __put_user(arg3, ptr);
> + raw_local_irq_restore(flags);
> + preempt_enable();
> +
> + return unlikely(err) ? err : prev;
> +}
> +
> +SYSCALL_DEFINE3(sysriscv_cmpxchg64, unsigned long, arg1, unsigned long, arg2,
> + unsigned long, arg3)
This one is even worse. How does this implement cmpxchg64 on a 32bit machine?
Answer: Not at all, because arg2 and 3 are 32bit ....
> +{
> + unsigned long flags;
> + unsigned long prev;
> + unsigned int *ptr;
> + unsigned int err;
> +
> + ptr = (unsigned int *)arg1;
Type casting to random pointer types makes the code more obvious
and safe, right? What the heck has a int pointer to do with u64?
> + if (!access_ok(VERIFY_WRITE, ptr, sizeof(unsigned long)))
> + return -EFAULT;
> +
> + preempt_disable();
> + raw_local_irq_save(flags);
Same as above.
> + err = __get_user(prev, ptr);
Sigh. Type safety is overrated, right?
Thanks,
tglx
next prev parent reply other threads:[~2017-06-28 21:51 UTC|newest]
Thread overview: 212+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-23 0:41 RISC-V Linux Port v1 Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64} Palmer Dabbelt
2017-05-23 11:30 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 10:50 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 17:39 ` Karsten Merker
2017-06-06 17:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt
2017-05-23 1:27 ` Olof Johansson
2017-05-23 1:31 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 4:49 ` Palmer Dabbelt
2017-05-23 5:16 ` [patches] " Olof Johansson
2017-05-23 21:07 ` Benjamin Herrenschmidt
2017-05-23 5:23 ` Olof Johansson
2017-05-23 15:29 ` Palmer Dabbelt
2017-05-23 10:51 ` Geert Uytterhoeven
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-23 11:46 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-29 11:17 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:20 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 3/7] RISC-V: Device Tree Documentation Palmer Dabbelt
2017-05-23 12:03 ` Arnd Bergmann
2017-05-27 0:57 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 4/7] RISC-V: arch/riscv/include Palmer Dabbelt
2017-05-23 12:55 ` Arnd Bergmann
2017-05-23 21:23 ` Benjamin Herrenschmidt
2017-06-03 2:00 ` Palmer Dabbelt
2017-06-01 0:56 ` Palmer Dabbelt
2017-06-01 9:00 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 8:54 ` Arnd Bergmann
2017-06-06 19:07 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt
2017-05-23 10:47 ` Geert Uytterhoeven
2017-05-23 22:07 ` Palmer Dabbelt
2017-05-23 11:19 ` Arnd Bergmann
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-26 9:06 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:31 ` Arnd Bergmann
2017-06-06 20:53 ` Palmer Dabbelt
2017-06-07 7:35 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 6/7] RISC-V: arch/riscv/kernel Palmer Dabbelt
2017-05-23 2:11 ` Olof Johansson
2017-05-25 1:59 ` Palmer Dabbelt
2017-05-25 19:51 ` Arnd Bergmann
2017-06-06 4:56 ` Palmer Dabbelt
2017-06-06 9:03 ` Arnd Bergmann
2017-06-06 20:38 ` Palmer Dabbelt
2017-05-23 13:35 ` Arnd Bergmann
2017-06-02 23:56 ` Palmer Dabbelt
2017-06-06 9:01 ` Arnd Bergmann
2017-06-06 20:37 ` Palmer Dabbelt
2017-05-25 17:05 ` Pavel Machek
2017-06-03 3:32 ` Palmer Dabbelt
2017-05-23 0:41 ` [PATCH 7/7] RISC-V: arch/riscv/mm Palmer Dabbelt
2017-05-23 1:28 ` Randy Dunlap
2017-05-23 2:17 ` Olof Johansson
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 1:16 ` RISC-V Linux Port v1 Olof Johansson
2017-05-23 1:25 ` Randy Dunlap
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 3:36 ` Palmer Dabbelt
2017-05-23 6:45 ` Tobias Klauser
2017-05-23 15:44 ` Palmer Dabbelt
2017-05-23 2:16 ` Randy Dunlap
2017-05-23 4:49 ` Palmer Dabbelt
2017-06-06 22:59 ` RISC-V Linux Port v2 Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 01/17] drivers: support PCIe in RISCV Palmer Dabbelt
2017-06-07 7:17 ` Geert Uytterhoeven
2017-06-07 14:25 ` Christoph Hellwig
[not found] ` <CAMgXwTjXZ5dsxmJ2FyWhCRWo-3nyvKUDfhfV0nNC+oakF=AEsA@mail.gmail.com>
2017-06-07 17:40 ` Olof Johansson
2017-06-23 21:47 ` [patches] " Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt Palmer Dabbelt
2017-06-07 7:18 ` Geert Uytterhoeven
2017-06-07 9:24 ` Marc Zyngier
2017-06-07 19:03 ` Wesley Terpstra
2017-06-06 22:59 ` [PATCH 03/17] base: fix order of OF initialization Palmer Dabbelt
2017-06-07 7:07 ` Geert Uytterhoeven
2017-06-07 9:35 ` Mark Rutland
2017-06-07 18:39 ` Wesley Terpstra
2017-06-07 21:10 ` Benjamin Herrenschmidt
2017-06-08 3:49 ` Frank Rowand
2017-06-08 9:05 ` Mark Rutland
2017-06-09 0:37 ` Frank Rowand
2017-06-06 22:59 ` [PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 9:20 ` Will Deacon
2017-06-06 22:59 ` [PATCH 05/17] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Palmer Dabbelt
2017-06-07 7:19 ` Geert Uytterhoeven
2017-06-07 8:01 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-08 8:12 ` Christoph Hellwig
2017-06-08 8:35 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 07/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-06-06 22:59 ` [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Palmer Dabbelt
2017-06-07 7:11 ` Geert Uytterhoeven
2017-06-07 10:13 ` Mark Rutland
2017-06-07 18:57 ` Wesley Terpstra
2017-06-07 19:57 ` Rob Herring
2017-06-07 20:31 ` Wesley Terpstra
2017-06-08 10:52 ` Mark Rutland
2017-06-09 21:46 ` Wesley Terpstra
2017-06-09 21:58 ` Wesley Terpstra
2017-06-19 14:30 ` Mark Rutland
2017-06-07 22:27 ` Luis R. Rodriguez
2017-06-06 22:59 ` [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Palmer Dabbelt
2017-06-07 7:12 ` Geert Uytterhoeven
2017-06-07 7:25 ` Arnd Bergmann
2017-06-23 23:24 ` Palmer Dabbelt
2017-06-07 9:43 ` Marc Zyngier
2017-06-24 2:02 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 10/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-06-07 7:13 ` Geert Uytterhoeven
2017-06-07 7:55 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-07 10:52 ` Marc Zyngier
2017-06-09 13:47 ` Will Deacon
2017-06-27 1:09 ` Palmer Dabbelt
2017-06-25 20:49 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-06-07 7:14 ` Geert Uytterhoeven
2017-06-06 23:00 ` [PATCH 12/17] tty: New RISC-V SBI Console Driver Palmer Dabbelt
2017-06-07 7:15 ` Geert Uytterhoeven
2017-06-07 7:58 ` Arnd Bergmann
2017-06-24 0:45 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 13/17] RISC-V: Add include subdirectory Palmer Dabbelt
2017-06-07 8:12 ` Arnd Bergmann
2017-06-24 2:01 ` Palmer Dabbelt
2017-06-24 15:42 ` Benjamin Herrenschmidt
2017-06-24 21:32 ` [patches] " Palmer Dabbelt
2017-06-25 3:01 ` Benjamin Herrenschmidt
2017-06-07 11:54 ` Peter Zijlstra
2017-06-07 12:25 ` Peter Zijlstra
2017-06-07 12:06 ` Peter Zijlstra
2017-06-07 12:18 ` Peter Zijlstra
2017-06-07 12:36 ` Peter Zijlstra
2017-06-07 12:58 ` Peter Zijlstra
2017-06-07 13:16 ` Will Deacon
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-27 0:07 ` Daniel Lustig
2017-06-27 8:48 ` Will Deacon
2017-06-07 16:35 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-07 12:42 ` Peter Zijlstra
2017-06-07 13:17 ` Peter Zijlstra
2017-06-09 8:16 ` Peter Zijlstra
2017-06-26 20:07 ` Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 14/17] RISC-V: lib files Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 15/17] RISC-V: Add mm subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 16/17] RISC-V: Add kernel subdirectory Palmer Dabbelt
2017-06-06 23:00 ` [PATCH 17/17] RISC-V: Makefile and Kconfig Palmer Dabbelt
2017-06-07 9:23 ` RISC-V Linux Port v2 Will Deacon
2017-06-07 21:54 ` Palmer Dabbelt
2017-06-08 10:26 ` Will Deacon
2017-06-08 18:16 ` Palmer Dabbelt
2017-06-28 18:55 ` RISC-V Linux Port v3 Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt
2017-06-29 9:44 ` Geert Uytterhoeven
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt
2017-06-28 23:32 ` James Hogan
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-29 8:22 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-06-29 8:39 ` Tobias Klauser
2017-06-29 22:52 ` Palmer Dabbelt
2017-06-30 7:57 ` Tobias Klauser
2017-06-28 18:55 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt
2017-06-28 23:09 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-06-28 21:49 ` Thomas Gleixner [this message]
2017-06-28 21:52 ` Thomas Gleixner
2017-06-29 17:22 ` Palmer Dabbelt
2017-06-28 22:42 ` James Hogan
2017-06-29 21:42 ` Palmer Dabbelt
2017-07-03 23:06 ` James Hogan
2017-07-05 16:49 ` Palmer Dabbelt
2017-06-28 18:55 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt
2017-06-28 21:05 ` Karsten Merker
2017-06-28 21:13 ` Palmer Dabbelt
2017-06-28 21:25 ` James Hogan
2017-06-29 16:29 ` Palmer Dabbelt
2017-06-28 22:54 ` James Hogan
2017-06-29 22:11 ` Palmer Dabbelt
2017-06-07 7:29 ` RISC-V Linux Port v2 David Howells
2017-06-07 21:54 ` Palmer Dabbelt
2017-07-04 19:50 RISC-V Linux Port v4 Palmer Dabbelt
2017-07-04 19:51 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt
2017-07-05 10:24 ` James Hogan
2017-07-06 2:01 ` Christoph Hellwig
2017-07-06 8:55 ` Will Deacon
2017-07-06 15:34 ` Christoph Hellwig
2017-07-06 15:45 ` Will Deacon
[not found] ` <mhng-f92ef7c4-049a-4a71-be12-c600d1d7858b@palmer-si-x1c4>
2017-07-10 20:18 ` Palmer Dabbelt
2017-07-11 13:22 ` Will Deacon
2017-07-11 13:55 ` Christoph Hellwig
2017-07-11 17:28 ` Palmer Dabbelt
2017-07-11 17:07 ` Palmer Dabbelt
2017-07-06 15:34 ` Dave P Martin
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