From: Borislav Petkov <bp@alien8.de>
To: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org, leo.duran@amd.com,
yazen.ghannam@amd.com, Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket
Date: Tue, 27 Jun 2017 18:16:57 +0200 [thread overview]
Message-ID: <20170627161657.p4kurw2f3gcavfvz@pd.tnic> (raw)
In-Reply-To: <122fd136-e3a1-1d59-87c8-a24de6b078c1@amd.com>
On Tue, Jun 27, 2017 at 10:55:52PM +0700, Suravee Suthikulpanit wrote:
> The reason we are trying to present "package == NUMA node (die)" here is
> because the topology.txt defines package to contain a number of cores plus
> shared resources (e.g. DRAM controller, shared caches, etc). Since the
> cpuinfo_x86.phys_proc_id is also defined as the physical ID of the package,
Ok, it seems we will continue talking past each other here. So let's
look at the issues separately:
* irqbalance fails to allocating IRQs to individual CPU within the die.
Why does it fail? What is the root cause for this?
* The scheduler fails to load-balance across 8 threads within a die
(e.g. running 8-thread application w/ taskset -c 0-7 ) with
the DIE schedule domain omitted due to x86_has_numa_in_package.
Why do you need to load-balance within the die? Why not load-balance
within the 0-15 threads?
What are the disadvantages of the situation now?
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
next prev parent reply other threads:[~2017-06-27 16:17 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-27 6:40 [PATCH 0/2] x86/CPU/AMD: Fix multi-die processor topology info Suravee Suthikulpanit
2017-06-27 6:40 ` [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket Suravee Suthikulpanit
2017-06-27 10:48 ` Borislav Petkov
2017-06-27 13:07 ` Suravee Suthikulpanit
2017-06-27 13:42 ` Borislav Petkov
2017-06-27 16:54 ` Suravee Suthikulpanit
2017-06-27 17:44 ` Borislav Petkov
2017-06-27 18:32 ` Ghannam, Yazen
2017-06-27 18:44 ` Borislav Petkov
2017-06-27 20:26 ` Suravee Suthikulpanit
2017-06-28 9:12 ` Borislav Petkov
2017-06-27 14:21 ` Thomas Gleixner
2017-06-27 14:54 ` Brice Goglin
2017-06-27 15:48 ` Duran, Leo
2017-06-27 16:11 ` Borislav Petkov
2017-06-27 16:23 ` Duran, Leo
2017-06-27 16:31 ` Borislav Petkov
2017-06-27 16:42 ` Duran, Leo
2017-06-27 16:45 ` Borislav Petkov
2017-06-27 17:04 ` Duran, Leo
2017-06-27 16:19 ` Thomas Gleixner
2017-06-27 16:34 ` Duran, Leo
2017-06-27 15:55 ` Suravee Suthikulpanit
2017-06-27 16:16 ` Borislav Petkov [this message]
2017-07-05 15:50 ` Peter Zijlstra
2017-06-27 6:40 ` [PATCH 2/2] x86/CPU/AMD: Use L3 Cache info from CPUID to determine LLC ID Suravee Suthikulpanit
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