[PATCH v3 0/3] arm: npcm: add basic support for Nuvoton BMCs

[PATCH v3 0/3] arm: npcm: add basic support for Nuvoton BMCs

[Brendan Higgins]

Addressed comments from:
  - Florian: https://www.spinics.net/lists/arm-kernel/msg604948.html

Changes since previous update:
  - Substanitally simplified the SMP code for NPCM750.
  - No changes to device tree or MAINTAINERS since v2

Changes have been tested on the NPCM750 evaluation board.

[PATCH v3 1/3] arm: npcm: add basic support for Nuvoton BMCs

[Brendan Higgins]

Adds basic support for the Nuvoton NPCM750 BMC.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
 arch/arm/Kconfig             |  2 +
 arch/arm/Makefile            |  1 +
 arch/arm/mach-npcm/Kconfig   | 48 ++++++++++++++++++++++++
 arch/arm/mach-npcm/Makefile  |  3 ++
 arch/arm/mach-npcm/headsmp.S | 17 +++++++++
 arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++
 arch/arm/mach-npcm/platsmp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 194 insertions(+)
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 61a0cb15067e..05543f1cfbde 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-npcm/Kconfig"
+
 source "arch/arm/mach-nspire/Kconfig"
 
 source "arch/arm/plat-omap/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..60ca50c7d762 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NPCM)		+= npcm
 machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OXNAS)		+= oxnas
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
new file mode 100644
index 000000000000..dfb17afa0230
--- /dev/null
+++ b/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,48 @@
+menuconfig ARCH_NPCM
+	bool "Nuvoton NPCM Architecture"
+	select ARCH_REQUIRE_GPIOLIB
+	select USE_OF
+	select PINCTRL
+	select PINCTRL_NPCM7XX
+
+if ARCH_NPCM
+
+comment "NPCMX50 CPU type"
+
+config CPU_NPCM750
+	depends on ARCH_NPCM && ARCH_MULTI_V7
+	bool "Support for NPCM750 BMC CPU (Poleg)"
+	select CACHE_L2X0
+	select CPU_V7
+	select ARM_GIC
+	select HAVE_SMP
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if SMP
+	select ARM_ERRATA_458693
+	select ARM_ERRATA_720789
+	select ARM_ERRATA_742231
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_764369
+	select ARM_ERRATA_794072
+	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
+	select USB_EHCI_ROOT_HUB_TT
+	select USB_ARCH_HAS_HCD
+	select USB_ARCH_HAS_EHCI
+	select USB_EHCI_HCD
+	select USB_ARCH_HAS_OHCI
+	select USB_OHCI_HCD
+	select USB
+	select FIQ
+	select CPU_USE_DOMAINS
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select COMMON_CLK if OF
+	select NPCM750_TIMER
+	select MFD_SYSCON
+	help
+	  Support for NPCM750 BMC CPU (Poleg).
+
+	  Nuvoton NPCM750 BMC based on the Cortex A9.
+
+endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
new file mode 100644
index 000000000000..78416055b854
--- /dev/null
+++ b/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,3 @@
+AFLAGS_headsmp.o		+= -march=armv7-a
+
+obj-$(CONFIG_CPU_NPCM750)	+= npcm7xx.o platsmp.o headsmp.o
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
new file mode 100644
index 000000000000..9fccbbd49ed4
--- /dev/null
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+ENTRY(npcm7xx_secondary_startup)
+	safe_svcmode_maskall r0
+
+	b	secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
index 000000000000..132e9d587857
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017 Nuvoton Technology corporation.
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |			       \
+			 L310_AUX_CTRL_DATA_PREFETCH |			       \
+			 L310_AUX_CTRL_NS_LOCKDOWN |			       \
+			 L310_AUX_CTRL_CACHE_REPLACE_RR |		       \
+			 L2C_AUX_CTRL_SHARED_OVERRIDE |			       \
+			 L310_AUX_CTRL_FULL_LINE_ZERO)
+
+static const char *const npcm7xx_dt_match[] = {
+	"nuvoton,npcm750",
+	NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family")
+	.atag_offset	= 0x100,
+	.dt_compat	= npcm7xx_dt_match,
+	.l2c_aux_val	= NPCM7XX_AUX_VAL,
+	.l2c_aux_mask	= ~NPCM7XX_AUX_VAL,
+MACHINE_END
diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
new file mode 100644
index 000000000000..144e3e7ec7e6
--- /dev/null
+++ b/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "PLATSMP: " fmt
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
+extern void npcm7xx_secondary_startup(void);
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu,
+				      struct task_struct *idle)
+{
+	struct device_node *gcr_np;
+	void __iomem *gcr_base;
+	int ret = 0;
+
+	gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+	if (!gcr_np) {
+		pr_err("no gcr device node\n");
+		ret = -EFAULT;
+		goto out;
+	}
+	gcr_base = of_iomap(gcr_np, 0);
+	if (!gcr_base) {
+		pr_err("could not iomap gcr at: 0x%llx\n", gcr_base);
+		ret = -EFAULT;
+		goto out;
+	}
+
+	/* give boot ROM kernel start address. */
+	iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
+		  NPCM7XX_SCRPAD_REG);
+	/* make sure npcm7xx_secondary_startup is seen by all observers. */
+	smp_wmb();
+	dsb_sev();
+	/* make sure write buffer is drained */
+	mb();
+
+out:
+	iounmap(gcr_base);
+	return ret;
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *scu_np;
+	void __iomem *scu_base;
+
+	scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+	if (!scu_np) {
+		pr_err("no scu device node\n");
+		return;
+	}
+	scu_base = of_iomap(scu_np, 0);
+	if (!scu_base) {
+		pr_err("could not iomap scu at: 0x%llx\n", scu_base);
+		return;
+	}
+
+	scu_enable(scu_base);
+
+out:
+	iounmap(scu_base);
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+	.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+	.smp_boot_secondary = npcm7xx_smp_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
-- 
2.14.1.581.gf28d330327-goog

[PATCH v3 2/3] arm: dts: add Nuvoton NPCM750 device tree

[Brendan Higgins]

Add a common device tree for all Nuvoton NPCM750 BMCs and a board
specific device tree for the NPCM750 (Poleg) evaluation board.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Avi Fishman <avifishman70@gmail.com>
Tested-by: Tomer Maimon <tmaimon77@gmail.com>
Tested-by: Avi Fishman <avifishman70@gmail.com>
---
 .../arm/cpu-enable-method/nuvoton,npcm7xx-smp      |  42 +++++
 .../devicetree/bindings/arm/npcm/npcm.txt          |   6 +
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts          |  59 +++++++
 arch/arm/boot/dts/nuvoton-npcm750.dtsi             | 177 +++++++++++++++++++++
 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h   |  39 +++++
 5 files changed, 323 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
 create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h

diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
new file mode 100644
index 000000000000..e81f85b400cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name:	"nuvoton,npcm7xx-smp"
+Compatible machines:	"nuvoton,npcm750"
+Compatible CPUs:	"arm,cortex-a9"
+Related properties:	(none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "nuvoton,npcm7xx-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+	};
+
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000000..2d87d9ecea85
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+	- compatible = "nuvoton,npcm750";
+
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
new file mode 100644
index 000000000000..54df32cff21b
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -0,0 +1,59 @@
+/*
+ * DTS file for all NPCM750 SoCs
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+
+/ {
+	model = "Nuvoton npcm750 Development Board (Device Tree)";
+	compatible = "nuvoton,npcm750";
+
+	chosen {
+		stdout-path = &serial3;
+		bootargs = "earlyprintk=serial,serial3,115200";
+	};
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	cpus {
+		enable-method = "nuvoton,npcm7xx-smp";
+	};
+
+	clk: clock-controller@f0801000 {
+		status = "okay";
+	};
+
+	apb {
+		watchdog1: watchdog@f0009000 {
+			status = "okay";
+		};
+
+		serial0: serial0@f0001000 {
+			status = "okay";
+		};
+
+		serial1: serial1@f0002000 {
+			status = "okay";
+		};
+
+		serial2: serial2@f0003000 {
+			status = "okay";
+		};
+
+		serial3: serial3@f0004000 {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..bca96b3ae9d3
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,177 @@
+/*
+ * DTSi file for the NPCM750 SoC
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&l2>;
+		};
+	};
+
+	gcr: gcr@f0800000 {
+		compatible = "nuvoton,npcm750-gcr", "syscon",
+			"simple-mfd";
+		reg = <0xf0800000 0x1000>;
+	};
+
+	scu: scu@f03fe000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xf03fe000 0x1000>;
+	};
+
+	l2: l2-cache@f03fc000 {
+		compatible = "arm,pl310-cache";
+		reg = <0xf03fc000 0x1000>;
+		interrupts = <0 21 4>;
+		cache-unified;
+		cache-level = <2>;
+		clocks = <&clk NPCM7XX_CLK_AXI>;
+	};
+
+	gic: interrupt-controller@f03ff000 {
+		compatible = "arm,cortex-a9-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0xf03ff000 0x1000>,
+		    <0xf03fe100 0x100>;
+	};
+
+	clk: clock-controller@f0801000 {
+		compatible = "nuvoton,npcm750-clk";
+		#clock-cells = <1>;
+		reg = <0xf0801000 0x1000>;
+	};
+
+	/* external clock signal rg1refck, supplied by the phy */
+	clk-rg1refck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	/* external clock signal rg2refck, supplied by the phy */
+	clk-rg2refck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clk-xin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	timer@f03fe600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0xf03fe600 0x20>;
+		interrupts = <1 13 0x304>;
+		clocks = <&clk NPCM7XX_CLK_TIMER>;
+	};
+
+	apb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		timer0: timer@f0000000 {
+			compatible = "nuvoton,npcm750-timer";
+			interrupts = <0 32 4>;
+			reg = <0xf0000000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+		};
+
+		watchdog0: watchdog@f0008000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 47 4>;
+			reg = <0xf0008000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+		};
+
+		watchdog1: watchdog@f0009000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 48 4>;
+			reg = <0xf0009000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+		};
+
+		watchdog2: watchdog@f000a000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 49 4>;
+			reg = <0xf000a000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+		};
+
+		serial0: serial0@f0001000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0001000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			interrupts = <0 2 4>;
+			status = "disabled";
+		};
+
+		serial1: serial1@f0002000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0002000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			interrupts = <0 3 4>;
+			status = "disabled";
+		};
+
+		serial2: serial2@f0003000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0003000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			interrupts = <0 4 4>;
+			status = "disabled";
+		};
+
+		serial3: serial3@f0004000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0004000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			interrupts = <0 5 4>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
new file mode 100644
index 000000000000..c69d3bbf7e42
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Nuvoton Technologies,  tali.perry@nuvoton.com
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_NPCM7XX_H
+#define _DT_BINDINGS_CLK_NPCM7XX_H
+
+#define NPCM7XX_CLK_PLL0	0
+#define NPCM7XX_CLK_PLL1	1
+#define NPCM7XX_CLK_PLL2	2
+#define NPCM7XX_CLK_GFX		3
+#define NPCM7XX_CLK_APB1	4
+#define NPCM7XX_CLK_APB2	5
+#define NPCM7XX_CLK_APB3	6
+#define NPCM7XX_CLK_APB4	7
+#define NPCM7XX_CLK_APB5	8
+#define NPCM7XX_CLK_MC		9
+#define NPCM7XX_CLK_CPU		10
+#define NPCM7XX_CLK_SPI0	11
+#define NPCM7XX_CLK_SPI3	12
+#define NPCM7XX_CLK_SPIX	13
+#define NPCM7XX_CLK_UART_CORE	14
+#define NPCM7XX_CLK_TIMER	15
+#define NPCM7XX_CLK_HOST_UART	16
+#define NPCM7XX_CLK_MMC		17
+#define NPCM7XX_CLK_SDHC	18
+#define NPCM7XX_CLK_ADC		19
+#define NPCM7XX_CLK_GFX_MEM	20
+#define NPCM7XX_CLK_USB_BRIDGE	21
+#define NPCM7XX_CLK_AXI		22
+#define NPCM7XX_CLK_AHB		23
+#define NPCM7XX_CLK_EMC		24
+#define NPCM7XX_CLK_GMAC	25
+
+#endif
-- 
2.14.1.581.gf28d330327-goog

[PATCH v3 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture

[Brendan Higgins]

Add maintainers and reviewers for the Nuvoton NPCM architecture.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Avi Fishman <avifishman70@gmail.com>
---
 MAINTAINERS | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 44cb004c765d..67064bf11904 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1598,6 +1598,19 @@ F:	drivers/pinctrl/nomadik/
 F:	drivers/i2c/busses/i2c-nomadik.c
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
 
+ARM/NUVOTON NPCM ARCHITECTURE
+M:	Avi Fishman <avifishman70@gmail.com>
+M:	Tomer Maimon <tmaimon77@gmail.com>
+R:	Brendan Higgins <brendanhiggins@google.com>
+R:	Rick Altherr <raltherr@google.com>
+L:	openbmc@lists.ozlabs.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm/mach-npcm/
+F:	arch/arm/boot/dts/nuvoton-npcm*
+F:	include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F:	drivers/*/*npcm*
+F:	Documentation/*/*npcm*
+
 ARM/NUVOTON W90X900 ARM ARCHITECTURE
 M:	Wan ZongShun <mcuos.com@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.14.1.581.gf28d330327-goog

Re: [PATCH v3 2/3] arm: dts: add Nuvoton NPCM750 device tree

[Joel Stanley]

On Wed, Sep 6, 2017 at 10:00 AM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
> @@ -0,0 +1,6 @@
> +NPCM Platforms Device Tree Bindings
> +-----------------------------------
> +NPCM750 SoC
> +Required root node properties:
> +       - compatible = "nuvoton,npcm750";
> +

This is minimal. I assume there will be more content added as more
support is added?

Does it need it's own directory?


> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> new file mode 100644
> index 000000000000..54df32cff21b
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts

> +
> +/dts-v1/;
> +#include "nuvoton-npcm750.dtsi"
> +
> +/ {
> +       model = "Nuvoton npcm750 Development Board (Device Tree)";
> +       compatible = "nuvoton,npcm750";
> +
> +       chosen {
> +               stdout-path = &serial3;
> +               bootargs = "earlyprintk=serial,serial3,115200";
> +       };
> +
> +       memory {
> +               reg = <0 0x40000000>;
> +       };
> +
> +       cpus {
> +               enable-method = "nuvoton,npcm7xx-smp";
> +       };
> +
> +       clk: clock-controller@f0801000 {
> +               status = "okay";
> +       };
> +
> +       apb {
> +               watchdog1: watchdog@f0009000 {
> +                       status = "okay";
> +               };

You've already got the label for the node, is there are reason you
don't use a phandle to set the status?

&watchdog1 {
   status = "okay";
};

Same with the serial nodes below.

> +
> +               serial0: serial0@f0001000 {
> +                       status = "okay";
> +               };
> +
> +               serial1: serial1@f0002000 {
> +                       status = "okay";
> +               };
> +
> +               serial2: serial2@f0003000 {
> +                       status = "okay";
> +               };
> +
> +               serial3: serial3@f0004000 {
> +                       status = "okay";
> +               };
> +       };

Re: [PATCH v3 2/3] arm: dts: add Nuvoton NPCM750 device tree

[Brendan Higgins]

On Tue, Sep 5, 2017 at 10:23 PM, Joel Stanley <joel@jms.id.au> wrote:
> On Wed, Sep 6, 2017 at 10:00 AM, Brendan Higgins
> <brendanhiggins@google.com> wrote:
>> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
>> @@ -0,0 +1,6 @@
>> +NPCM Platforms Device Tree Bindings
>> +-----------------------------------
>> +NPCM750 SoC
>> +Required root node properties:
>> +       - compatible = "nuvoton,npcm750";
>> +
>
> This is minimal. I assume there will be more content added as more
> support is added?

Yep, that's the plan. They have a number of similar BMCs, both those
based on different ARM cores and some with different peripheral sets,
so we will probably want to have different compat strings for those.

>
> Does it need it's own directory?

Not sure, I saw that some of the other architectures did it, some did
not. I don't feel strongly about it.

>
>
>> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
>> new file mode 100644
>> index 000000000000..54df32cff21b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
>
>> +
>> +/dts-v1/;
>> +#include "nuvoton-npcm750.dtsi"
>> +
>> +/ {
>> +       model = "Nuvoton npcm750 Development Board (Device Tree)";
>> +       compatible = "nuvoton,npcm750";
>> +
>> +       chosen {
>> +               stdout-path = &serial3;
>> +               bootargs = "earlyprintk=serial,serial3,115200";
>> +       };
>> +
>> +       memory {
>> +               reg = <0 0x40000000>;
>> +       };
>> +
>> +       cpus {
>> +               enable-method = "nuvoton,npcm7xx-smp";
>> +       };
>> +
>> +       clk: clock-controller@f0801000 {
>> +               status = "okay";
>> +       };
>> +
>> +       apb {
>> +               watchdog1: watchdog@f0009000 {
>> +                       status = "okay";
>> +               };
>
> You've already got the label for the node, is there are reason you
> don't use a phandle to set the status?

Addressed in v4.

>
> &watchdog1 {
>    status = "okay";
> };
>
> Same with the serial nodes below.
>
>> +
>> +               serial0: serial0@f0001000 {
>> +                       status = "okay";
>> +               };
>> +
>> +               serial1: serial1@f0002000 {
>> +                       status = "okay";
>> +               };
>> +
>> +               serial2: serial2@f0003000 {
>> +                       status = "okay";
>> +               };
>> +
>> +               serial3: serial3@f0004000 {
>> +                       status = "okay";
>> +               };
>> +       };

Re: [PATCH v3 1/3] arm: npcm: add basic support for Nuvoton BMCs

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1120 bytes --]

Hi Brendan,

[auto build test WARNING on linus/master]
[also build test WARNING on v4.13 next-20170907]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Brendan-Higgins/arm-npcm-add-basic-support-for-Nuvoton-BMCs/20170907-214055
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

warning: (CPU_NPCM750) selects ARM_ERRATA_458693 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM)
warning: (CPU_NPCM750) selects ARM_ERRATA_742231 which has unmet direct dependencies (CPU_V7 && SMP && !ARCH_MULTIPLATFORM)

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 63097 bytes --]

Re: [PATCH v3 1/3] arm: npcm: add basic support for Nuvoton BMCs

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4291 bytes --]

Hi Brendan,

[auto build test WARNING on linus/master]
[also build test WARNING on v4.13 next-20170907]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Brendan-Higgins/arm-npcm-add-basic-support-for-Nuvoton-BMCs/20170907-214055
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   In file included from include/linux/printk.h:6:0,
                    from include/linux/kernel.h:13,
                    from include/linux/delay.h:21,
                    from arch/arm/mach-npcm/platsmp.c:11:
   arch/arm/mach-npcm/platsmp.c: In function 'npcm7xx_smp_boot_secondary':
>> include/linux/kern_levels.h:4:18: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'void *' [-Wformat=]
    #define KERN_SOH "\001"  /* ASCII Start Of Header */
                     ^
   include/linux/kern_levels.h:10:18: note: in expansion of macro 'KERN_SOH'
    #define KERN_ERR KERN_SOH "3" /* error conditions */
                     ^~~~~~~~
   include/linux/printk.h:301:9: note: in expansion of macro 'KERN_ERR'
     printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
            ^~~~~~~~
>> arch/arm/mach-npcm/platsmp.c:43:3: note: in expansion of macro 'pr_err'
      pr_err("could not iomap gcr at: 0x%llx\n", gcr_base);
      ^~~~~~
   arch/arm/mach-npcm/platsmp.c: In function 'npcm7xx_smp_prepare_cpus':
>> include/linux/kern_levels.h:4:18: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'void *' [-Wformat=]
    #define KERN_SOH "\001"  /* ASCII Start Of Header */
                     ^
   include/linux/kern_levels.h:10:18: note: in expansion of macro 'KERN_SOH'
    #define KERN_ERR KERN_SOH "3" /* error conditions */
                     ^~~~~~~~
   include/linux/printk.h:301:9: note: in expansion of macro 'KERN_ERR'
     printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
            ^~~~~~~~
   arch/arm/mach-npcm/platsmp.c:74:3: note: in expansion of macro 'pr_err'
      pr_err("could not iomap scu at: 0x%llx\n", scu_base);
      ^~~~~~
   arch/arm/mach-npcm/platsmp.c:80:1: warning: label 'out' defined but not used [-Wunused-label]
    out:
    ^~~
   In file included from include/linux/io.h:25:0,
                    from arch/arm/mach-npcm/platsmp.c:14:
   arch/arm/mach-npcm/platsmp.c: In function 'npcm7xx_smp_boot_secondary':
>> arch/arm/include/asm/io.h:421:17: warning: 'gcr_base' may be used uninitialized in this function [-Wmaybe-uninitialized]
    #define iounmap iounmap
                    ^~~~~~~
   arch/arm/mach-npcm/platsmp.c:32:16: note: 'gcr_base' was declared here
     void __iomem *gcr_base;
                   ^~~~~~~~

vim +/pr_err +43 arch/arm/mach-npcm/platsmp.c

    27	
    28	static int npcm7xx_smp_boot_secondary(unsigned int cpu,
    29					      struct task_struct *idle)
    30	{
    31		struct device_node *gcr_np;
    32		void __iomem *gcr_base;
    33		int ret = 0;
    34	
    35		gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
    36		if (!gcr_np) {
    37			pr_err("no gcr device node\n");
    38			ret = -EFAULT;
    39			goto out;
    40		}
    41		gcr_base = of_iomap(gcr_np, 0);
    42		if (!gcr_base) {
  > 43			pr_err("could not iomap gcr at: 0x%llx\n", gcr_base);
    44			ret = -EFAULT;
    45			goto out;
    46		}
    47	
    48		/* give boot ROM kernel start address. */
    49		iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
    50			  NPCM7XX_SCRPAD_REG);
    51		/* make sure npcm7xx_secondary_startup is seen by all observers. */
    52		smp_wmb();
    53		dsb_sev();
    54		/* make sure write buffer is drained */
    55		mb();
    56	
    57	out:
    58		iounmap(gcr_base);
    59		return ret;
    60	}
    61	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 63097 bytes --]