* [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller
2018-02-19 6:54 [PATCH 0/3] reset: simple: enable for ASPEED SoCs Joel Stanley
@ 2018-02-19 6:54 ` Joel Stanley
2018-02-19 11:46 ` Philipp Zabel
2018-02-19 20:41 ` Rob Herring
2018-02-19 6:54 ` [PATCH 2/3] reset: simple: Enable for ASPEED systems Joel Stanley
` (2 subsequent siblings)
3 siblings, 2 replies; 10+ messages in thread
From: Joel Stanley @ 2018-02-19 6:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Philipp Zabel, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
This describes the reset controller present in the LPC address space.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index 514d82ced95b..721a2b1eb40f 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -135,3 +135,24 @@ lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+LPC reset control
+-----------------
+
+The UARTs present in the ASPEED SoC can have their resets tied to the reset
+state of the LPC bus. Some systems may chose to modify this configuration.
+
+Required properties:
+
+ - comaptible: "aspeed,ast2500-lpc-reset" or
+ "aspeed,ast2400-lpc-reset"
+ - reg: offset and length of the IP in the LHC memory region
+ - #reset-controller indacates the number of reset cells excepted
+
+Example:
+
+lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+};
--
2.15.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller
2018-02-19 6:54 ` [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller Joel Stanley
@ 2018-02-19 11:46 ` Philipp Zabel
2018-02-19 12:00 ` Joel Stanley
2018-02-19 20:41 ` Rob Herring
1 sibling, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2018-02-19 11:46 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
On Mon, 2018-02-19 at 17:24 +1030, Joel Stanley wrote:
> This describes the reset controller present in the LPC address space.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> index 514d82ced95b..721a2b1eb40f 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> @@ -135,3 +135,24 @@ lhc: lhc@20 {
> compatible = "aspeed,ast2500-lhc";
> reg = <0x20 0x24 0x48 0x8>;
> };
> +
> +LPC reset control
> +-----------------
> +
> +The UARTs present in the ASPEED SoC can have their resets tied to the reset
> +state of the LPC bus. Some systems may chose to modify this configuration.
> +
> +Required properties:
> +
> + - comaptible: "aspeed,ast2500-lpc-reset" or
"compatible"
> + "aspeed,ast2400-lpc-reset"
> + - reg: offset and length of the IP in the LHC memory region
> + - #reset-controller indacates the number of reset cells excepted
"indicates", "expected"
> +
> +Example:
> +
> +lpc_reset: reset-controller@18 {
> + compatible = "aspeed,ast2500-lpc-reset";
> + reg = <0x18 0x4>;
> + #reset-cells = <1>;
> +};
Should this mention or indicate in the example that the reset-controller
node must be child of (a subnode of) the lpc node?
regards
Philipp
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller
2018-02-19 11:46 ` Philipp Zabel
@ 2018-02-19 12:00 ` Joel Stanley
0 siblings, 0 replies; 10+ messages in thread
From: Joel Stanley @ 2018-02-19 12:00 UTC (permalink / raw)
To: Philipp Zabel
Cc: Rob Herring, Mark Rutland, Andrew Jeffery, Lee Jones, devicetree,
Linux Kernel Mailing List, linux-aspeed
On Mon, Feb 19, 2018 at 10:16 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> On Mon, 2018-02-19 at 17:24 +1030, Joel Stanley wrote:
>> This describes the reset controller present in the LPC address space.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> ---
>> .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
>> index 514d82ced95b..721a2b1eb40f 100644
>> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
>> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
>> @@ -135,3 +135,24 @@ lhc: lhc@20 {
>> compatible = "aspeed,ast2500-lhc";
>> reg = <0x20 0x24 0x48 0x8>;
>> };
>> +
>> +LPC reset control
>> +-----------------
>> +
>> +The UARTs present in the ASPEED SoC can have their resets tied to the reset
>> +state of the LPC bus. Some systems may chose to modify this configuration.
>> +
>> +Required properties:
>> +
>> + - comaptible: "aspeed,ast2500-lpc-reset" or
>
> "compatible"
>
>> + "aspeed,ast2400-lpc-reset"
>> + - reg: offset and length of the IP in the LHC memory region
>> + - #reset-controller indacates the number of reset cells excepted
>
> "indicates", "expected"
Oops, thanks.
>
>> +
>> +Example:
>> +
>> +lpc_reset: reset-controller@18 {
>> + compatible = "aspeed,ast2500-lpc-reset";
>> + reg = <0x18 0x4>;
>> + #reset-cells = <1>;
>> +};
>
> Should this mention or indicate in the example that the reset-controller
> node must be child of (a subnode of) the lpc node?
This is indicated by the layout of the binding document. The "LPC
reset control" heading is below a "Host Node Children" heading.
>
> regards
> Philipp
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller
2018-02-19 6:54 ` [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller Joel Stanley
2018-02-19 11:46 ` Philipp Zabel
@ 2018-02-19 20:41 ` Rob Herring
1 sibling, 0 replies; 10+ messages in thread
From: Rob Herring @ 2018-02-19 20:41 UTC (permalink / raw)
To: Joel Stanley
Cc: Mark Rutland, Philipp Zabel, Andrew Jeffery, Lee Jones,
devicetree, linux-kernel, linux-aspeed
On Mon, Feb 19, 2018 at 05:24:36PM +1030, Joel Stanley wrote:
> This describes the reset controller present in the LPC address space.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] reset: simple: Enable for ASPEED systems
2018-02-19 6:54 [PATCH 0/3] reset: simple: enable for ASPEED SoCs Joel Stanley
2018-02-19 6:54 ` [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller Joel Stanley
@ 2018-02-19 6:54 ` Joel Stanley
2018-02-19 6:54 ` [PATCH 3/3] reset: simple: Allow user selection of driver Joel Stanley
2018-02-19 11:46 ` [PATCH 0/3] reset: simple: enable for ASPEED SoCs Philipp Zabel
3 siblings, 0 replies; 10+ messages in thread
From: Joel Stanley @ 2018-02-19 6:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Philipp Zabel, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
ASPEED BMC SoCs have a reset controller in the LPC IP that can be
controlled using this driver to release the UARTs from reset.
No special configuration is required, so only the compatible string is
added.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/reset/Kconfig | 10 +++++++---
drivers/reset/reset-simple.c | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc77696bb1e..18f152d251d7 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -83,14 +83,18 @@ config RESET_PISTACHIO
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
- default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
+ default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
- Currently this driver supports Altera SoCFPGAs, the RCC reset
- controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family.
+ Currently this driver supports:
+ - Altera SoCFPGAs
+ - ASPEED BMC SoCs
+ - RCC reset controller in STM32 MCUs
+ - Allwinner SoCs
+ - ZTE's zx2967 family
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 2d4f362ef025..f7ce8910a392 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -125,6 +125,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
.data = &reset_simple_active_low },
{ .compatible = "zte,zx296718-reset",
.data = &reset_simple_active_low },
+ { .compatible = "aspeed,ast2400-lpc-reset" },
+ { .compatible = "aspeed,ast2500-lpc-reset" },
{ /* sentinel */ },
};
--
2.15.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/3] reset: simple: Allow user selection of driver
2018-02-19 6:54 [PATCH 0/3] reset: simple: enable for ASPEED SoCs Joel Stanley
2018-02-19 6:54 ` [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller Joel Stanley
2018-02-19 6:54 ` [PATCH 2/3] reset: simple: Enable for ASPEED systems Joel Stanley
@ 2018-02-19 6:54 ` Joel Stanley
2018-02-19 11:46 ` Philipp Zabel
2018-02-19 11:46 ` [PATCH 0/3] reset: simple: enable for ASPEED SoCs Philipp Zabel
3 siblings, 1 reply; 10+ messages in thread
From: Joel Stanley @ 2018-02-19 6:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Philipp Zabel, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
Currently this driver is only user selectable if COMPILE_TEST is turned
on. Users may wish to select (and deselect) it, so remove this
restriction.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/reset/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 18f152d251d7..7490a4370900 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -82,7 +82,7 @@ config RESET_PISTACHIO
This enables the reset driver for ImgTec Pistachio SoCs.
config RESET_SIMPLE
- bool "Simple Reset Controller Driver" if COMPILE_TEST
+ bool "Simple Reset Controller Driver"
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
help
This enables a simple reset controller driver for reset lines that
--
2.15.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] reset: simple: Allow user selection of driver
2018-02-19 6:54 ` [PATCH 3/3] reset: simple: Allow user selection of driver Joel Stanley
@ 2018-02-19 11:46 ` Philipp Zabel
2018-02-19 12:07 ` Joel Stanley
0 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2018-02-19 11:46 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
On Mon, 2018-02-19 at 17:24 +1030, Joel Stanley wrote:
> Currently this driver is only user selectable if COMPILE_TEST is turned
> on. Users may wish to select (and deselect) it, so remove this
> restriction.
I would like to keep user visible options to a minimum unless there is a
good reason. What is the scenario in which a user would decide to
disable the default-enabled reset-simple driver, or the other way
around? This should be mentioned in the commit message.
Maybe this is an indication that there could be a better default than
just ARCH_ASPEED.
regards
Philipp
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/reset/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 18f152d251d7..7490a4370900 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -82,7 +82,7 @@ config RESET_PISTACHIO
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> config RESET_SIMPLE
> - bool "Simple Reset Controller Driver" if COMPILE_TEST
> + bool "Simple Reset Controller Driver"
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
> help
> This enables a simple reset controller driver for reset lines that
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] reset: simple: Allow user selection of driver
2018-02-19 11:46 ` Philipp Zabel
@ 2018-02-19 12:07 ` Joel Stanley
0 siblings, 0 replies; 10+ messages in thread
From: Joel Stanley @ 2018-02-19 12:07 UTC (permalink / raw)
To: Philipp Zabel
Cc: Rob Herring, Mark Rutland, Andrew Jeffery, Lee Jones, devicetree,
Linux Kernel Mailing List, linux-aspeed
On Mon, Feb 19, 2018 at 10:16 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> On Mon, 2018-02-19 at 17:24 +1030, Joel Stanley wrote:
>> Currently this driver is only user selectable if COMPILE_TEST is turned
>> on. Users may wish to select (and deselect) it, so remove this
>> restriction.
>
> I would like to keep user visible options to a minimum unless there is a
> good reason. What is the scenario in which a user would decide to
> disable the default-enabled reset-simple driver, or the other way
> around? This should be mentioned in the commit message.
In this SoC's case the driver is not essential. A system that does not
use UART1..4 will not ever call on the driver. This situation is
common as the console uses UART5.
> Maybe this is an indication that there could be a better default than
> just ARCH_ASPEED.
This is an appropriate default, as it causes the least surprise to a
user. Without taking the UART out of reset, the kernel driver still
loads, but characters are never drained from the FIFO.
Advanced users may want to save the few kilobytes that an extra driver
adds, and the boot overhead of loading yet another driver. The saving
is small, so if you feel strongly about it we can drop this patch.
Cheers,
Joel
>
> regards
> Philipp
>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> ---
>> drivers/reset/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 18f152d251d7..7490a4370900 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -82,7 +82,7 @@ config RESET_PISTACHIO
>> This enables the reset driver for ImgTec Pistachio SoCs.
>>
>> config RESET_SIMPLE
>> - bool "Simple Reset Controller Driver" if COMPILE_TEST
>> + bool "Simple Reset Controller Driver"
>> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
>> help
>> This enables a simple reset controller driver for reset lines that
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] reset: simple: enable for ASPEED SoCs
2018-02-19 6:54 [PATCH 0/3] reset: simple: enable for ASPEED SoCs Joel Stanley
` (2 preceding siblings ...)
2018-02-19 6:54 ` [PATCH 3/3] reset: simple: Allow user selection of driver Joel Stanley
@ 2018-02-19 11:46 ` Philipp Zabel
3 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2018-02-19 11:46 UTC (permalink / raw)
To: Joel Stanley, Rob Herring, Mark Rutland, Andrew Jeffery
Cc: Lee Jones, devicetree, linux-kernel, linux-aspeed
Hi Joel,
On Mon, 2018-02-19 at 17:24 +1030, Joel Stanley wrote:
> Hello Philip,
>
> Here is a series that enables the simple reset driver for the ASPEED
> SoCs. You may recall I posted a patch back in May 2017 with a
> similar idea[1]. I was happy to see that you merged a driver that solves
> the problem, and suits our purpose for the ASPEED. Thanks!
Yes, sometimes it takes a few drivers to see what the common patterns
are. When it came to unify them, starting from one of the preexisting
drivers seemed like the straightforward thing to do.
regards
Philipp
^ permalink raw reply [flat|nested] 10+ messages in thread