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* [PATCH v1 0/4] Add EDAC driver for QCOM SoCs
@ 2018-08-01 20:33 Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
                   ` (3 more replies)
  0 siblings, 4 replies; 13+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-01 20:33 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp

This series implements EDAC driver for QCOM SoCs. As of now, this driver
supports EDAC for Last Level Cache Controller (LLCC). LLCC EDAC driver is
to detect and report single and double bit errors on Last Level Cache
Controller (LLCC) cache. This driver also takes care of dumping registers
and also adding config options to enable and disable panic when these
errors happen in LLCC.

The driver functionality is implemented in:
qcom_edac.c : This platform driver registers to edac framework and
handles the single and double bit errors in cache by registering
interrupt handlers.

llcc-slice.c: It invokes the llcc edac driver and passes platform
data to it.

This patchset depends on the LLCC driver, which is yet to be merged.
Link: https://patchwork.kernel.org/patch/10422531/
Link: http://lists-archives.com/linux-kernel/29157082-dt-bindings-documentation-for-qcom-llcc.html

Changes since v0:
  * Added EDAC_QCOM config and updated the driver
  * Addressed comments related to indentation and other minor ones

Channagoud Kadabi (1):
  drivers: edac: Add EDAC driver support for QCOM SoCs

Venkata Narendra Kumar Gutta (3):
  drivers: soc: Add broadcast base for Last Level Cache Controller
    (LLCC)
  drivers: soc: Add support to register LLCC EDAC driver
  dt-bindigs: Update documentation of qcom,llcc

 .../devicetree/bindings/arm/msm/qcom,llcc.txt      |  15 +-
 MAINTAINERS                                        |   7 +
 drivers/edac/Kconfig                               |  28 ++
 drivers/edac/Makefile                              |   1 +
 drivers/edac/qcom_edac.c                           | 507 +++++++++++++++++++++
 drivers/soc/qcom/llcc-slice.c                      |  73 ++-
 include/linux/soc/qcom/llcc-qcom.h                 |   6 +-
 7 files changed, 610 insertions(+), 27 deletions(-)
 create mode 100644 drivers/edac/qcom_edac.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)
  2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-01 20:33 ` Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 13+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-01 20:33 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp
  Cc: Venkata Narendra Kumar Gutta

Currently, boradcast base is set to end of the LLCC banks, which may
not be correct always. As the number of banks may vary for each chipset
and the broadcast base could be at a different address as well. This info
depends on the chipset, so get the broadcast base info from the device
tree (DT). Add broadcast base in LLCC driver and use this for broadcast
writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 55 +++++++++++++++++++++++---------------
 include/linux/soc/qcom/llcc-qcom.h |  4 +--
 2 files changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index fcaad1a..a63640d 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -105,22 +105,24 @@ static int llcc_update_act_ctrl(u32 sid,
 	u32 slice_status;
 	int ret;
 
-	act_ctrl_reg = drv_data->bcast_off + LLCC_TRP_ACT_CTRLn(sid);
-	status_reg = drv_data->bcast_off + LLCC_TRP_STATUSn(sid);
+	act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
+	status_reg = LLCC_TRP_STATUSn(sid);
 
 	/* Set the ACTIVE trigger */
 	act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
 	/* Clear the ACTIVE trigger */
 	act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
-	ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
+	ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
 				      slice_status, !(slice_status & status),
 				      0, LLCC_STATUS_READ_DELAY);
 	return ret;
@@ -225,16 +227,13 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	int ret;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
-	u32 bcast_off = drv_data->bcast_off;
 
 	sz = drv_data->cfg_size;
 	llcc_table = drv_data->cfg;
 
 	for (i = 0; i < sz; i++) {
-		attr1_cfg = bcast_off +
-				LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
-		attr0_cfg = bcast_off +
-				LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
+		attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
+		attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
 
 		attr1_val = llcc_table[i].cache_mode;
 		attr1_val |= llcc_table[i].probe_target_ways <<
@@ -259,10 +258,12 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 		attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
 		attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
 
-		ret = regmap_write(drv_data->regmap, attr1_cfg, attr1_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
+					attr1_val);
 		if (ret)
 			return ret;
-		ret = regmap_write(drv_data->regmap, attr0_cfg, attr0_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
+					attr0_val);
 		if (ret)
 			return ret;
 		if (llcc_table[i].activate_on_init) {
@@ -278,24 +279,36 @@ int qcom_llcc_probe(struct platform_device *pdev,
 {
 	u32 num_banks;
 	struct device *dev = &pdev->dev;
-	struct resource *res;
-	void __iomem *base;
+	struct resource *llcc_banks_res, *llcc_bcast_res;
+	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
 		return -ENOMEM;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	llcc_banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_base");
+	llcc_banks_base = devm_ioremap_resource(&pdev->dev, llcc_banks_res);
+	if (IS_ERR(llcc_banks_base))
+		return PTR_ERR(llcc_banks_base);
 
-	drv_data->regmap = devm_regmap_init_mmio(dev, base,
-					&llcc_regmap_config);
+	drv_data->regmap = devm_regmap_init_mmio(dev, llcc_banks_base,
+						&llcc_regmap_config);
 	if (IS_ERR(drv_data->regmap))
 		return PTR_ERR(drv_data->regmap);
 
+	llcc_bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_broadcast_base");
+	llcc_bcast_base = devm_ioremap_resource(&pdev->dev, llcc_bcast_res);
+	if (IS_ERR(llcc_bcast_base))
+		return PTR_ERR(llcc_bcast_base);
+
+	drv_data->bcast_regmap = devm_regmap_init_mmio(dev, llcc_bcast_base,
+							&llcc_regmap_config);
+	if (IS_ERR(drv_data->bcast_regmap))
+		return PTR_ERR(drv_data->bcast_regmap);
+
 	ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
 						&num_banks);
 	if (ret)
@@ -317,8 +330,6 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	for (i = 0; i < num_banks; i++)
 		drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
 
-	drv_data->bcast_off = num_banks * BANK_OFFSET_STRIDE;
-
 	drv_data->bitmap = devm_kcalloc(dev,
 	BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
 						GFP_KERNEL);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 7e3b9c6..c681e79 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -70,22 +70,22 @@ struct llcc_slice_config {
 /**
  * llcc_drv_data - Data associated with the llcc driver
  * @regmap: regmap associated with the llcc device
+ * @bcast_regmap: regmap associated with llcc broadcast offset
  * @cfg: pointer to the data structure for slice configuration
  * @lock: mutex associated with each slice
  * @cfg_size: size of the config data table
  * @max_slices: max slices as read from device tree
- * @bcast_off: Offset of the broadcast bank
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
+	struct regmap *bcast_regmap;
 	const struct llcc_slice_config *cfg;
 	struct mutex lock;
 	u32 cfg_size;
 	u32 max_slices;
-	u32 bcast_off;
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
@ 2018-08-01 20:33 ` Venkata Narendra Kumar Gutta
  2018-08-10 17:21   ` Evan Green
  2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
  3 siblings, 1 reply; 13+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-01 20:33 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp
  Cc: Venkata Narendra Kumar Gutta

Cache error reporting controller is to detect and report single
and double bit errors on Last Level Cache Controller (LLCC) cache.
Add required support to register LLCC EDAC driver as platform driver,
from LLCC driver.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 18 ++++++++++++++++--
 include/linux/soc/qcom/llcc-qcom.h |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index a63640d..09c8bb0 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	u32 attr0_val;
 	u32 max_cap_cacheline;
 	u32 sz;
-	int ret;
+	int ret = 0;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
 
@@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	struct resource *llcc_banks_res, *llcc_bcast_res;
 	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
+	struct platform_device *llcc_edac;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
@@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	mutex_init(&drv_data->lock);
 	platform_set_drvdata(pdev, drv_data);
 
-	return qcom_llcc_cfg_program(pdev);
+	ret = qcom_llcc_cfg_program(pdev);
+	if (ret)
+		return ret;
+
+	drv_data->ecc_irq = platform_get_irq(pdev, 0);
+	if (drv_data->ecc_irq >= 0) {
+		llcc_edac = platform_device_register_data(&pdev->dev,
+						"qcom_llcc_edac", -1, drv_data,
+						sizeof(*drv_data));
+		if (IS_ERR(llcc_edac))
+			dev_err(dev, "Failed to register llcc edac driver\n");
+	}
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_llcc_probe);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index c681e79..1a3bc25 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -78,6 +78,7 @@ struct llcc_slice_config {
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
+ * @ecc_irq: interrupt for llcc cache error detection and reporting
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
@@ -89,6 +90,7 @@ struct llcc_drv_data {
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
+	u32 ecc_irq;
 };
 
 #if IS_ENABLED(CONFIG_QCOM_LLCC)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
  2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
@ 2018-08-01 20:33 ` Venkata Narendra Kumar Gutta
  2018-08-08 23:11   ` vnkgutta
                     ` (2 more replies)
  2018-08-01 20:33 ` [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
  3 siblings, 3 replies; 13+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-01 20:33 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp
  Cc: Venkata Narendra Kumar Gutta

From: Channagoud Kadabi <ckadabi@codeaurora.org>

Add error reporting driver for SBEs and DBEs. As of now, this driver
supports erp for Last Level Cache Controller (LLCC). This driver takes
care of dumping registers and adding config options to enable and
disable panic when the errors happen in cache.

Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
---
 MAINTAINERS              |   7 +
 drivers/edac/Kconfig     |  28 +++
 drivers/edac/Makefile    |   1 +
 drivers/edac/qcom_edac.c | 507 +++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 543 insertions(+)
 create mode 100644 drivers/edac/qcom_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index f6a9b08..68b3484 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5227,6 +5227,13 @@ L:	linux-edac@vger.kernel.org
 S:	Maintained
 F:	drivers/edac/ti_edac.c
 
+EDAC-QUALCOMM
+M:	Channagoud Kadabi<ckadabi@codeaurora.org>
+M:	Venkata Narendra Kumar Gutta<vnkgutta@codeaurora.org>
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	drivers/edac/qcom_edac.c
+
 EDIROL UA-101/UA-1000 DRIVER
 M:	Clemens Ladisch <clemens@ladisch.de>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 57304b2..c654b0e 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,4 +460,32 @@ config EDAC_TI
 	  Support for error detection and correction on the
           TI SoCs.
 
+config EDAC_QCOM
+	depends on EDAC=y
+	tristate "QCOM EDAC Controller"
+	help
+		Support for error detection and correction on the
+		QCOM SoCs.
+
+config EDAC_QCOM_LLCC
+	depends on EDAC_QCOM=y && QCOM_LLCC
+	tristate "QCOM EDAC Controller for LLCC Cache"
+	help
+		Support for error detection and correction on the
+		QCOM LLCC cache. Report errors caught by LLCC ECC
+		mechanism.
+
+		For debugging issues having to do with stability and overall system
+		health, you should probably say 'Y' here.
+
+config EDAC_QCOM_LLCC_PANIC_ON_UE
+	depends on EDAC_QCOM_LLCC
+	bool "Panic on uncorrectable errors - qcom llcc"
+	help
+		Forcibly cause a kernel panic if an uncorrectable error (UE) is
+		detected. This can reduce debugging times on hardware which may be
+		operating at voltages or frequencies outside normal specification.
+
+		For production builds, you should probably say 'N' here.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 02b43a7..716096d 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
 obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
+obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
new file mode 100644
index 0000000..cf3e2b0
--- /dev/null
+++ b/drivers/edac/qcom_edac.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/edac.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+#include <linux/regmap.h>
+#include <linux/interrupt.h>
+#include <linux/soc/qcom/llcc-qcom.h>
+#include "edac_mc.h"
+#include "edac_device.h"
+
+#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
+#define LLCC_ERP_PANIC_ON_UE            1
+#else
+#define LLCC_ERP_PANIC_ON_UE            0
+#endif
+
+#define EDAC_LLCC                       "qcom_llcc"
+
+#define TRP_SYN_REG_CNT                 6
+
+#define DRP_SYN_REG_CNT                 8
+
+#define LLCC_COMMON_STATUS0             0x0003000C
+#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT               28
+
+/* single & Double Bit syndrome register offsets */
+#define TRP_ECC_SB_ERR_SYN0             0x0002304C
+#define TRP_ECC_DB_ERR_SYN0             0x00020370
+#define DRP_ECC_SB_ERR_SYN0             0x0004204C
+#define DRP_ECC_DB_ERR_SYN0             0x00042070
+
+/* Error register offsets */
+#define TRP_ECC_ERROR_STATUS1           0x00020348
+#define TRP_ECC_ERROR_STATUS0           0x00020344
+#define DRP_ECC_ERROR_STATUS1           0x00042048
+#define DRP_ECC_ERROR_STATUS0           0x00042044
+
+/* TRP, DRP interrupt register offsets */
+#define DRP_INTERRUPT_STATUS            0x00041000
+#define TRP_INTERRUPT_0_STATUS          0x00020480
+#define DRP_INTERRUPT_CLEAR             0x00041008
+#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
+#define TRP_INTERRUPT_0_CLEAR           0x00020484
+#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
+
+/* Mask and shift macros */
+#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
+#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
+#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
+
+#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
+#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
+#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
+
+#define SB_ECC_ERROR                    BIT(0)
+#define DB_ECC_ERROR                    BIT(1)
+
+#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
+#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
+
+/* Config registers offsets*/
+#define DRP_ECC_ERROR_CFG               0x00040000
+
+/* TRP, DRP interrupt register offsets */
+#define CMN_INTERRUPT_0_ENABLE          0x0003001C
+#define CMN_INTERRUPT_2_ENABLE          0x0003003C
+#define TRP_INTERRUPT_0_ENABLE          0x00020488
+#define DRP_INTERRUPT_ENABLE            0x0004100C
+
+#define SB_ERROR_THRESHOLD              0x1
+#define SB_ERROR_THRESHOLD_SHIFT        24
+#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
+#define TRP0_INTERRUPT_ENABLE           0x1
+#define DRP0_INTERRUPT_ENABLE           BIT(6)
+#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
+
+
+enum {
+	LLCC_DRAM_CE = 0,
+	LLCC_DRAM_UE,
+	LLCC_TRAM_CE,
+	LLCC_TRAM_UE,
+};
+
+struct errors_edac {
+	const char *msg;
+	void (*func)(struct edac_device_ctl_info *edev_ctl,
+				int inst_nr, int block_nr, const char *msg);
+};
+
+static const struct errors_edac errors[] = {
+	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
+	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
+	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
+	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
+};
+
+static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
+{
+	u32 sb_err_threshold;
+	int ret;
+
+	/* Enable TRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				 TRP0_INTERRUPT_ENABLE,
+				 TRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Tag Ram */
+	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
+				 SB_DB_TRP_INTERRUPT_ENABLE,
+				 SB_DB_TRP_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable SB error for Data RAM */
+	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
+	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
+			   sb_err_threshold);
+	if (ret)
+		return ret;
+
+	/* Enable DRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				 DRP0_INTERRUPT_ENABLE,
+				 DRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Data Ram */
+	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
+			   SB_DB_DRP_INTERRUPT_ENABLE);
+	return ret;
+}
+
+/* Clear the error interrupt and counter registers */
+static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data *drv)
+{
+	int ret = 0;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+	case LLCC_DRAM_UE:
+		/* Clear the interrupt */
+		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
+				   DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		/* Clear the counters */
+		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
+				   DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	case LLCC_TRAM_CE:
+	case LLCC_TRAM_UE:
+		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
+				   DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
+				   DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	}
+	return ret;
+}
+
+/* Dump syndrome registers for tag Ram Double bit errors */
+static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int db_err_cnt, db_err_ways, ret, i;
+	u32 synd_reg, synd_val;
+
+	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
+		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				  &synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
+			    i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
+			  &db_err_cnt);
+	if (ret)
+		return ret;
+	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
+		    db_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
+			  &db_err_ways);
+	if (ret)
+		return ret;
+	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
+	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
+		    db_err_ways);
+
+	return ret;
+}
+
+/* Dump syndrome register for tag Ram Single Bit Errors */
+static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int sb_err_cnt, sb_err_ways, ret, i;
+	u32 synd_reg, synd_val;
+
+	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
+		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				  &synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i,
+			    synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
+			  &sb_err_cnt);
+	if (ret)
+		return ret;
+	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
+	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
+		    sb_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
+			  &sb_err_ways);
+	if (ret)
+		return ret;
+
+	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
+		    sb_err_ways);
+
+	return ret;
+}
+
+/* Dump syndrome registers for Data Ram Double bit errors */
+static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int db_err_cnt, db_err_ways, ret, i;
+	u32 synd_reg, synd_val;
+
+	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
+		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				  &synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
+			    synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
+			  &db_err_cnt);
+	if (ret)
+		return ret;
+	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
+		    db_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
+			  &db_err_ways);
+	if (ret)
+		return ret;
+	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
+	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
+		    db_err_ways);
+
+	return ret;
+}
+
+/* Dump Syndrome registers for Data Ram Single bit errors*/
+static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int sb_err_cnt, sb_err_ways, ret, i;
+	u32 synd_reg, synd_val;
+
+	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
+		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				  &synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
+			    synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
+			  &sb_err_cnt);
+	if (ret)
+		return ret;
+	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
+	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
+		    sb_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
+			  &sb_err_ways);
+	if (ret)
+		return ret;
+	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
+		    sb_err_ways);
+
+	return ret;
+}
+
+static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
+			 int err_type, u32 bank)
+{
+	struct llcc_drv_data *drv = edev_ctl->pvt_info;
+	int ret = 0;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+		ret = dump_drp_sb_syn_reg(drv, bank);
+		break;
+	case LLCC_DRAM_UE:
+		ret = dump_drp_db_syn_reg(drv, bank);
+		break;
+	case LLCC_TRAM_CE:
+		ret = dump_trp_sb_syn_reg(drv, bank);
+		break;
+	case LLCC_TRAM_UE:
+		ret = dump_trp_db_syn_reg(drv, bank);
+		break;
+	}
+	if (ret)
+		return ret;
+
+	ret = qcom_llcc_clear_errors(err_type, drv);
+	if (ret)
+		return ret;
+
+	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
+
+	return ret;
+}
+
+static irqreturn_t
+llcc_ecc_irq_handler (int irq, void *edev_ctl)
+{
+	struct edac_device_ctl_info *edac_dev_ctl;
+	irqreturn_t irq_rc = IRQ_NONE;
+	u32 drp_error, trp_error, i;
+	struct llcc_drv_data *drv;
+	int ret;
+
+	edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
+	drv = edac_dev_ctl->pvt_info;
+
+	for (i = 0; i < drv->num_banks; i++) {
+		/* Look for Data RAM errors */
+		ret = regmap_read(drv->regmap,
+				  drv->offsets[i] + DRP_INTERRUPT_STATUS,
+				  &drp_error);
+		if (ret)
+			return irq_rc;
+
+		if (drp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Single Bit Error detected in Data Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
+			irq_rc = IRQ_HANDLED;
+		} else if (drp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Double Bit Error detected in Data Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
+			irq_rc = IRQ_HANDLED;
+		}
+
+		/* Look for Tag RAM errors */
+		ret = regmap_read(drv->regmap,
+				  drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
+				  &trp_error);
+		if (ret)
+			return irq_rc;
+		if (trp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Single Bit Error detected in Tag Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
+			irq_rc = IRQ_HANDLED;
+		} else if (trp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Double Bit Error detected in Tag Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
+			irq_rc = IRQ_HANDLED;
+		}
+	}
+
+	return irq_rc;
+}
+
+static int qcom_llcc_edac_probe(struct platform_device *pdev)
+{
+	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
+	struct edac_device_ctl_info *edev_ctl;
+	struct device *dev = &pdev->dev;
+	u32 ecc_irq;
+	int rc;
+
+	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
+	if (rc)
+		return rc;
+
+	/* Allocate edac control info */
+	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
+					      llcc_driv_data->num_banks, 1,
+					      NULL, 0,
+					      edac_device_alloc_index());
+
+	if (!edev_ctl)
+		return -ENOMEM;
+
+	edev_ctl->dev = dev;
+	edev_ctl->mod_name = dev_name(dev);
+	edev_ctl->dev_name = dev_name(dev);
+	edev_ctl->ctl_name = "llcc";
+	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
+
+	edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data;
+
+	rc = edac_device_add_device(edev_ctl);
+	if (rc)
+		goto out_mem;
+
+	platform_set_drvdata(pdev, edev_ctl);
+
+	/* Request for ecc irq */
+	ecc_irq = llcc_driv_data->ecc_irq;
+	if (!ecc_irq) {
+		rc = -ENODEV;
+		goto out_dev;
+	}
+	rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
+			      IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
+	if (rc)
+		goto out_dev;
+
+	return rc;
+
+out_dev:
+	edac_device_del_device(edev_ctl->dev);
+out_mem:
+	edac_device_free_ctl_info(edev_ctl);
+
+	return rc;
+}
+
+static int qcom_llcc_edac_remove(struct platform_device *pdev)
+{
+	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
+
+	edac_device_del_device(edev_ctl->dev);
+	edac_device_free_ctl_info(edev_ctl);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+#ifdef EDAC_QCOM_LLCC
+	{ .compatible = "qcom,llcc-edac" },
+#endif
+	{ },
+};
+
+static struct platform_driver qcom_llcc_edac_driver = {
+	.probe = qcom_llcc_edac_probe,
+	.remove = qcom_llcc_edac_remove,
+	.driver = {
+		.name = "qcom_llcc_edac",
+		.of_match_table = qcom_llcc_edac_match_table,
+	},
+};
+module_platform_driver(qcom_llcc_edac_driver);
+
+MODULE_DESCRIPTION("QCOM EDAC driver");
+MODULE_LICENSE("GPL v2");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc
  2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
                   ` (2 preceding siblings ...)
  2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-01 20:33 ` Venkata Narendra Kumar Gutta
  3 siblings, 0 replies; 13+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-01 20:33 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp
  Cc: Venkata Narendra Kumar Gutta

Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
 	Value Type: <prop-encoded-array>
 	Definition: Start address and the the size of the register region.
 
+- reg-names:
+        Usage: required
+        Value Type: <stringlist>
+        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+	Usage: required
+	Definition: The interrupt is associated with the llcc edac device.
+			It's used for llcc cache single and double bit error detection
+			and reporting.
+
 Example:
 
 	cache-controller@1100000 {
 		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x250000>;
+		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+		reg-names = "llcc_base", "llcc_bcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-08 23:11   ` vnkgutta
  2018-08-10  3:59   ` Borislav Petkov
  2018-08-10 17:23   ` Evan Green
  2 siblings, 0 replies; 13+ messages in thread
From: vnkgutta @ 2018-08-08 23:11 UTC (permalink / raw)
  To: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb, bp


Reminder. Would someone review this EDAC patch series?

Thanks,
Narendra

On 2018-08-01 13:33, Venkata Narendra Kumar Gutta wrote:
> From: Channagoud Kadabi <ckadabi@codeaurora.org>
> 
> Add error reporting driver for SBEs and DBEs. As of now, this driver
> supports erp for Last Level Cache Controller (LLCC). This driver takes
> care of dumping registers and adding config options to enable and
> disable panic when the errors happen in cache.
> 
> Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> ---
>  MAINTAINERS              |   7 +
>  drivers/edac/Kconfig     |  28 +++
>  drivers/edac/Makefile    |   1 +
>  drivers/edac/qcom_edac.c | 507 
> +++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 543 insertions(+)
>  create mode 100644 drivers/edac/qcom_edac.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f6a9b08..68b3484 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5227,6 +5227,13 @@ L:	linux-edac@vger.kernel.org
>  S:	Maintained
>  F:	drivers/edac/ti_edac.c
> 
> +EDAC-QUALCOMM
> +M:	Channagoud Kadabi<ckadabi@codeaurora.org>
> +M:	Venkata Narendra Kumar Gutta<vnkgutta@codeaurora.org>
> +L:	linux-arm-msm@vger.kernel.org
> +S:	Maintained
> +F:	drivers/edac/qcom_edac.c
> +
>  EDIROL UA-101/UA-1000 DRIVER
>  M:	Clemens Ladisch <clemens@ladisch.de>
>  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 57304b2..c654b0e 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -460,4 +460,32 @@ config EDAC_TI
>  	  Support for error detection and correction on the
>            TI SoCs.
> 
> +config EDAC_QCOM
> +	depends on EDAC=y
> +	tristate "QCOM EDAC Controller"
> +	help
> +		Support for error detection and correction on the
> +		QCOM SoCs.
> +
> +config EDAC_QCOM_LLCC
> +	depends on EDAC_QCOM=y && QCOM_LLCC
> +	tristate "QCOM EDAC Controller for LLCC Cache"
> +	help
> +		Support for error detection and correction on the
> +		QCOM LLCC cache. Report errors caught by LLCC ECC
> +		mechanism.
> +
> +		For debugging issues having to do with stability and overall system
> +		health, you should probably say 'Y' here.
> +
> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> +	depends on EDAC_QCOM_LLCC
> +	bool "Panic on uncorrectable errors - qcom llcc"
> +	help
> +		Forcibly cause a kernel panic if an uncorrectable error (UE) is
> +		detected. This can reduce debugging times on hardware which may be
> +		operating at voltages or frequencies outside normal specification.
> +
> +		For production builds, you should probably say 'N' here.
> +
>  endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 02b43a7..716096d 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
>  obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
>  obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
>  obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
> +obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> new file mode 100644
> index 0000000..cf3e2b0
> --- /dev/null
> +++ b/drivers/edac/qcom_edac.c
> @@ -0,0 +1,507 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/edac.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +#include <linux/regmap.h>
> +#include <linux/interrupt.h>
> +#include <linux/soc/qcom/llcc-qcom.h>
> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE            1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE            0
> +#endif
> +
> +#define EDAC_LLCC                       "qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT                 6
> +
> +#define DRP_SYN_REG_CNT                 8
> +
> +#define LLCC_COMMON_STATUS0             0x0003000C
> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT               28
> +
> +/* single & Double Bit syndrome register offsets */
> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS            0x00041000
> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> +#define DRP_INTERRUPT_CLEAR             0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR                    BIT(0)
> +#define DB_ECC_ERROR                    BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG               0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD              0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE           0x1
> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +
> +enum {
> +	LLCC_DRAM_CE = 0,
> +	LLCC_DRAM_UE,
> +	LLCC_TRAM_CE,
> +	LLCC_TRAM_UE,
> +};
> +
> +struct errors_edac {
> +	const char *msg;
> +	void (*func)(struct edac_device_ctl_info *edev_ctl,
> +				int inst_nr, int block_nr, const char *msg);
> +};
> +
> +static const struct errors_edac errors[] = {
> +	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
> +	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
> +};
> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +	u32 sb_err_threshold;
> +	int ret;
> +
> +	/* Enable TRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				 TRP0_INTERRUPT_ENABLE,
> +				 TRP0_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Tag Ram */
> +	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +				 SB_DB_TRP_INTERRUPT_ENABLE,
> +				 SB_DB_TRP_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable SB error for Data RAM */
> +	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +			   sb_err_threshold);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable DRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				 DRP0_INTERRUPT_ENABLE,
> +				 DRP0_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Data Ram */
> +	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +			   SB_DB_DRP_INTERRUPT_ENABLE);
> +	return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data 
> *drv)
> +{
> +	int ret = 0;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +	case LLCC_DRAM_UE:
> +		/* Clear the interrupt */
> +		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +				   DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		/* Clear the counters */
> +		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +				   DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	case LLCC_TRAM_CE:
> +	case LLCC_TRAM_UE:
> +		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +				   DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +				   DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	}
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for tag Ram Double bit errors */
> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int db_err_cnt, db_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
> +			    i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +			  &db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		    db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +			  &db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		    db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome register for tag Ram Single Bit Errors */
> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int sb_err_cnt, sb_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +			  &sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		    sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +			  &sb_err_ways);
> +	if (ret)
> +		return ret;
> +
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +		    sb_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for Data Ram Double bit errors */
> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int db_err_cnt, db_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +			  &db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		    db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +			  &db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		    db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump Syndrome registers for Data Ram Single bit errors*/
> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int sb_err_cnt, sb_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +			  &sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		    sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +			  &sb_err_ways);
> +	if (ret)
> +		return ret;
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +		    sb_err_ways);
> +
> +	return ret;
> +}
> +
> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
> +			 int err_type, u32 bank)
> +{
> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +	int ret = 0;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +		ret = dump_drp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_DRAM_UE:
> +		ret = dump_drp_db_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_CE:
> +		ret = dump_trp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_UE:
> +		ret = dump_trp_db_syn_reg(drv, bank);
> +		break;
> +	}
> +	if (ret)
> +		return ret;
> +
> +	ret = qcom_llcc_clear_errors(err_type, drv);
> +	if (ret)
> +		return ret;
> +
> +	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
> +
> +	return ret;
> +}
> +
> +static irqreturn_t
> +llcc_ecc_irq_handler (int irq, void *edev_ctl)
> +{
> +	struct edac_device_ctl_info *edac_dev_ctl;
> +	irqreturn_t irq_rc = IRQ_NONE;
> +	u32 drp_error, trp_error, i;
> +	struct llcc_drv_data *drv;
> +	int ret;
> +
> +	edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
> +	drv = edac_dev_ctl->pvt_info;
> +
> +	for (i = 0; i < drv->num_banks; i++) {
> +		/* Look for Data RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				  drv->offsets[i] + DRP_INTERRUPT_STATUS,
> +				  &drp_error);
> +		if (ret)
> +			return irq_rc;
> +
> +		if (drp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Single Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (drp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Double Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +
> +		/* Look for Tag RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				  drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
> +				  &trp_error);
> +		if (ret)
> +			return irq_rc;
> +		if (trp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Single Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (trp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Double Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +	}
> +
> +	return irq_rc;
> +}
> +
> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
> +{
> +	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> +	struct edac_device_ctl_info *edev_ctl;
> +	struct device *dev = &pdev->dev;
> +	u32 ecc_irq;
> +	int rc;
> +
> +	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
> +	if (rc)
> +		return rc;
> +
> +	/* Allocate edac control info */
> +	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
> +					      llcc_driv_data->num_banks, 1,
> +					      NULL, 0,
> +					      edac_device_alloc_index());
> +
> +	if (!edev_ctl)
> +		return -ENOMEM;
> +
> +	edev_ctl->dev = dev;
> +	edev_ctl->mod_name = dev_name(dev);
> +	edev_ctl->dev_name = dev_name(dev);
> +	edev_ctl->ctl_name = "llcc";
> +	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
> +
> +	edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data;
> +
> +	rc = edac_device_add_device(edev_ctl);
> +	if (rc)
> +		goto out_mem;
> +
> +	platform_set_drvdata(pdev, edev_ctl);
> +
> +	/* Request for ecc irq */
> +	ecc_irq = llcc_driv_data->ecc_irq;
> +	if (!ecc_irq) {
> +		rc = -ENODEV;
> +		goto out_dev;
> +	}
> +	rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
> +			      IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
> +	if (rc)
> +		goto out_dev;
> +
> +	return rc;
> +
> +out_dev:
> +	edac_device_del_device(edev_ctl->dev);
> +out_mem:
> +	edac_device_free_ctl_info(edev_ctl);
> +
> +	return rc;
> +}
> +
> +static int qcom_llcc_edac_remove(struct platform_device *pdev)
> +{
> +	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
> +
> +	edac_device_del_device(edev_ctl->dev);
> +	edac_device_free_ctl_info(edev_ctl);
> +	platform_set_drvdata(pdev, NULL);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id qcom_llcc_edac_match_table[] = {
> +#ifdef EDAC_QCOM_LLCC
> +	{ .compatible = "qcom,llcc-edac" },
> +#endif
> +	{ },
> +};
> +
> +static struct platform_driver qcom_llcc_edac_driver = {
> +	.probe = qcom_llcc_edac_probe,
> +	.remove = qcom_llcc_edac_remove,
> +	.driver = {
> +		.name = "qcom_llcc_edac",
> +		.of_match_table = qcom_llcc_edac_match_table,
> +	},
> +};
> +module_platform_driver(qcom_llcc_edac_driver);
> +
> +MODULE_DESCRIPTION("QCOM EDAC driver");
> +MODULE_LICENSE("GPL v2");

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-08 23:11   ` vnkgutta
@ 2018-08-10  3:59   ` Borislav Petkov
  2018-08-10 23:03     ` vnkgutta
  2018-08-10 17:23   ` Evan Green
  2 siblings, 1 reply; 13+ messages in thread
From: Borislav Petkov @ 2018-08-10  3:59 UTC (permalink / raw)
  To: Venkata Narendra Kumar Gutta
  Cc: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb

On Wed, Aug 01, 2018 at 01:33:34PM -0700, Venkata Narendra Kumar Gutta wrote:
> From: Channagoud Kadabi <ckadabi@codeaurora.org>
> 
> Add error reporting driver for SBEs and DBEs. As of now, this driver

Please write out those abbreviations.

> supports erp for Last Level Cache Controller (LLCC). This driver takes
> care of dumping registers and adding config options to enable and
> disable panic when the errors happen in cache.
> 
> Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>

The proper order is:

SOB: Author
SOB: Sender/handler/...

So:

Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>

> ---
>  MAINTAINERS              |   7 +
>  drivers/edac/Kconfig     |  28 +++
>  drivers/edac/Makefile    |   1 +
>  drivers/edac/qcom_edac.c | 507 +++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 543 insertions(+)
>  create mode 100644 drivers/edac/qcom_edac.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f6a9b08..68b3484 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5227,6 +5227,13 @@ L:	linux-edac@vger.kernel.org
>  S:	Maintained
>  F:	drivers/edac/ti_edac.c
>  
> +EDAC-QUALCOMM
> +M:	Channagoud Kadabi<ckadabi@codeaurora.org>
> +M:	Venkata Narendra Kumar Gutta<vnkgutta@codeaurora.org>

Space between name and email address.

> +L:	linux-arm-msm@vger.kernel.org

Also

L:      linux-edac@vger.kernel.org

so that the EDAC ML gets CCed too.

> +S:	Maintained
> +F:	drivers/edac/qcom_edac.c
> +
>  EDIROL UA-101/UA-1000 DRIVER
>  M:	Clemens Ladisch <clemens@ladisch.de>
>  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 57304b2..c654b0e 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -460,4 +460,32 @@ config EDAC_TI
>  	  Support for error detection and correction on the
>            TI SoCs.
>  
> +config EDAC_QCOM
> +	depends on EDAC=y

Why on EDAC=y? Did you blindly copy it or is there a reason why
edac_core should be only built-in or can it be a module too?

> +	tristate "QCOM EDAC Controller"
> +	help
> +		Support for error detection and correction on the
> +		QCOM SoCs.
> +
> +config EDAC_QCOM_LLCC
> +	depends on EDAC_QCOM=y && QCOM_LLCC
> +	tristate "QCOM EDAC Controller for LLCC Cache"
> +	help
> +		Support for error detection and correction on the
> +		QCOM LLCC cache. Report errors caught by LLCC ECC
> +		mechanism.
> +
> +		For debugging issues having to do with stability and overall system
> +		health, you should probably say 'Y' here.
> +
> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> +	depends on EDAC_QCOM_LLCC
> +	bool "Panic on uncorrectable errors - qcom llcc"
> +	help
> +		Forcibly cause a kernel panic if an uncorrectable error (UE) is
> +		detected. This can reduce debugging times on hardware which may be
> +		operating at voltages or frequencies outside normal specification.
> +
> +		For production builds, you should probably say 'N' here.
> +
>  endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 02b43a7..716096d 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
>  obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
>  obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
>  obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
> +obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> new file mode 100644
> index 0000000..cf3e2b0
> --- /dev/null
> +++ b/drivers/edac/qcom_edac.c
> @@ -0,0 +1,507 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/edac.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +#include <linux/regmap.h>
> +#include <linux/interrupt.h>
> +#include <linux/soc/qcom/llcc-qcom.h>
> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE            1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE            0
> +#endif
> +
> +#define EDAC_LLCC                       "qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT                 6
> +
> +#define DRP_SYN_REG_CNT                 8
> +
> +#define LLCC_COMMON_STATUS0             0x0003000C
> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT               28
> +
> +/* single & Double Bit syndrome register offsets */
> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS            0x00041000
> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> +#define DRP_INTERRUPT_CLEAR             0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR                    BIT(0)
> +#define DB_ECC_ERROR                    BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG               0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD              0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE           0x1
> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +
> +enum {
> +	LLCC_DRAM_CE = 0,
> +	LLCC_DRAM_UE,
> +	LLCC_TRAM_CE,
> +	LLCC_TRAM_UE,
> +};
> +
> +struct errors_edac {
> +	const char *msg;
> +	void (*func)(struct edac_device_ctl_info *edev_ctl,
> +				int inst_nr, int block_nr, const char *msg);
> +};
> +
> +static const struct errors_edac errors[] = {
> +	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
> +	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
> +};

An array of function pointers just for two functions?! This looks silly.
Just do a simple if-else.

> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +	u32 sb_err_threshold;
> +	int ret;
> +
> +	/* Enable TRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				 TRP0_INTERRUPT_ENABLE,
> +				 TRP0_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Tag Ram */
> +	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +				 SB_DB_TRP_INTERRUPT_ENABLE,
> +				 SB_DB_TRP_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable SB error for Data RAM */
> +	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +			   sb_err_threshold);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable DRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				 DRP0_INTERRUPT_ENABLE,
> +				 DRP0_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Data Ram */
> +	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +			   SB_DB_DRP_INTERRUPT_ENABLE);
> +	return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data *drv)
> +{
> +	int ret = 0;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +	case LLCC_DRAM_UE:
> +		/* Clear the interrupt */
> +		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +				   DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		/* Clear the counters */
> +		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +				   DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	case LLCC_TRAM_CE:
> +	case LLCC_TRAM_UE:
> +		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +				   DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +				   DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	}
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for tag Ram Double bit errors */
> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int db_err_cnt, db_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
> +			    i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +			  &db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		    db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +			  &db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		    db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome register for tag Ram Single Bit Errors */
> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int sb_err_cnt, sb_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +			  &sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		    sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +			  &sb_err_ways);
> +	if (ret)
> +		return ret;
> +
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +		    sb_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for Data Ram Double bit errors */
> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int db_err_cnt, db_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +			  &db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		    db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +			  &db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		    db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump Syndrome registers for Data Ram Single bit errors*/
> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int sb_err_cnt, sb_err_ways, ret, i;
> +	u32 synd_reg, synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				  &synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +			    synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +			  &sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		    sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +			  &sb_err_ways);
> +	if (ret)
> +		return ret;
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +		    sb_err_ways);
> +
> +	return ret;
> +}
> +
> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
> +			 int err_type, u32 bank)
> +{
> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +	int ret = 0;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +		ret = dump_drp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_DRAM_UE:
> +		ret = dump_drp_db_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_CE:
> +		ret = dump_trp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_UE:
> +		ret = dump_trp_db_syn_reg(drv, bank);

So those functions look very similar to one another and thus are
quadrupled object code. You could have one function instead and pass
in the register as an arg. Or some other smarter scheme to save object
size...

> +		break;
> +	}
> +	if (ret)
> +		return ret;
> +
> +	ret = qcom_llcc_clear_errors(err_type, drv);
> +	if (ret)
> +		return ret;
> +
> +	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
> +
> +	return ret;
> +}
> +
> +static irqreturn_t
> +llcc_ecc_irq_handler (int irq, void *edev_ctl)

Stray " " after function name.

> +{
> +	struct edac_device_ctl_info *edac_dev_ctl;
> +	irqreturn_t irq_rc = IRQ_NONE;
> +	u32 drp_error, trp_error, i;
> +	struct llcc_drv_data *drv;
> +	int ret;
> +
> +	edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
> +	drv = edac_dev_ctl->pvt_info;
> +
> +	for (i = 0; i < drv->num_banks; i++) {
> +		/* Look for Data RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				  drv->offsets[i] + DRP_INTERRUPT_STATUS,
> +				  &drp_error);
> +		if (ret)
> +			return irq_rc;
> +
> +		if (drp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Single Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (drp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Double Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +
> +		/* Look for Tag RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				  drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
> +				  &trp_error);
> +		if (ret)
> +			return irq_rc;
> +		if (trp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Single Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (trp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				    "Double Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +	}
> +
> +	return irq_rc;
> +}
> +
> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
> +{
> +	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> +	struct edac_device_ctl_info *edev_ctl;
> +	struct device *dev = &pdev->dev;
> +	u32 ecc_irq;
> +	int rc;
> +
> +	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
> +	if (rc)
> +		return rc;
> +
> +	/* Allocate edac control info */
> +	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
> +					      llcc_driv_data->num_banks, 1,
> +					      NULL, 0,
> +					      edac_device_alloc_index());
> +
> +	if (!edev_ctl)
> +		return -ENOMEM;
> +
> +	edev_ctl->dev = dev;
> +	edev_ctl->mod_name = dev_name(dev);
> +	edev_ctl->dev_name = dev_name(dev);
> +	edev_ctl->ctl_name = "llcc";
> +	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
> +
> +	edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data;

Why is that cast needed?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
@ 2018-08-10 17:21   ` Evan Green
  2018-08-10 23:04     ` vnkgutta
  0 siblings, 1 reply; 13+ messages in thread
From: Evan Green @ 2018-08-10 17:21 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> Cache error reporting controller is to detect and report single
> and double bit errors on Last Level Cache Controller (LLCC) cache.
> Add required support to register LLCC EDAC driver as platform driver,
> from LLCC driver.
>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> ---
>  drivers/soc/qcom/llcc-slice.c      | 18 ++++++++++++++++--
>  include/linux/soc/qcom/llcc-qcom.h |  2 ++
>  2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
> index a63640d..09c8bb0 100644
> --- a/drivers/soc/qcom/llcc-slice.c
> +++ b/drivers/soc/qcom/llcc-slice.c
> @@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
>         u32 attr0_val;
>         u32 max_cap_cacheline;
>         u32 sz;
> -       int ret;
> +       int ret = 0;
>         const struct llcc_slice_config *llcc_table;
>         struct llcc_slice_desc desc;
>
> @@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
>         struct resource *llcc_banks_res, *llcc_bcast_res;
>         void __iomem *llcc_banks_base, *llcc_bcast_base;
>         int ret, i;
> +       struct platform_device *llcc_edac;
>
>         drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
>         if (!drv_data)
> @@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
>         mutex_init(&drv_data->lock);
>         platform_set_drvdata(pdev, drv_data);
>
> -       return qcom_llcc_cfg_program(pdev);
> +       ret = qcom_llcc_cfg_program(pdev);
> +       if (ret)
> +               return ret;
> +
> +       drv_data->ecc_irq = platform_get_irq(pdev, 0);
> +       if (drv_data->ecc_irq >= 0) {

This condition will always be true for u32. See below...

> +               llcc_edac = platform_device_register_data(&pdev->dev,
> +                                               "qcom_llcc_edac", -1, drv_data,
> +                                               sizeof(*drv_data));
> +               if (IS_ERR(llcc_edac))
> +                       dev_err(dev, "Failed to register llcc edac driver\n");
> +       }
> +
> +       return ret;
>  }
>  EXPORT_SYMBOL_GPL(qcom_llcc_probe);
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index c681e79..1a3bc25 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -78,6 +78,7 @@ struct llcc_slice_config {
>   * @num_banks: Number of llcc banks
>   * @bitmap: Bit map to track the active slice ids
>   * @offsets: Pointer to the bank offsets array
> + * @ecc_irq: interrupt for llcc cache error detection and reporting
>   */
>  struct llcc_drv_data {
>         struct regmap *regmap;
> @@ -89,6 +90,7 @@ struct llcc_drv_data {
>         u32 num_banks;
>         unsigned long *bitmap;
>         u32 *offsets;
> +       u32 ecc_irq;

The return type for platform_get_irq is int, so this should probably
be int, or "unsigned", but then you'd need to fix your logic above.

>  };
>
>  #if IS_ENABLED(CONFIG_QCOM_LLCC)
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-08 23:11   ` vnkgutta
  2018-08-10  3:59   ` Borislav Petkov
@ 2018-08-10 17:23   ` Evan Green
  2018-08-10 23:13     ` vnkgutta
  2 siblings, 1 reply; 13+ messages in thread
From: Evan Green @ 2018-08-10 17:23 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>
> Add error reporting driver for SBEs and DBEs. As of now, this driver
> supports erp for Last Level Cache Controller (LLCC). This driver takes
> care of dumping registers and adding config options to enable and
> disable panic when the errors happen in cache.
>
> Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> ---
>  MAINTAINERS              |   7 +
>  drivers/edac/Kconfig     |  28 +++
>  drivers/edac/Makefile    |   1 +
>  drivers/edac/qcom_edac.c | 507 +++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 543 insertions(+)
>  create mode 100644 drivers/edac/qcom_edac.c
>
...
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> new file mode 100644
> index 0000000..cf3e2b0
> --- /dev/null
> +++ b/drivers/edac/qcom_edac.c
> @@ -0,0 +1,507 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/edac.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +#include <linux/regmap.h>
> +#include <linux/interrupt.h>
> +#include <linux/soc/qcom/llcc-qcom.h>

Please alphabetize these includes, and remove any unneeded ones.

> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE            1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE            0
> +#endif
> +
> +#define EDAC_LLCC                       "qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT                 6
> +
> +#define DRP_SYN_REG_CNT                 8
> +
> +#define LLCC_COMMON_STATUS0             0x0003000C
> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT               28
> +
> +/* single & Double Bit syndrome register offsets */
> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS            0x00041000
> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> +#define DRP_INTERRUPT_CLEAR             0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR                    BIT(0)
> +#define DB_ECC_ERROR                    BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG               0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD              0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE           0x1
> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +
> +enum {
> +       LLCC_DRAM_CE = 0,
> +       LLCC_DRAM_UE,
> +       LLCC_TRAM_CE,
> +       LLCC_TRAM_UE,
> +};
> +
> +struct errors_edac {
> +       const char *msg;
> +       void (*func)(struct edac_device_ctl_info *edev_ctl,
> +                               int inst_nr, int block_nr, const char *msg);
> +};
> +
> +static const struct errors_edac errors[] = {
> +       {"LLCC Data RAM correctable Error", edac_device_handle_ce},
> +       {"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
> +       {"LLCC Tag RAM correctable Error", edac_device_handle_ce},
> +       {"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
> +};
> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +       u32 sb_err_threshold;
> +       int ret;
> +
> +       /* Enable TRP in instance 2 of common interrupt enable register */
> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Tag Ram */
> +       ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable SB error for Data RAM */
> +       sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +                          sb_err_threshold);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable DRP in instance 2 of common interrupt enable register */
> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Data Ram */
> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +                          SB_DB_DRP_INTERRUPT_ENABLE);
> +       return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data *drv)
> +{
> +       int ret = 0;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +       case LLCC_DRAM_UE:
> +               /* Clear the interrupt */
> +               ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               /* Clear the counters */
> +               ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;
> +       case LLCC_TRAM_CE:
> +       case LLCC_TRAM_UE:
> +               ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;
> +       }
> +       return ret;
> +}
> +
> +/* Dump syndrome registers for tag Ram Double bit errors */
> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +       int db_err_cnt, db_err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +               synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       return ret;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
> +                           i, synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +                         &db_err_cnt);
> +       if (ret)
> +               return ret;
> +       db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +                   db_err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +                         &db_err_ways);
> +       if (ret)
> +               return ret;
> +       db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
> +       db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +                   db_err_ways);
> +
> +       return ret;
> +}
> +
> +/* Dump syndrome register for tag Ram Single Bit Errors */
> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +       int sb_err_cnt, sb_err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +               synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       return ret;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i,
> +                           synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +                         &sb_err_cnt);
> +       if (ret)
> +               return ret;
> +       sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
> +       sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +                   sb_err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +                         &sb_err_ways);
> +       if (ret)
> +               return ret;
> +
> +       sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +                   sb_err_ways);
> +
> +       return ret;
> +}
> +
> +/* Dump syndrome registers for Data Ram Double bit errors */
> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +       int db_err_cnt, db_err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +               synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       return ret;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +                           synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +                         &db_err_cnt);
> +       if (ret)
> +               return ret;
> +       db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +                   db_err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +                         &db_err_ways);
> +       if (ret)
> +               return ret;
> +       db_err_ways &= ECC_DB_ERR_WAYS_MASK;
> +       db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +                   db_err_ways);
> +
> +       return ret;
> +}
> +
> +/* Dump Syndrome registers for Data Ram Single bit errors*/
> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +       int sb_err_cnt, sb_err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +               synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       return ret;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
> +                           synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +                         &sb_err_cnt);
> +       if (ret)
> +               return ret;
> +       sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
> +       sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +                   sb_err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +                         &sb_err_ways);
> +       if (ret)
> +               return ret;
> +       sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +                   sb_err_ways);
> +
> +       return ret;
> +}

As Borislav mentioned, dump_{trp,drp}_{db,sb}_syn_reg are basically
copy/pastes of each other with minor differences. I wonder if there's
a way to refactor this so that there's less boilerplate. Maybe a
helper function for the for loop, and maybe another one to read both
of the status registers (or optionally just one) might help. Or you
might do even better with a table, depending on how things shake out.

> +
> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
> +                        int err_type, u32 bank)
> +{
> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +       int ret = 0;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +               ret = dump_drp_sb_syn_reg(drv, bank);
> +               break;
> +       case LLCC_DRAM_UE:
> +               ret = dump_drp_db_syn_reg(drv, bank);
> +               break;
> +       case LLCC_TRAM_CE:
> +               ret = dump_trp_sb_syn_reg(drv, bank);
> +               break;
> +       case LLCC_TRAM_UE:
> +               ret = dump_trp_db_syn_reg(drv, bank);
> +               break;
> +       }
> +       if (ret)
> +               return ret;
> +

If something fails and you return here without clearing errors, would
there be an interrupt storm?

> +       ret = qcom_llcc_clear_errors(err_type, drv);
> +       if (ret)
> +               return ret;
> +
> +       errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
> +
> +       return ret;
> +}
> +

Whoops, I clipped the rest of this message already, but in probe, the
type of ecc_irq should be int. Also, in patch 2 you directly assigned
platform_get_irq into the ecc_irq member, so the if (!ecc_irq) logic
in probe doesn't quite work if platform_get_irq returns a negative
number. Is 0 a valid irq number? I don't know.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-10  3:59   ` Borislav Petkov
@ 2018-08-10 23:03     ` vnkgutta
  0 siblings, 0 replies; 13+ messages in thread
From: vnkgutta @ 2018-08-10 23:03 UTC (permalink / raw)
  To: Borislav Petkov
  Cc: evgreen, robh, mchehab, linux-edac, linux-kernel, andy.gross,
	david.brown, linux-arm-msm, linux-soc, robh+dt, mark.rutland,
	devicetree, tsoni, ckadabi, rishabhb

On 2018-08-09 20:59, Borislav Petkov wrote:
> On Wed, Aug 01, 2018 at 01:33:34PM -0700, Venkata Narendra Kumar Gutta 
> wrote:
>> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>> 
>> Add error reporting driver for SBEs and DBEs. As of now, this driver
> 
> Please write out those abbreviations.
Done, I just followed the other commits which has the same and thought 
they are understood in the community,
I'll update it in the next patch set.
> 
>> supports erp for Last Level Cache Controller (LLCC). This driver takes
>> care of dumping registers and adding config options to enable and
>> disable panic when the errors happen in cache.
>> 
>> Co-developed-by: Venkata Narendra Kumar Gutta 
>> <vnkgutta@codeaurora.org>
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> 
> The proper order is:
> 
> SOB: Author
> SOB: Sender/handler/...
> 
> So:
> 
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Ok, I'll update accordingly.

> 
>> ---
>>  MAINTAINERS              |   7 +
>>  drivers/edac/Kconfig     |  28 +++
>>  drivers/edac/Makefile    |   1 +
>>  drivers/edac/qcom_edac.c | 507 
>> +++++++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 543 insertions(+)
>>  create mode 100644 drivers/edac/qcom_edac.c
>> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index f6a9b08..68b3484 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -5227,6 +5227,13 @@ L:	linux-edac@vger.kernel.org
>>  S:	Maintained
>>  F:	drivers/edac/ti_edac.c
>> 
>> +EDAC-QUALCOMM
>> +M:	Channagoud Kadabi<ckadabi@codeaurora.org>
>> +M:	Venkata Narendra Kumar Gutta<vnkgutta@codeaurora.org>
> 
> Space between name and email address.
> 
>> +L:	linux-arm-msm@vger.kernel.org
> 
> Also
> 
> L:      linux-edac@vger.kernel.org
> 
> so that the EDAC ML gets CCed too.
Ok, Done
> 
>> +S:	Maintained
>> +F:	drivers/edac/qcom_edac.c
>> +
>>  EDIROL UA-101/UA-1000 DRIVER
>>  M:	Clemens Ladisch <clemens@ladisch.de>
>>  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 57304b2..c654b0e 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -460,4 +460,32 @@ config EDAC_TI
>>  	  Support for error detection and correction on the
>>            TI SoCs.
>> 
>> +config EDAC_QCOM
>> +	depends on EDAC=y
> 
> Why on EDAC=y? Did you blindly copy it or is there a reason why
> edac_core should be only built-in or can it be a module too?

I took it from EDAC_ALTERA example. I want to put it like EDAC_QCOM
should be dependent on EDAC. Doesn't it make any sense or we don't need 
this at all?
or do you think it's redundant?

> 
>> +	tristate "QCOM EDAC Controller"
>> +	help
>> +		Support for error detection and correction on the
>> +		QCOM SoCs.
>> +
>> +config EDAC_QCOM_LLCC
>> +	depends on EDAC_QCOM=y && QCOM_LLCC
>> +	tristate "QCOM EDAC Controller for LLCC Cache"
>> +	help
>> +		Support for error detection and correction on the
>> +		QCOM LLCC cache. Report errors caught by LLCC ECC
>> +		mechanism.
>> +
>> +		For debugging issues having to do with stability and overall system
>> +		health, you should probably say 'Y' here.
>> +
>> +config EDAC_QCOM_LLCC_PANIC_ON_UE
>> +	depends on EDAC_QCOM_LLCC
>> +	bool "Panic on uncorrectable errors - qcom llcc"
>> +	help
>> +		Forcibly cause a kernel panic if an uncorrectable error (UE) is
>> +		detected. This can reduce debugging times on hardware which may be
>> +		operating at voltages or frequencies outside normal specification.
>> +
>> +		For production builds, you should probably say 'N' here.
>> +
>>  endif # EDAC
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index 02b43a7..716096d 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
>>  obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
>>  obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
>>  obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
>> +obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> new file mode 100644
>> index 0000000..cf3e2b0
>> --- /dev/null
>> +++ b/drivers/edac/qcom_edac.c
>> @@ -0,0 +1,507 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/edac.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/smp.h>
>> +#include <linux/regmap.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/soc/qcom/llcc-qcom.h>
>> +#include "edac_mc.h"
>> +#include "edac_device.h"
>> +
>> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> +#define LLCC_ERP_PANIC_ON_UE            1
>> +#else
>> +#define LLCC_ERP_PANIC_ON_UE            0
>> +#endif
>> +
>> +#define EDAC_LLCC                       "qcom_llcc"
>> +
>> +#define TRP_SYN_REG_CNT                 6
>> +
>> +#define DRP_SYN_REG_CNT                 8
>> +
>> +#define LLCC_COMMON_STATUS0             0x0003000C
>> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
>> +#define LLCC_LB_CNT_SHIFT               28
>> +
>> +/* single & Double Bit syndrome register offsets */
>> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
>> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
>> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
>> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
>> +
>> +/* Error register offsets */
>> +#define TRP_ECC_ERROR_STATUS1           0x00020348
>> +#define TRP_ECC_ERROR_STATUS0           0x00020344
>> +#define DRP_ECC_ERROR_STATUS1           0x00042048
>> +#define DRP_ECC_ERROR_STATUS0           0x00042044
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define DRP_INTERRUPT_STATUS            0x00041000
>> +#define TRP_INTERRUPT_0_STATUS          0x00020480
>> +#define DRP_INTERRUPT_CLEAR             0x00041008
>> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
>> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
>> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
>> +
>> +/* Mask and shift macros */
>> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
>> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
>> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
>> +
>> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
>> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
>> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
>> +
>> +#define SB_ECC_ERROR                    BIT(0)
>> +#define DB_ECC_ERROR                    BIT(1)
>> +
>> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
>> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
>> +
>> +/* Config registers offsets*/
>> +#define DRP_ECC_ERROR_CFG               0x00040000
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> +
>> +#define SB_ERROR_THRESHOLD              0x1
>> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> +#define TRP0_INTERRUPT_ENABLE           0x1
>> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
>> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> +
>> +
>> +enum {
>> +	LLCC_DRAM_CE = 0,
>> +	LLCC_DRAM_UE,
>> +	LLCC_TRAM_CE,
>> +	LLCC_TRAM_UE,
>> +};
>> +
>> +struct errors_edac {
>> +	const char *msg;
>> +	void (*func)(struct edac_device_ctl_info *edev_ctl,
>> +				int inst_nr, int block_nr, const char *msg);
>> +};
>> +
>> +static const struct errors_edac errors[] = {
>> +	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
>> +	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
>> +	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
>> +	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
>> +};
> 
> An array of function pointers just for two functions?! This looks 
> silly.
> Just do a simple if-else.
Ok, I'll check and update this one.
> 
>> +
>> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> +{
>> +	u32 sb_err_threshold;
>> +	int ret;
>> +
>> +	/* Enable TRP in instance 2 of common interrupt enable register */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
>> +				 TRP0_INTERRUPT_ENABLE,
>> +				 TRP0_INTERRUPT_ENABLE);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable ECC interrupts on Tag Ram */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
>> +				 SB_DB_TRP_INTERRUPT_ENABLE,
>> +				 SB_DB_TRP_INTERRUPT_ENABLE);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable SB error for Data RAM */
>> +	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
>> +	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> +			   sb_err_threshold);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable DRP in instance 2 of common interrupt enable register */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
>> +				 DRP0_INTERRUPT_ENABLE,
>> +				 DRP0_INTERRUPT_ENABLE);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable ECC interrupts on Data Ram */
>> +	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> +			   SB_DB_DRP_INTERRUPT_ENABLE);
>> +	return ret;
>> +}
>> +
>> +/* Clear the error interrupt and counter registers */
>> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data 
>> *drv)
>> +{
>> +	int ret = 0;
>> +
>> +	switch (err_type) {
>> +	case LLCC_DRAM_CE:
>> +	case LLCC_DRAM_UE:
>> +		/* Clear the interrupt */
>> +		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
>> +				   DRP_TRP_INT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +
>> +		/* Clear the counters */
>> +		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
>> +				   DRP_TRP_CNT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +		break;
>> +	case LLCC_TRAM_CE:
>> +	case LLCC_TRAM_UE:
>> +		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
>> +				   DRP_TRP_INT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +
>> +		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
>> +				   DRP_TRP_CNT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +		break;
>> +	}
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome registers for tag Ram Double bit errors */
>> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int db_err_cnt, db_err_ways, ret, i;
>> +	u32 synd_reg, synd_val;
>> +
>> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +				  &synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
>> +			    i, synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +			  &db_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
>> +		    db_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
>> +			  &db_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
>> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
>> +		    db_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome register for tag Ram Single Bit Errors */
>> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int sb_err_cnt, sb_err_ways, ret, i;
>> +	u32 synd_reg, synd_val;
>> +
>> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +				  &synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i,
>> +			    synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +			  &sb_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
>> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
>> +		    sb_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
>> +			  &sb_err_ways);
>> +	if (ret)
>> +		return ret;
>> +
>> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
>> +		    sb_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome registers for Data Ram Double bit errors */
>> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int db_err_cnt, db_err_ways, ret, i;
>> +	u32 synd_reg, synd_val;
>> +
>> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +				  &synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
>> +			    synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +			  &db_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
>> +		    db_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +			  &db_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
>> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
>> +		    db_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump Syndrome registers for Data Ram Single bit errors*/
>> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int sb_err_cnt, sb_err_ways, ret, i;
>> +	u32 synd_reg, synd_val;
>> +
>> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +				  &synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i,
>> +			    synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +			  &sb_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
>> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
>> +		    sb_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +			  drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +			  &sb_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
>> +		    sb_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
>> +			 int err_type, u32 bank)
>> +{
>> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +	int ret = 0;
>> +
>> +	switch (err_type) {
>> +	case LLCC_DRAM_CE:
>> +		ret = dump_drp_sb_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_DRAM_UE:
>> +		ret = dump_drp_db_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_TRAM_CE:
>> +		ret = dump_trp_sb_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_TRAM_UE:
>> +		ret = dump_trp_db_syn_reg(drv, bank);
> 
> So those functions look very similar to one another and thus are
> quadrupled object code. You could have one function instead and pass
> in the register as an arg. Or some other smarter scheme to save object
> size...

There are actually 6 different registers foe each case handled in each
function, that's why we had to have different functions with the same
outline. I can explore the way of having a single method and categorize 
based on
the error type. But I don't think I will be reducing a lot of object 
code. Let me
explore on what can I do on this.


> 
>> +		break;
>> +	}
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = qcom_llcc_clear_errors(err_type, drv);
>> +	if (ret)
>> +		return ret;
>> +
>> +	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
>> +
>> +	return ret;
>> +}
>> +
>> +static irqreturn_t
>> +llcc_ecc_irq_handler (int irq, void *edev_ctl)
> 
> Stray " " after function name.
I'll correct this.
> 
>> +{
>> +	struct edac_device_ctl_info *edac_dev_ctl;
>> +	irqreturn_t irq_rc = IRQ_NONE;
>> +	u32 drp_error, trp_error, i;
>> +	struct llcc_drv_data *drv;
>> +	int ret;
>> +
>> +	edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
>> +	drv = edac_dev_ctl->pvt_info;
>> +
>> +	for (i = 0; i < drv->num_banks; i++) {
>> +		/* Look for Data RAM errors */
>> +		ret = regmap_read(drv->regmap,
>> +				  drv->offsets[i] + DRP_INTERRUPT_STATUS,
>> +				  &drp_error);
>> +		if (ret)
>> +			return irq_rc;
>> +
>> +		if (drp_error & SB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				    "Single Bit Error detected in Data Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		} else if (drp_error & DB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				    "Double Bit Error detected in Data Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		}
>> +
>> +		/* Look for Tag RAM errors */
>> +		ret = regmap_read(drv->regmap,
>> +				  drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
>> +				  &trp_error);
>> +		if (ret)
>> +			return irq_rc;
>> +		if (trp_error & SB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				    "Single Bit Error detected in Tag Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		} else if (trp_error & DB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				    "Double Bit Error detected in Tag Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		}
>> +	}
>> +
>> +	return irq_rc;
>> +}
>> +
>> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
>> +{
>> +	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
>> +	struct edac_device_ctl_info *edev_ctl;
>> +	struct device *dev = &pdev->dev;
>> +	u32 ecc_irq;
>> +	int rc;
>> +
>> +	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
>> +	if (rc)
>> +		return rc;
>> +
>> +	/* Allocate edac control info */
>> +	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
>> +					      llcc_driv_data->num_banks, 1,
>> +					      NULL, 0,
>> +					      edac_device_alloc_index());
>> +
>> +	if (!edev_ctl)
>> +		return -ENOMEM;
>> +
>> +	edev_ctl->dev = dev;
>> +	edev_ctl->mod_name = dev_name(dev);
>> +	edev_ctl->dev_name = dev_name(dev);
>> +	edev_ctl->ctl_name = "llcc";
>> +	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
>> +
>> +	edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data;
> 
> Why is that cast needed?
Not needed, redundant, the variable is already of that type. I'll check 
if the cast is needed in the first line of this function.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-10 17:21   ` Evan Green
@ 2018-08-10 23:04     ` vnkgutta
  0 siblings, 0 replies; 13+ messages in thread
From: vnkgutta @ 2018-08-10 23:04 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-10 10:21, Evan Green wrote:
> On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
>> 
>> Cache error reporting controller is to detect and report single
>> and double bit errors on Last Level Cache Controller (LLCC) cache.
>> Add required support to register LLCC EDAC driver as platform driver,
>> from LLCC driver.
>> 
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> ---
>>  drivers/soc/qcom/llcc-slice.c      | 18 ++++++++++++++++--
>>  include/linux/soc/qcom/llcc-qcom.h |  2 ++
>>  2 files changed, 18 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/soc/qcom/llcc-slice.c 
>> b/drivers/soc/qcom/llcc-slice.c
>> index a63640d..09c8bb0 100644
>> --- a/drivers/soc/qcom/llcc-slice.c
>> +++ b/drivers/soc/qcom/llcc-slice.c
>> @@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct 
>> platform_device *pdev)
>>         u32 attr0_val;
>>         u32 max_cap_cacheline;
>>         u32 sz;
>> -       int ret;
>> +       int ret = 0;
>>         const struct llcc_slice_config *llcc_table;
>>         struct llcc_slice_desc desc;
>> 
>> @@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
>>         struct resource *llcc_banks_res, *llcc_bcast_res;
>>         void __iomem *llcc_banks_base, *llcc_bcast_base;
>>         int ret, i;
>> +       struct platform_device *llcc_edac;
>> 
>>         drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
>>         if (!drv_data)
>> @@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
>>         mutex_init(&drv_data->lock);
>>         platform_set_drvdata(pdev, drv_data);
>> 
>> -       return qcom_llcc_cfg_program(pdev);
>> +       ret = qcom_llcc_cfg_program(pdev);
>> +       if (ret)
>> +               return ret;
>> +
>> +       drv_data->ecc_irq = platform_get_irq(pdev, 0);
>> +       if (drv_data->ecc_irq >= 0) {
> 
> This condition will always be true for u32. See below...
That's true. I missed that.
> 
>> +               llcc_edac = platform_device_register_data(&pdev->dev,
>> +                                               "qcom_llcc_edac", -1, 
>> drv_data,
>> +                                               sizeof(*drv_data));
>> +               if (IS_ERR(llcc_edac))
>> +                       dev_err(dev, "Failed to register llcc edac 
>> driver\n");
>> +       }
>> +
>> +       return ret;
>>  }
>>  EXPORT_SYMBOL_GPL(qcom_llcc_probe);
>> diff --git a/include/linux/soc/qcom/llcc-qcom.h 
>> b/include/linux/soc/qcom/llcc-qcom.h
>> index c681e79..1a3bc25 100644
>> --- a/include/linux/soc/qcom/llcc-qcom.h
>> +++ b/include/linux/soc/qcom/llcc-qcom.h
>> @@ -78,6 +78,7 @@ struct llcc_slice_config {
>>   * @num_banks: Number of llcc banks
>>   * @bitmap: Bit map to track the active slice ids
>>   * @offsets: Pointer to the bank offsets array
>> + * @ecc_irq: interrupt for llcc cache error detection and reporting
>>   */
>>  struct llcc_drv_data {
>>         struct regmap *regmap;
>> @@ -89,6 +90,7 @@ struct llcc_drv_data {
>>         u32 num_banks;
>>         unsigned long *bitmap;
>>         u32 *offsets;
>> +       u32 ecc_irq;
> 
> The return type for platform_get_irq is int, so this should probably
> be int, or "unsigned", but then you'd need to fix your logic above.
I think we should keep that as int. I'll check on which one I'm supposed 
to use here and update in the next version.
> 
>>  };
>> 
>>  #if IS_ENABLED(CONFIG_QCOM_LLCC)
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-10 17:23   ` Evan Green
@ 2018-08-10 23:13     ` vnkgutta
  2018-08-11  0:14       ` Evan Green
  0 siblings, 1 reply; 13+ messages in thread
From: vnkgutta @ 2018-08-10 23:13 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-10 10:23, Evan Green wrote:
> On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
>> 
>> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>> 
>> Add error reporting driver for SBEs and DBEs. As of now, this driver
>> supports erp for Last Level Cache Controller (LLCC). This driver takes
>> care of dumping registers and adding config options to enable and
>> disable panic when the errors happen in cache.
>> 
>> Co-developed-by: Venkata Narendra Kumar Gutta 
>> <vnkgutta@codeaurora.org>
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
>> ---
>>  MAINTAINERS              |   7 +
>>  drivers/edac/Kconfig     |  28 +++
>>  drivers/edac/Makefile    |   1 +
>>  drivers/edac/qcom_edac.c | 507 
>> +++++++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 543 insertions(+)
>>  create mode 100644 drivers/edac/qcom_edac.c
>> 
> ...
>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> new file mode 100644
>> index 0000000..cf3e2b0
>> --- /dev/null
>> +++ b/drivers/edac/qcom_edac.c
>> @@ -0,0 +1,507 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/edac.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/smp.h>
>> +#include <linux/regmap.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/soc/qcom/llcc-qcom.h>
> 
> Please alphabetize these includes, and remove any unneeded ones.
Ok, I'll update it in the next version. I didn't know that it's 
mandatory to have in alphabetic order.
Is it recommended or a strict rule that we have includes in alphabetize 
order?
> 
>> +#include "edac_mc.h"
>> +#include "edac_device.h"
>> +
>> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> +#define LLCC_ERP_PANIC_ON_UE            1
>> +#else
>> +#define LLCC_ERP_PANIC_ON_UE            0
>> +#endif
>> +
>> +#define EDAC_LLCC                       "qcom_llcc"
>> +
>> +#define TRP_SYN_REG_CNT                 6
>> +
>> +#define DRP_SYN_REG_CNT                 8
>> +
>> +#define LLCC_COMMON_STATUS0             0x0003000C
>> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
>> +#define LLCC_LB_CNT_SHIFT               28
>> +
>> +/* single & Double Bit syndrome register offsets */
>> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
>> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
>> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
>> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
>> +
>> +/* Error register offsets */
>> +#define TRP_ECC_ERROR_STATUS1           0x00020348
>> +#define TRP_ECC_ERROR_STATUS0           0x00020344
>> +#define DRP_ECC_ERROR_STATUS1           0x00042048
>> +#define DRP_ECC_ERROR_STATUS0           0x00042044
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define DRP_INTERRUPT_STATUS            0x00041000
>> +#define TRP_INTERRUPT_0_STATUS          0x00020480
>> +#define DRP_INTERRUPT_CLEAR             0x00041008
>> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
>> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
>> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
>> +
>> +/* Mask and shift macros */
>> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
>> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
>> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
>> +
>> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
>> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
>> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
>> +
>> +#define SB_ECC_ERROR                    BIT(0)
>> +#define DB_ECC_ERROR                    BIT(1)
>> +
>> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
>> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
>> +
>> +/* Config registers offsets*/
>> +#define DRP_ECC_ERROR_CFG               0x00040000
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> +
>> +#define SB_ERROR_THRESHOLD              0x1
>> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> +#define TRP0_INTERRUPT_ENABLE           0x1
>> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
>> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> +
>> +
>> +enum {
>> +       LLCC_DRAM_CE = 0,
>> +       LLCC_DRAM_UE,
>> +       LLCC_TRAM_CE,
>> +       LLCC_TRAM_UE,
>> +};
>> +
>> +struct errors_edac {
>> +       const char *msg;
>> +       void (*func)(struct edac_device_ctl_info *edev_ctl,
>> +                               int inst_nr, int block_nr, const char 
>> *msg);
>> +};
>> +
>> +static const struct errors_edac errors[] = {
>> +       {"LLCC Data RAM correctable Error", edac_device_handle_ce},
>> +       {"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
>> +       {"LLCC Tag RAM correctable Error", edac_device_handle_ce},
>> +       {"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
>> +};
>> +
>> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> +{
>> +       u32 sb_err_threshold;
>> +       int ret;
>> +
>> +       /* Enable TRP in instance 2 of common interrupt enable 
>> register */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Tag Ram */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> TRP_INTERRUPT_0_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable SB error for Data RAM */
>> +       sb_err_threshold = (SB_ERROR_THRESHOLD << 
>> SB_ERROR_THRESHOLD_SHIFT);
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> +                          sb_err_threshold);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable DRP in instance 2 of common interrupt enable 
>> register */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Data Ram */
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> +                          SB_DB_DRP_INTERRUPT_ENABLE);
>> +       return ret;
>> +}
>> +
>> +/* Clear the error interrupt and counter registers */
>> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data 
>> *drv)
>> +{
>> +       int ret = 0;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +       case LLCC_DRAM_UE:
>> +               /* Clear the interrupt */
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_INTERRUPT_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               /* Clear the counters */
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +       case LLCC_TRAM_UE:
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_INTERRUPT_0_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
>> +       }
>> +       return ret;
>> +}
>> +
>> +/* Dump syndrome registers for tag Ram Double bit errors */
>> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +       int db_err_cnt, db_err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +               synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       return ret;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 
>> 0x%8x\n",
>> +                           i, synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +                         &db_err_cnt);
>> +       if (ret)
>> +               return ret;
>> +       db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 
>> 0x%4x\n",
>> +                   db_err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
>> +                         &db_err_ways);
>> +       if (ret)
>> +               return ret;
>> +       db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
>> +       db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 
>> 0x%4x\n",
>> +                   db_err_ways);
>> +
>> +       return ret;
>> +}
>> +
>> +/* Dump syndrome register for tag Ram Single Bit Errors */
>> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +       int sb_err_cnt, sb_err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +               synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       return ret;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 
>> 0x%8x\n", i,
>> +                           synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +                         &sb_err_cnt);
>> +       if (ret)
>> +               return ret;
>> +       sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
>> +       sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 
>> 0x%4x\n",
>> +                   sb_err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
>> +                         &sb_err_ways);
>> +       if (ret)
>> +               return ret;
>> +
>> +       sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 
>> 0x%4x\n",
>> +                   sb_err_ways);
>> +
>> +       return ret;
>> +}
>> +
>> +/* Dump syndrome registers for Data Ram Double bit errors */
>> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +       int db_err_cnt, db_err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +               synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       return ret;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 
>> 0x%8x\n", i,
>> +                           synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +                         &db_err_cnt);
>> +       if (ret)
>> +               return ret;
>> +       db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 
>> 0x%4x\n",
>> +                   db_err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +                         &db_err_ways);
>> +       if (ret)
>> +               return ret;
>> +       db_err_ways &= ECC_DB_ERR_WAYS_MASK;
>> +       db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 
>> 0x%4x\n",
>> +                   db_err_ways);
>> +
>> +       return ret;
>> +}
>> +
>> +/* Dump Syndrome registers for Data Ram Single bit errors*/
>> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +       int sb_err_cnt, sb_err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +               synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       return ret;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 
>> 0x%8x\n", i,
>> +                           synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +                         &sb_err_cnt);
>> +       if (ret)
>> +               return ret;
>> +       sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
>> +       sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 
>> 0x%4x\n",
>> +                   sb_err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +                         &sb_err_ways);
>> +       if (ret)
>> +               return ret;
>> +       sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 
>> 0x%4x\n",
>> +                   sb_err_ways);
>> +
>> +       return ret;
>> +}
> 
> As Borislav mentioned, dump_{trp,drp}_{db,sb}_syn_reg are basically
> copy/pastes of each other with minor differences. I wonder if there's
> a way to refactor this so that there's less boilerplate. Maybe a
> helper function for the for loop, and maybe another one to read both
> of the status registers (or optionally just one) might help. Or you
> might do even better with a table, depending on how things shake out.

Sure, I'll explore that option.

> 
>> +
>> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
>> +                        int err_type, u32 bank)
>> +{
>> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +       int ret = 0;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +               ret = dump_drp_sb_syn_reg(drv, bank);
>> +               break;
>> +       case LLCC_DRAM_UE:
>> +               ret = dump_drp_db_syn_reg(drv, bank);
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +               ret = dump_trp_sb_syn_reg(drv, bank);
>> +               break;
>> +       case LLCC_TRAM_UE:
>> +               ret = dump_trp_db_syn_reg(drv, bank);
>> +               break;
>> +       }
>> +       if (ret)
>> +               return ret;
>> +
> 
> If something fails and you return here without clearing errors, would
> there be an interrupt storm?

I'm not sure on this. I'll have to go back and check the spec. I can 
update
it in the next patch set based on the findings.

> 
>> +       ret = qcom_llcc_clear_errors(err_type, drv);
>> +       if (ret)
>> +               return ret;
>> +
>> +       errors[err_type].func(edev_ctl, 0, bank, 
>> errors[err_type].msg);
>> +
>> +       return ret;
>> +}
>> +
> 
> Whoops, I clipped the rest of this message already, but in probe, the
> type of ecc_irq should be int. Also, in patch 2 you directly assigned
> platform_get_irq into the ecc_irq member, so the if (!ecc_irq) logic
> in probe doesn't quite work if platform_get_irq returns a negative
> number. Is 0 a valid irq number? I don't know.

Yeah, I'll update the data type and fix the logic accordingly.


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-10 23:13     ` vnkgutta
@ 2018-08-11  0:14       ` Evan Green
  0 siblings, 0 replies; 13+ messages in thread
From: Evan Green @ 2018-08-11  0:14 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Fri, Aug 10, 2018 at 4:13 PM <vnkgutta@codeaurora.org> wrote:
>
> On 2018-08-10 10:23, Evan Green wrote:
> > On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
> > <vnkgutta@codeaurora.org> wrote:
> >>
> >> From: Channagoud Kadabi <ckadabi@codeaurora.org>
> >>
> >> Add error reporting driver for SBEs and DBEs. As of now, this driver
> >> supports erp for Last Level Cache Controller (LLCC). This driver takes
> >> care of dumping registers and adding config options to enable and
> >> disable panic when the errors happen in cache.
> >>
> >> Co-developed-by: Venkata Narendra Kumar Gutta
> >> <vnkgutta@codeaurora.org>
> >> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> >> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> >> ---
> >>  MAINTAINERS              |   7 +
> >>  drivers/edac/Kconfig     |  28 +++
> >>  drivers/edac/Makefile    |   1 +
> >>  drivers/edac/qcom_edac.c | 507
> >> +++++++++++++++++++++++++++++++++++++++++++++++
> >>  4 files changed, 543 insertions(+)
> >>  create mode 100644 drivers/edac/qcom_edac.c
> >>
> > ...
> >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> >> new file mode 100644
> >> index 0000000..cf3e2b0
> >> --- /dev/null
> >> +++ b/drivers/edac/qcom_edac.c
> >> @@ -0,0 +1,507 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> >> + */
> >> +
> >> +#include <linux/kernel.h>
> >> +#include <linux/edac.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/smp.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/interrupt.h>
> >> +#include <linux/soc/qcom/llcc-qcom.h>
> >
> > Please alphabetize these includes, and remove any unneeded ones.
> Ok, I'll update it in the next version. I didn't know that it's
> mandatory to have in alphabetic order.
> Is it recommended or a strict rule that we have includes in alphabetize
> order?

You know, I'm not actually sure if it's a strict rule. I'm still
learning many of the conventions here myself. But it seems to get
commented on consistently by reviewers, so it's in my bag of "things I
look out for".

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, back to index

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
2018-08-10 17:21   ` Evan Green
2018-08-10 23:04     ` vnkgutta
2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-08 23:11   ` vnkgutta
2018-08-10  3:59   ` Borislav Petkov
2018-08-10 23:03     ` vnkgutta
2018-08-10 17:23   ` Evan Green
2018-08-10 23:13     ` vnkgutta
2018-08-11  0:14       ` Evan Green
2018-08-01 20:33 ` [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta

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