[PATCH 0/3] dmaengine: xilinx_dma: Minor fix and refactoring

[PATCH 0/3] dmaengine: xilinx_dma: Minor fix and refactoring

[Radhey Shyam Pandey]

This patchset fixes 64-bit simple CDMA transfer.
It also does some trivial code refactoring.


Radhey Shyam Pandey (3):
  dmaengine: xilinx_dma: Refactor axidma channel allocation
  dmaengine: xilinx_dma: Refactor axidma channel validation
  dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

 drivers/dma/xilinx/xilinx_dma.c |   46 ++++++++++++++++++++------------------
 1 files changed, 24 insertions(+), 22 deletions(-)

[PATCH 1/3] dmaengine: xilinx_dma: Refactor axidma channel allocation

[Radhey Shyam Pandey]

In axidma alloc_chan_resources merge BD and cyclic BD allocation.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/dma/xilinx/xilinx_dma.c |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index c124423..06d1632 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -887,6 +887,24 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
 				chan->id);
 			return -ENOMEM;
 		}
+		/*
+		 * For cyclic DMA mode we need to program the tail Descriptor
+		 * register with a value which is not a part of the BD chain
+		 * so allocating a desc segment during channel allocation for
+		 * programming tail descriptor.
+		 */
+		chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
+					sizeof(*chan->cyclic_seg_v),
+					&chan->cyclic_seg_p, GFP_KERNEL);
+		if (!chan->cyclic_seg_v) {
+			dev_err(chan->dev,
+				"unable to allocate desc segment for cyclic DMA\n");
+			dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
+				XILINX_DMA_NUM_DESCS, chan->seg_v,
+				chan->seg_p);
+			return -ENOMEM;
+		}
+		chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
 
 		for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
 			chan->seg_v[i].hw.next_desc =
@@ -922,24 +940,6 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
 		return -ENOMEM;
 	}
 
-	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
-		/*
-		 * For cyclic DMA mode we need to program the tail Descriptor
-		 * register with a value which is not a part of the BD chain
-		 * so allocating a desc segment during channel allocation for
-		 * programming tail descriptor.
-		 */
-		chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
-					sizeof(*chan->cyclic_seg_v),
-					&chan->cyclic_seg_p, GFP_KERNEL);
-		if (!chan->cyclic_seg_v) {
-			dev_err(chan->dev,
-				"unable to allocate desc segment for cyclic DMA\n");
-			return -ENOMEM;
-		}
-		chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
-	}
-
 	dma_cookie_init(dchan);
 
 	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
-- 
1.7.1

RE: [PATCH 1/3] dmaengine: xilinx_dma: Refactor axidma channel allocation

[Appana Durga Kedareswara Rao]

Hi,

	Thanks for the patch... 
> 
> In axidma alloc_chan_resources merge BD and cyclic BD allocation.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Acked-for-series: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>

Regards,
Kedar.

> ---
>  drivers/dma/xilinx/xilinx_dma.c |   36 ++++++++++++++++++------------------
>  1 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/dma/xilinx/xilinx_dma.c
> b/drivers/dma/xilinx/xilinx_dma.c index c124423..06d1632 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -887,6 +887,24 @@ static int xilinx_dma_alloc_chan_resources(struct
> dma_chan *dchan)
>  				chan->id);
>  			return -ENOMEM;
>  		}
> +		/*
> +		 * For cyclic DMA mode we need to program the tail
> Descriptor
> +		 * register with a value which is not a part of the BD chain
> +		 * so allocating a desc segment during channel allocation for
> +		 * programming tail descriptor.
> +		 */
> +		chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
> +					sizeof(*chan->cyclic_seg_v),
> +					&chan->cyclic_seg_p, GFP_KERNEL);
> +		if (!chan->cyclic_seg_v) {
> +			dev_err(chan->dev,
> +				"unable to allocate desc segment for cyclic
> DMA\n");
> +			dma_free_coherent(chan->dev, sizeof(*chan->seg_v)
> *
> +				XILINX_DMA_NUM_DESCS, chan->seg_v,
> +				chan->seg_p);
> +			return -ENOMEM;
> +		}
> +		chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
> 
>  		for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
>  			chan->seg_v[i].hw.next_desc =
> @@ -922,24 +940,6 @@ static int xilinx_dma_alloc_chan_resources(struct
> dma_chan *dchan)
>  		return -ENOMEM;
>  	}
> 
> -	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
> -		/*
> -		 * For cyclic DMA mode we need to program the tail
> Descriptor
> -		 * register with a value which is not a part of the BD chain
> -		 * so allocating a desc segment during channel allocation for
> -		 * programming tail descriptor.
> -		 */
> -		chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
> -					sizeof(*chan->cyclic_seg_v),
> -					&chan->cyclic_seg_p, GFP_KERNEL);
> -		if (!chan->cyclic_seg_v) {
> -			dev_err(chan->dev,
> -				"unable to allocate desc segment for cyclic
> DMA\n");
> -			return -ENOMEM;
> -		}
> -		chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
> -	}
> -
>  	dma_cookie_init(dchan);
> 
>  	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
> --
> 1.7.1

[PATCH 2/3] dmaengine: xilinx_dma: Refactor axidma channel validation

[Radhey Shyam Pandey]

In axidma start_transfer, prefer checking channel states before
other params i.e pending_list.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---
 drivers/dma/xilinx/xilinx_dma.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 06d1632..a37871e 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 	if (chan->err)
 		return;
 
-	if (list_empty(&chan->pending_list))
+	if (!chan->idle)
 		return;
 
-	if (!chan->idle)
+	if (list_empty(&chan->pending_list))
 		return;
 
 	head_desc = list_first_entry(&chan->pending_list,
-- 
1.7.1

Re: [PATCH 2/3] dmaengine: xilinx_dma: Refactor axidma channel validation

[Vinod]

On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> In axidma start_transfer, prefer checking channel states before
> other params i.e pending_list.

and what that preference be?

> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> ---
>  drivers/dma/xilinx/xilinx_dma.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 06d1632..a37871e 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
>  	if (chan->err)
>  		return;
>  
> -	if (list_empty(&chan->pending_list))
> +	if (!chan->idle)
>  		return;
>  
> -	if (!chan->idle)
> +	if (list_empty(&chan->pending_list))
>  		return;
>  
>  	head_desc = list_first_entry(&chan->pending_list,
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
~Vinod

RE: [PATCH 2/3] dmaengine: xilinx_dma: Refactor axidma channel validation

[Radhey Shyam Pandey]

> -----Original Message-----
> From: Vinod <vkoul@kernel.org>
> Sent: Tuesday, August 21, 2018 9:20 PM
> To: Radhey Shyam Pandey <radheys@xilinx.com>
> Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; Appana
> Durga Kedareswara Rao <appanad@xilinx.com>; lars@metafoo.de;
> dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 2/3] dmaengine: xilinx_dma: Refactor axidma channel
> validation
> 
> On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> > In axidma start_transfer, prefer checking channel states before other
> > params i.e pending_list.
> 
> and what that preference be?
There is no strict preference. I thought to group and first check channel
states(idle/error) and then look for pending list.

Thanks,
Radhey
> 
> >
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> > ---
> >  drivers/dma/xilinx/xilinx_dma.c |    4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/dma/xilinx/xilinx_dma.c
> > b/drivers/dma/xilinx/xilinx_dma.c index 06d1632..a37871e 100644
> > --- a/drivers/dma/xilinx/xilinx_dma.c
> > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > @@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct
> xilinx_dma_chan *chan)
> >  	if (chan->err)
> >  		return;
> >
> > -	if (list_empty(&chan->pending_list))
> > +	if (!chan->idle)
> >  		return;
> >
> > -	if (!chan->idle)
> > +	if (list_empty(&chan->pending_list))
> >  		return;
> >
> >  	head_desc = list_first_entry(&chan->pending_list,
> > --
> > 1.7.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe dmaengine"
> > in the body of a message to majordomo@vger.kernel.org More majordomo
> > info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> ~Vinod

[PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Radhey Shyam Pandey]

In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/dma/xilinx/xilinx_dma.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index a37871e..2e15d86 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
 
 		hw = &segment->hw;
 
-		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
-		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
+		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)
+			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));
+		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)
+			     ((u64)hw->dest_addr_msb << 32 | hw->dest_addr));
 
 		/* Start the transfer */
 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
-- 
1.7.1

Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Vinod]

On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> In AXI CDMA simple mode also pass MSB bits of source and destination
> address to xilinx_write function. This fixes simple CDMA operation
> mode using 64-bit addressing.
> 
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>  drivers/dma/xilinx/xilinx_dma.c |    6 ++++--
>  1 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index a37871e..2e15d86 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
>  
>  		hw = &segment->hw;
>  
> -		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
> -		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
> +		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)
> +			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));

so this is:
        (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr)

what is src_addr data type? I think its u32. It would be better to
update xilinx_write() to take u64 and not dma_addr_t.


> +		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)
> +			     ((u64)hw->dest_addr_msb << 32 | hw->dest_addr));
>  
>  		/* Start the transfer */
>  		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
~Vinod

RE: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Radhey Shyam Pandey]

> -----Original Message-----
> From: Vinod <vkoul@kernel.org>
> Sent: Tuesday, August 21, 2018 9:26 PM
> To: Radhey Shyam Pandey <radheys@xilinx.com>
> Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; Appana
> Durga Kedareswara Rao <appanad@xilinx.com>; lars@metafoo.de;
> dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA
> transfer
> 
> On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> > In AXI CDMA simple mode also pass MSB bits of source and destination
> > address to xilinx_write function. This fixes simple CDMA operation
> > mode using 64-bit addressing.
> >
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> >  drivers/dma/xilinx/xilinx_dma.c |    6 ++++--
> >  1 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> > index a37871e..2e15d86 100644
> > --- a/drivers/dma/xilinx/xilinx_dma.c
> > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct
> xilinx_dma_chan *chan)
> >
> >  		hw = &segment->hw;
> >
> > -		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> >src_addr);
> > -		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> >dest_addr);
> > +		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> (dma_addr_t)
> > +			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));
> 
> so this is:
>         (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr)
> 
> what is src_addr data type? I think its u32. It would be better to
> update xilinx_write() to take u64 and not dma_addr_t.

Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no
prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit 
depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a bug
i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix
that combine MSB and LSB 32 bits before passing it to xilinx_write.

Thanks,
Radhey
> 
> 
> > +		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
> (dma_addr_t)
> > +			     ((u64)hw->dest_addr_msb << 32 | hw-
> >dest_addr));
> >
> >  		/* Start the transfer */
> >  		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
> > --
> > 1.7.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> --
> ~Vinod

Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Vinod]

On 28-08-18, 14:03, Radhey Shyam Pandey wrote:
> > On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> > > In AXI CDMA simple mode also pass MSB bits of source and destination
> > > address to xilinx_write function. This fixes simple CDMA operation
> > > mode using 64-bit addressing.
> > >
> > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> > > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > > ---
> > >  drivers/dma/xilinx/xilinx_dma.c |    6 ++++--
> > >  1 files changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> > > index a37871e..2e15d86 100644
> > > --- a/drivers/dma/xilinx/xilinx_dma.c
> > > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > > @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct
> > xilinx_dma_chan *chan)
> > >
> > >  		hw = &segment->hw;
> > >
> > > -		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> > >src_addr);
> > > -		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> > >dest_addr);
> > > +		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> > (dma_addr_t)
> > > +			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));
> > 
> > so this is:
> >         (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr)
> > 
> > what is src_addr data type? I think its u32. It would be better to
> > update xilinx_write() to take u64 and not dma_addr_t.
> 
> Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no
> prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit 
> depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a bug
> i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix
> that combine MSB and LSB 32 bits before passing it to xilinx_write.

Yeah that part was clear but the implementation can be better..

-- 
~Vinod

RE: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Radhey Shyam Pandey]

> -----Original Message-----
> From: Vinod <vkoul@kernel.org>
> Sent: Wednesday, August 29, 2018 9:31 AM
> To: Radhey Shyam Pandey <radheys@xilinx.com>
> Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; Appana
> Durga Kedareswara Rao <appanad@xilinx.com>; lars@metafoo.de;
> dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA
> transfer
> 
> On 28-08-18, 14:03, Radhey Shyam Pandey wrote:
> > > On 27-07-18, 16:20, Radhey Shyam Pandey wrote:
> > > > In AXI CDMA simple mode also pass MSB bits of source and destination
> > > > address to xilinx_write function. This fixes simple CDMA operation
> > > > mode using 64-bit addressing.
> > > >
> > > > Signed-off-by: Radhey Shyam Pandey
> <radhey.shyam.pandey@xilinx.com>
> > > > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > > > ---
> > > >  drivers/dma/xilinx/xilinx_dma.c |    6 ++++--
> > > >  1 files changed, 4 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c
> b/drivers/dma/xilinx/xilinx_dma.c
> > > > index a37871e..2e15d86 100644
> > > > --- a/drivers/dma/xilinx/xilinx_dma.c
> > > > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > > > @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct
> > > xilinx_dma_chan *chan)
> > > >
> > > >  		hw = &segment->hw;
> > > >
> > > > -		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> > > >src_addr);
> > > > -		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> > > >dest_addr);
> > > > +		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> > > (dma_addr_t)
> > > > +			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));
> > >
> > > so this is:
> > >         (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr)
> > >
> > > what is src_addr data type? I think its u32. It would be better to
> > > update xilinx_write() to take u64 and not dma_addr_t.
> >
> > Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no
> > prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit
> > depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a
> bug
> > i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix
> > that combine MSB and LSB 32 bits before passing it to xilinx_write.
> 
> Yeah that part was clear but the implementation can be better..
Thanks! Separate fields for source address are needed due to CDMA BD structure. 
Please suggest if it doesn't look ok.

> 
> --
> ~Vinod

RE: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Radhey Shyam Pandey]

<snip>
> > > > > -		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> > > > >src_addr);
> > > > > -		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> > > > >dest_addr);
> > > > > +		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> > > > (dma_addr_t)
> > > > > +			     ((u64)hw->src_addr_msb << 32 | hw-
> >src_addr));
> > > >
> > > > so this is:
> > > >         (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr)
> > > >
> > > > what is src_addr data type? I think its u32. It would be better to
> > > > update xilinx_write() to take u64 and not dma_addr_t.
> > >
> > > Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no
> > > prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit
> > > depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a
> > bug
> > > i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix
> > > that combine MSB and LSB 32 bits before passing it to xilinx_write.
> >
> > Yeah that part was clear but the implementation can be better..
I thought over it and it seems having a new interface dma_ctrl_write_64
taking lsb and msb bits input looks better and scalable. It will be similar
to existing vdma_desc_write_64 impl. I will send v2 if it looks ok.

Thanks,
Radhey
<snip>
> 
> >
> > --
> > ~Vinod

Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Vinod]

On 07-09-18, 12:08, Radhey Shyam Pandey wrote:

> > > Yeah that part was clear but the implementation can be better..
> I thought over it and it seems having a new interface dma_ctrl_write_64
> taking lsb and msb bits input looks better and scalable. It will be similar
> to existing vdma_desc_write_64 impl. I will send v2 if it looks ok.

Yes that is much better, btw why not reuse same routine as common xilinx
lib functions :)

-- 
~Vinod

RE: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer

[Radhey Shyam Pandey]

> > > > Yeah that part was clear but the implementation can be better..
> > I thought over it and it seems having a new interface dma_ctrl_write_64
> > taking lsb and msb bits input looks better and scalable. It will be similar
> > to existing vdma_desc_write_64 impl. I will send v2 if it looks ok.
> 
> Yes that is much better, btw why not reuse same routine as common xilinx
> lib functions :)

Thanks.  vdma_desc_write_64 uses a different offset i.e desc_offset.
For reusing it we need to have an additional check to derive offset
(ctrl_offset/desc_offset) based on channel config type. Considering
it, i think a separate helper interface _64 for desc/control offset
simplifies the flow. Please let me know your thoughts on it.

-Radhey
> 
> --
> ~Vinod