Re: [RFC v1 0/1] imx-drm: match ipu_di_signal_cfg's clk_pol with its observed behaviour.

Re: [RFC v1 0/1] imx-drm: match ipu_di_signal_cfg's clk_pol with its observed behaviour.

[thesven73]

Hi Russell, thanks for looking at the RFC !

> Given what's in the documentation, I'd opt for it describing the
> edge that the output data changes, not the latch edge.  With that
> interpretation, the existing code is correct.

The clock polarity is reversed in Freescale's non-mainline fbdev code,
which we were using previously, contributing to the confusion.

Yes, I think your interpretation is the correct one. Let's double-check.

Suppose we set this bus flag in the panel/mode definition:

drm/drm_connector.h:
/* drive data on pos. edge */
#define DRM_BUS_FLAG_PIXDATA_POSEDGE	(1<<2)

According to your interpretation, this means we're asking the data to change
on the positive edge, and be stable on the negative edge. Correct?

then clk_pol == 1:
drivers/gpu/drm/imx/ipuv3-crtc.c:
	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
			     DRM_BUS_FLAG_PIXDATA_POSEDGE);

then DI_GENERAL bit 17 is set:
drivers/gpu/ipu-v3/ipu-di.c:
	if (sig->clk_pol)
		di_gen |= DI_GEN_POLARITY_DISP_CLK;

and data is stable on the pixel clock's falling edge, as we observed on
the oscilloscope.

All good. Thank you !

[RFC v1 0/1] imx-drm: match ipu_di_signal_cfg's clk_pol with its observed behaviour.

[thesven73]

From: Sven Van Asbroeck <svendev@arcx.com>

Request For Comments

We believe that the ipuv3 DI's pixel clock polarity is possibly being
misconfigured by the imx-drm driver.

We used an oscilloscope the observe the actual behaviour on our hardware,
and it is the opposite of what the driver is supposed to configure.

Some confusion could arise because the Freescale documentation does not
speak about data stable on rising or falling edge, but only of clock active
high / active low:

i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015,
page 3298)
  bit 17 DI0 Output Clock's polarity
  This bits define the polarity of the DI0's clock.
    1 The output clock is active high
    0 The output clock is active low

However, the supposedly wrong behaviour has been in place since April 2014,
and no-one has complained so far.
See commit 85de9d17c485c4196f74d45de2206d4802f8a3be

What are we missing ?

Sven Van Asbroeck (1):
  imx-drm: match ipu_di_signal_cfg's clk_pol with its observed
    behaviour.

 drivers/gpu/ipu-v3/ipu-di.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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2.17.1