* [PATCH 1/5] arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
@ 2018-10-23 19:06 ` Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 2/5] arm64: dts: hisilicon: hi3760: Add GPIO controller support Manivannan Sadhasivam
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-10-23 19:06 UTC (permalink / raw)
To: xuwei5, linus.walleij, robh+dt
Cc: linux-gpio, devicetree, amit.kucheria, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
Add pinctrl support based on "pinctrl-single" driver for HiKey970
development board from HiSilicon.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
new file mode 100644
index 000000000000..64fb9a3bd707
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl dts file for HiSilicon HiKey970 development board
+ */
+
+#include <dt-bindings/pinctrl/hisi.h>
+
+/ {
+ soc {
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+ pmx0: pinmux@e896c000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xe896c000 0x0 0x72c>;
+ #pinctrl-cells = <1>;
+ #gpio-range-cells = <0x3>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 82 0>;
+ };
+
+ pmx2: pinmux@e896c800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xe896c800 0x0 0x72c>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ };
+
+ pmx5: pinmux@fc182000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xfc182000 0x0 0x028>;
+ #gpio-range-cells = <3>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 10 0>;
+
+ };
+
+ pmx6: pinmux@fc182800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xfc182800 0x0 0x028>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ };
+
+ pmx7: pinmux@ff37e000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xff37e000 0x0 0x030>;
+ #gpio-range-cells = <3>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 12 0>;
+ };
+
+ pmx8: pinmux@ff37e800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff37e800 0x0 0x030>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ };
+
+ pmx1: pinmux@fff11000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xfff11000 0x0 0x73c>;
+ #gpio-range-cells = <0x3>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 46 0>;
+ };
+
+ pmx16: pinmux@fff11800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xfff11800 0x0 0x73c>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/5] arm64: dts: hisilicon: hi3760: Add GPIO controller support
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 1/5] arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board Manivannan Sadhasivam
@ 2018-10-23 19:06 ` Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 3/5] arm64: dts: hisilicon: hi3670: Add UART nodes Manivannan Sadhasivam
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-10-23 19:06 UTC (permalink / raw)
To: xuwei5, linus.walleij, robh+dt
Cc: linux-gpio, devicetree, amit.kucheria, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
Add GPIO controller support for HiSilicon HI3670 SoC based on ARM
Primecell PL061 GPIO controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../boot/dts/hisilicon/hi3670-hikey970.dts | 1 +
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 379 ++++++++++++++++++
2 files changed, 380 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index 4f5118642024..8fdc1dfcb06c 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -10,6 +10,7 @@
/dts-v1/;
#include "hi3670.dtsi"
+#include "hikey970-pinctrl.dtsi"
/ {
model = "HiKey970";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 34a2f0dbc6f7..b99f5e0fe577 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -196,5 +196,384 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ gpio0: gpio@e8a0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a0b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio1: gpio@e8a0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a0c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio2: gpio@e8a0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a0d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 6 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio3: gpio@e8a0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a0e000 0x0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio4: gpio@e8a0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a0f000 0x0 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 18 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio5: gpio@e8a10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 26 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio6: gpio@e8a11000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a11000 0x0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 34 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio7: gpio@e8a12000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a12000 0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 41 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio8: gpio@e8a13000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a13000 0x0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 49 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio9: gpio@e8a14000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 57 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio10: gpio@e8a15000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a15000 0x0 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 65 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio11: gpio@e8a16000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a16000 0x0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 73 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio12: gpio@e8a17000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a17000 0x0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 81 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio13: gpio@e8a18000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a18000 0x0 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio14: gpio@e8a19000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a19000 0x0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio15: gpio@e8a1a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a1a000 0x0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio16: gpio@e8a1b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a1b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx5 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio17: gpio@e8a1c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a1c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx5 0 8 2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio18: gpio@fff28000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff28000 0x0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 4 42 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_GPIO18>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio19: gpio@fff29000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff29000 0x0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 0 61 2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_GPIO19>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio20: gpio@e8a1f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a1f000 0x0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx7 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio21: gpio@e8a20000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xe8a20000 0x0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx7 0 8 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio22: gpio@fff0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff0b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO176 */
+ gpio-ranges = <&pmx1 2 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio23: gpio@fff0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff0c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO184 */
+ gpio-ranges = <&pmx1 0 6 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio24: gpio@fff0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff0d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO192 */
+ gpio-ranges = <&pmx1 0 14 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio25: gpio@fff0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff0e000 0x0 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO200 */
+ gpio-ranges = <&pmx1 0 22 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio26: gpio@fff0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff0f000 0x0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO208 */
+ gpio-ranges = <&pmx1 0 30 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio27: gpio@fff10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO216 */
+ gpio-ranges = <&pmx1 4 31 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio28: gpio@fff1d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xfff1d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 1 35 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
+ clock-names = "apb_pclk";
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/5] arm64: dts: hisilicon: hi3670: Add UART nodes
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 1/5] arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 2/5] arm64: dts: hisilicon: hi3760: Add GPIO controller support Manivannan Sadhasivam
@ 2018-10-23 19:06 ` Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 4/5] arm64: boot: dts: hisilicon: hikey970: Enable on-board UARTs Manivannan Sadhasivam
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-10-23 19:06 UTC (permalink / raw)
To: xuwei5, linus.walleij, robh+dt
Cc: linux-gpio, devicetree, amit.kucheria, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
Add UART nodes for HiSilicon HI3670 SoC and also relevant pinmux/pinconf
entries.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 ++++++++
.../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 157 ++++++++++++++++++
2 files changed, 229 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index b99f5e0fe577..a5bd6d80b226 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -187,6 +187,76 @@
#clock-cells = <1>;
};
+ uart0: serial@fdf02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf02000 0x0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+ status = "disabled";
+ };
+
+ uart1: serial@fdf00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart2: serial@fdf03000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf03000 0x0 0x1000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffd74000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xffd74000 0x0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "disabled";
+ };
+
+ uart4: serial@fdf01000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf01000 0x0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "disabled";
+ };
+
+ uart5: serial@fdf05000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf05000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
+ <&crg_ctrl HI3670_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
uart6: serial@fff32000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfff32000 0x0 0x1000>;
@@ -194,6 +264,8 @@
clocks = <&crg_ctrl HI3670_CLK_UART6>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
index 64fb9a3bd707..67bb52d43619 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
@@ -20,6 +20,47 @@
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 82 0>;
+
+ uart0_pmx_func: uart0_pmx_func {
+ pinctrl-single,pins = <
+ 0x054 MUX_M2 /* UART0_RXD */
+ 0x058 MUX_M2 /* UART0_TXD */
+ >;
+ };
+
+ uart2_pmx_func: uart2_pmx_func {
+ pinctrl-single,pins = <
+ 0x700 MUX_M2 /* UART2_CTS_N */
+ 0x704 MUX_M2 /* UART2_RTS_N */
+ 0x708 MUX_M2 /* UART2_RXD */
+ 0x70c MUX_M2 /* UART2_TXD */
+ >;
+ };
+
+ uart3_pmx_func: uart3_pmx_func {
+ pinctrl-single,pins = <
+ 0x064 MUX_M1 /* UART3_CTS_N */
+ 0x068 MUX_M1 /* UART3_RTS_N */
+ 0x06c MUX_M1 /* UART3_RXD */
+ 0x070 MUX_M1 /* UART3_TXD */
+ >;
+ };
+
+ uart4_pmx_func: uart4_pmx_func {
+ pinctrl-single,pins = <
+ 0x074 MUX_M1 /* UART4_CTS_N */
+ 0x078 MUX_M1 /* UART4_RTS_N */
+ 0x07c MUX_M1 /* UART4_RXD */
+ 0x080 MUX_M1 /* UART4_TXD */
+ >;
+ };
+
+ uart6_pmx_func: uart6_pmx_func {
+ pinctrl-single,pins = <
+ 0x05c MUX_M1 /* UART6_RXD */
+ 0x060 MUX_M1 /* UART6_TXD */
+ >;
+ };
};
pmx2: pinmux@e896c800 {
@@ -27,6 +68,122 @@
reg = <0x0 0xe896c800 0x0 0x72c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
+
+ uart0_cfg_func: uart0_cfg_func {
+ pinctrl-single,pins = <
+ 0x058 0x0 /* UART0_RXD */
+ 0x05c 0x0 /* UART0_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0x700 0x0 /* UART2_CTS_N */
+ 0x704 0x0 /* UART2_RTS_N */
+ 0x708 0x0 /* UART2_RXD */
+ 0x70c 0x0 /* UART2_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x068 0x0 /* UART3_CTS_N */
+ 0x06c 0x0 /* UART3_RTS_N */
+ 0x070 0x0 /* UART3_RXD */
+ 0x074 0x0 /* UART3_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x078 0x0 /* UART4_CTS_N */
+ 0x07c 0x0 /* UART4_RTS_N */
+ 0x080 0x0 /* UART4_RXD */
+ 0x084 0x0 /* UART4_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart6_cfg_func: uart6_cfg_func {
+ pinctrl-single,pins = <
+ 0x060 0x0 /* UART6_RXD */
+ 0x064 0x0 /* UART6_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
};
pmx5: pinmux@fc182000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/5] arm64: boot: dts: hisilicon: hikey970: Enable on-board UARTs
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
` (2 preceding siblings ...)
2018-10-23 19:06 ` [PATCH 3/5] arm64: dts: hisilicon: hi3670: Add UART nodes Manivannan Sadhasivam
@ 2018-10-23 19:06 ` Manivannan Sadhasivam
2018-10-23 19:06 ` [PATCH 5/5] arm64: dts: hisilicon: hikey970: Add GPIO line names Manivannan Sadhasivam
2018-10-31 9:43 ` [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Linus Walleij
5 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-10-23 19:06 UTC (permalink / raw)
To: xuwei5, linus.walleij, robh+dt
Cc: linux-gpio, devicetree, amit.kucheria, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
Enable on-board UARTs on HiSilicon HiKey970 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../boot/dts/hisilicon/hi3670-hikey970.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index 8fdc1dfcb06c..fc851a3177e7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -17,6 +17,12 @@
compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
serial6 = &uart6; /* console UART */
};
@@ -31,6 +37,20 @@
};
};
+&uart0 {
+ /* On High speed expansion header */
+ label = "HS-UART0";
+ status = "okay";
+};
+
+&uart2 {
+ /* On Low speed expansion header */
+ label = "LS-UART0";
+ status = "okay";
+};
+
&uart6 {
+ /* On Low speed expansion header */
+ label = "LS-UART1";
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/5] arm64: dts: hisilicon: hikey970: Add GPIO line names
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
` (3 preceding siblings ...)
2018-10-23 19:06 ` [PATCH 4/5] arm64: boot: dts: hisilicon: hikey970: Enable on-board UARTs Manivannan Sadhasivam
@ 2018-10-23 19:06 ` Manivannan Sadhasivam
2018-10-31 9:43 ` [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Linus Walleij
5 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-10-23 19:06 UTC (permalink / raw)
To: xuwei5, linus.walleij, robh+dt
Cc: linux-gpio, devicetree, amit.kucheria, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
Add GPIO line names for HiSilicon HiKey970 board based on HI3670 SoC.
The Line names are derived from "hikey970-schematics.pdf" document and
named in conjunction with 96Boards CE Specification v1.0.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../boot/dts/hisilicon/hi3670-hikey970.dts | 317 ++++++++++++++++++
1 file changed, 317 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
index fc851a3177e7..c9775b66629f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -37,6 +37,323 @@
};
};
+/*
+ * Legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ * anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * "" = no idea, schematic doesn't say, could be
+ * unrouted (not connected to any external pin)
+ * LSEC = Low Speed External Connector
+ * HSEC = High Speed External Connector
+ *
+ * Line names are taken from "hikey970-schematics.pdf" from HiSilicon.
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART2. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+&gpio0 {
+ /* GPIO_000-GPIO_007 */
+ gpio-line-names =
+ "",
+ "TP901", /* TEST_MODE connected to TP901 */
+ "",
+ "GPIO_003_USB_HUB_RESET_N",
+ "NC",
+ "[AP_GPS_REF_CLK]",
+ "[I2C3_SCL]",
+ "[I2C3_SDA]";
+};
+
+&gpio1 {
+ /* GPIO_008-GPIO_015 */
+ gpio-line-names =
+ "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */
+ "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */
+ "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */
+ "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */
+ "[USER_LED5]",
+ "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */
+ "[USER_LED3]",
+ "[USER_LED4]";
+};
+
+&gpio2 {
+ /* GPIO_016-GPIO_023 */
+ gpio-line-names =
+ "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */
+ "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
+ "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
+ "GPIO_019_BT_ACTIVE",
+ "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
+ "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
+ "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
+ "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */
+};
+
+&gpio3 {
+ /* GPIO_024-GPIO_031 */
+ gpio-line-names =
+ "GPIO_024_WIFI_ACTIVE",
+ "GPIO_025_PERST_M.2",
+ "[I2C4_SCL]",
+ "[I2C4_SDA]",
+ "NC",
+ "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */
+ "[USER_LED1]",
+ "GPIO-L"; /* LSEC pin 34: GPIO_031 */
+};
+
+&gpio4 {
+ /* GPIO_032-GPIO_039 */
+ gpio-line-names =
+ "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */
+ "GPIO_033_PMU1_EN",
+ "GPIO_034_USBSW_SEL",
+ /*
+ * These two pins should be used for SD(IO) data according
+ * to the 96boards specification but seems to be repurposed
+ * for UART 0. They are however named according to the spec.
+ */
+ "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */
+ "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */
+ "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */
+ "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
+ "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */
+};
+
+&gpio5 {
+ /* GPIO_040-GPIO_047 */
+ gpio-line-names =
+ "[SOC_GPS_UART3_RTS_N]", /* TP2302 */
+ "[SOC_GPS_UART3_RXD]", /* TP2303 */
+ "[SOC_GPS_UART3_TXD]", /* TP2305 */
+ "[SOC_BT_UART4_CTS_N]",
+ "[SOC_BT_UART4_RTS_N]",
+ "[SOC_BT_UART4_RXD]",
+ "[SOC_BT_UART4_TXD]",
+ "NC";
+};
+
+&gpio6 {
+ /* GPIO_048-GPIO_055 */
+ gpio-line-names =
+ "NC",
+ "GPIO_049_USER_LED6",
+ "GPIO_050_CAN_RST",
+ "GPIO_051_WIFI_EN",
+ "GPIO-D", /* LSEC pin 26 */
+ "GPIO-J", /* LSEC pin 32 */
+ "GPIO_054_BT_EN",
+ "[GPIO_055_SEL]";
+};
+
+&gpio7 {
+ /* GPIO_056-GPIO_063 */
+ gpio-line-names =
+ "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio8 {
+ /* GPIO_064-GPIO_071 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio9 {
+ /* GPIO_072-GPIO_079 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio10 {
+ /* GPIO_080-GPIO_087 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio11 {
+ /* GPIO_088-GPIO_095 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio12 {
+ /* GPIO_096-GPIO_103 */
+ gpio-line-names = "NC", "", "", "", "", "", "", "";
+};
+
+&gpio13 {
+ /* GPIO_104-GPIO_111 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio14 {
+ /* GPIO_112-GPIO_119 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio15 {
+ /* GPIO_120-GPIO_127 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio16 {
+ /* GPIO_128-GPIO_135 */
+ gpio-line-names =
+ "[WL_SDIO_CLK]",
+ "[WL_SDIO_CMD]",
+ "[WL_SDIO_DATA0]",
+ "[WL_SDIO_DATA1]",
+ "[WL_SDIO_DATA2]",
+ "[WL_SDIO_DATA3]",
+ "[ETH_ISOLATE]",
+ "NC";
+};
+
+&gpio17 {
+ /* GPIO_136-GPIO_143 */
+ gpio-line-names =
+ "[MINI1CLK_EN]", "NC", "", "", "", "", "", "";
+};
+
+&gpio18 {
+ /* GPIO_144-GPIO_151 */
+ gpio-line-names =
+ "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */
+ "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */
+ "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */
+ "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */
+ "[POWER_INT_N]",
+ "[CDMA_GPS_SYNC]",
+ "GPIO_150_PEX_INTA",
+ "GPIO_151_CAN_INT";
+};
+
+&gpio19 {
+ /* GPIO_152-GPIO_159 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio20 {
+ /* GPIO_160-GPIO_167 */
+ gpio-line-names =
+ "[SD_CLK]",
+ "[SD_CMD]",
+ "[SD_DATA0]",
+ "[SD_DATA1]",
+ "[SD_DATA2]",
+ "[SD_DATA3]",
+ "GPIO_166_ETHCLK_EN",
+ "GPIO_167_USER_LED2";
+};
+
+&gpio21 {
+ /* GPIO_168-GPIO_175 */
+ gpio-line-names =
+ "GPIO_168_GPS_EN",
+ "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */
+ "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */
+ "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */
+ "", "", "", "", "";
+};
+
+&gpio22 {
+ /* GPIO_176-GPIO_183 */
+ gpio-line-names =
+ "[PMU_PWR_HOLD]",
+ "GPIO_177_WL_WAKEUP_AP",
+ "[JTAG_TCK]",
+ "[JTAG_TMS]",
+ "[JTAG_TDI]",
+ "[JTAG_TMS]",
+ "GPIO_182_FATAL_ERR",
+ "NC";
+};
+
+&gpio23 {
+ /* GPIO_184-GPIO_191 */
+ gpio-line-names =
+ "GPIO_184_JTAG_SEL",
+ "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */
+ "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */
+ "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */
+ "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */
+ "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */
+ "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */
+ "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */
+};
+
+&gpio24 {
+ /* GPIO_192-GPIO_199 */
+ gpio-line-names =
+ "[SD_LED]",
+ "NC",
+ "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */
+ "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */
+ "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */
+ "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */
+ "",
+ "[I2S2_DO]";
+};
+
+&gpio25 {
+ /* GPIO_200-GPIO_207 */
+ gpio-line-names =
+ "[I2S2_XCLK]",
+ "[I2S2_XFS]",
+ "GPIO_202_PERST_ETH",
+ "GPIO_203_PWRON_DET",
+ "GPIO_204_PMU1_IRQ_N",
+ "GPIO_205_SD_DET",
+ "GPIO_206_GPS_MOTION_INT",
+ "GPIO_207_HDMI_SEL";
+};
+
+&gpio26 {
+ /* GPIO_208-GPIO_215 */
+ gpio-line-names =
+ "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */
+ "GPIO_209_VBUS_TYPEC",
+ "NC",
+ "NC",
+ "NC",
+ "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */
+ "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */
+ "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */
+};
+
+&gpio27 {
+ /* GPIO_216-GPIO_223 */
+ gpio-line-names =
+ "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */
+ "GPIO_217_HDMI_PD",
+ "GPIO_218_GPS_WAKEUP_AP",
+ "GPIO_219_M.2CLK_EN",
+ "GPIO_220_PERST_MINI",
+ "GPIO_221_CC_INT",
+ "[PCIE_CLKREQ_L]",
+ "NC";
+};
+
+&gpio28 {
+ /* GPIO_224-GPIO_231 */
+ gpio-line-names =
+ "[PMU0_INT]",
+ "[SPMI_DATA]",
+ "[SPMI_CLK]",
+ "[CAN_SPI_CLK]",
+ "[CAN_SPI_DI]",
+ "[CAN_SPI_DO]",
+ "[CAN_SPI_CS]",
+ "GPIO_231_HDMI_INT";
+};
+
&uart0 {
/* On High speed expansion header */
label = "HS-UART0";
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC
2018-10-23 19:06 [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Manivannan Sadhasivam
` (4 preceding siblings ...)
2018-10-23 19:06 ` [PATCH 5/5] arm64: dts: hisilicon: hikey970: Add GPIO line names Manivannan Sadhasivam
@ 2018-10-31 9:43 ` Linus Walleij
2018-11-12 7:17 ` Manivannan Sadhasivam
5 siblings, 1 reply; 9+ messages in thread
From: Linus Walleij @ 2018-10-31 9:43 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Xu Wei, Rob Herring, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Amit Kucheria, Linux ARM, linux-kernel
On Tue, Oct 23, 2018 at 9:07 PM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> This patchset adds Pinctrl and GPIO support for HI3670 SoC from HiSilicon
> found in the HiKey970 developement board. Also, the remaining UARTs are
> enabled and GPIO line names are added based on the Schematics and the
> 96Boards Consumer Edition spec.
>
> Note: These patches are based on the below common clk patches pushed
> earlier:
>
> arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
> arm64: dts: hisilicon: Source SoC clock for UART6
All looks good to me.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
for the series.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC
2018-10-31 9:43 ` [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC Linus Walleij
@ 2018-11-12 7:17 ` Manivannan Sadhasivam
2018-11-29 15:29 ` Wei Xu
0 siblings, 1 reply; 9+ messages in thread
From: Manivannan Sadhasivam @ 2018-11-12 7:17 UTC (permalink / raw)
To: xuwei5
Cc: linus.walleij, Rob Herring, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Amit Kucheria, Linux ARM, linux-kernel
On Wed, Oct 31, 2018 at 10:43:00AM +0100, Linus Walleij wrote:
> On Tue, Oct 23, 2018 at 9:07 PM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
>
> > This patchset adds Pinctrl and GPIO support for HI3670 SoC from HiSilicon
> > found in the HiKey970 developement board. Also, the remaining UARTs are
> > enabled and GPIO line names are added based on the Schematics and the
> > 96Boards Consumer Edition spec.
> >
> > Note: These patches are based on the below common clk patches pushed
> > earlier:
> >
> > arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
> > arm64: dts: hisilicon: Source SoC clock for UART6
>
> All looks good to me.
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> for the series.
>
Hi Wei,
Any update on this patchset?
Thanks,
Mani
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] Add Pinctrl and GPIO support for HI3670 SoC
2018-11-12 7:17 ` Manivannan Sadhasivam
@ 2018-11-29 15:29 ` Wei Xu
0 siblings, 0 replies; 9+ messages in thread
From: Wei Xu @ 2018-11-29 15:29 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linus.walleij, Rob Herring, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Amit Kucheria, Linux ARM, linux-kernel
Hi Manivannan,
On 2018/11/12 7:17, Manivannan Sadhasivam wrote:
> On Wed, Oct 31, 2018 at 10:43:00AM +0100, Linus Walleij wrote:
>> On Tue, Oct 23, 2018 at 9:07 PM Manivannan Sadhasivam
>> <manivannan.sadhasivam@linaro.org> wrote:
>>
>>> This patchset adds Pinctrl and GPIO support for HI3670 SoC from HiSilicon
>>> found in the HiKey970 developement board. Also, the remaining UARTs are
>>> enabled and GPIO line names are added based on the Schematics and the
>>> 96Boards Consumer Edition spec.
>>>
>>> Note: These patches are based on the below common clk patches pushed
>>> earlier:
>>>
>>> arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
>>> arm64: dts: hisilicon: Source SoC clock for UART6
>>
>> All looks good to me.
>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>> for the series.
>>
>
> Hi Wei,
>
> Any update on this patchset?
Sorry for the late reply!
Series applied to the hisilicon soc dt tree with minor changes
in the subject.
Thanks!
Best Regards,
Wei
>
> Thanks,
> Mani
>
>> Yours,
>> Linus Walleij
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread