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* [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest
@ 2018-11-14 18:15 Borislav Petkov
  2018-11-14 18:15 ` [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Borislav Petkov
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Borislav Petkov @ 2018-11-14 18:15 UTC (permalink / raw)
  To: KVM
  Cc: Paolo Bonzini, Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

From: Borislav Petkov <bp@suse.de>

Hi all,

here's a rediff ontop of -rc2. No changes, only added Yazen's Tested-by.

Please queue,
thx.

Changelog:
==========

v2:

here's v2, dropping patch 3 and incorporating hopefully all of Radim's
feedback.

v1:

there's this mce-inject.ko module in the kernel which allows for
injecting real MCEs and thus test the MCE handling code.

It is doubly useful to be able to inject same MCEs in a guest so that
testing of the MCE handling code can happen even easier/faster. In order
to be able to do that on an AMD guest, we need to emulate some bits
and pieces like the HWCR[McStatusWrEn] bit which allows writes to the
MCi_STATUS registers without a #GP.

The below does that and with it I'm able to properly inject MCEs in said
guest.

--

Borislav Petkov (2):
  kvm/x86: Move MSR_K7_HWCR to svm.c
  x86/kvm: Implement MSR_HWCR support

 arch/x86/kvm/svm.c | 20 ++++++++++++++++++++
 arch/x86/kvm/x86.c | 46 +++++++++++++++++++++++++++++++---------------
 2 files changed, 51 insertions(+), 15 deletions(-)

-- 
2.19.1


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c
  2018-11-14 18:15 [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Borislav Petkov
@ 2018-11-14 18:15 ` Borislav Petkov
  2018-11-26 15:33   ` David Hildenbrand
  2018-11-14 18:15 ` [PATCH v3 2/2] x86/kvm: Implement MSR_HWCR support Borislav Petkov
  2018-11-26 16:41 ` [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Paolo Bonzini
  2 siblings, 1 reply; 6+ messages in thread
From: Borislav Petkov @ 2018-11-14 18:15 UTC (permalink / raw)
  To: KVM
  Cc: Paolo Bonzini, Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

From: Borislav Petkov <bp@suse.de>

This is an AMD-specific MSR. Put it where it belongs.

Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kvm/svm.c | 14 ++++++++++++++
 arch/x86/kvm/x86.c | 12 ------------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 0e21ccc46792..5c9c26dc7d84 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -4154,6 +4154,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_F10H_DECFG:
 		msr_info->data = svm->msr_decfg;
 		break;
+	case MSR_K7_HWCR:
+		msr_info->data = 0;
+		break;
 	default:
 		return kvm_get_msr_common(vcpu, msr_info);
 	}
@@ -4358,6 +4361,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 		svm->msr_decfg = data;
 		break;
 	}
+	case MSR_K7_HWCR:
+		data &= ~(u64)0x40;	/* ignore flush filter disable */
+		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
+		data &= ~(u64)0x8;	/* ignore TLB cache disable */
+		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
+		if (data != 0) {
+			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
+				    data);
+			return 1;
+		}
+		break;
 	case MSR_IA32_APICBASE:
 		if (kvm_vcpu_apicv_active(vcpu))
 			avic_update_vapic_bar(to_svm(vcpu), data);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 5cd5647120f2..d9abbe24deb5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2434,17 +2434,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		break;
 	case MSR_EFER:
 		return set_efer(vcpu, data);
-	case MSR_K7_HWCR:
-		data &= ~(u64)0x40;	/* ignore flush filter disable */
-		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
-		data &= ~(u64)0x8;	/* ignore TLB cache disable */
-		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
-		if (data != 0) {
-			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
-				    data);
-			return 1;
-		}
-		break;
 	case MSR_FAM10H_MMIO_CONF_BASE:
 		if (data != 0) {
 			vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
@@ -2713,7 +2702,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_K8_SYSCFG:
 	case MSR_K8_TSEG_ADDR:
 	case MSR_K8_TSEG_MASK:
-	case MSR_K7_HWCR:
 	case MSR_VM_HSAVE_PA:
 	case MSR_K8_INT_PENDING_MSG:
 	case MSR_AMD64_NB_CFG:
-- 
2.19.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v3 2/2] x86/kvm: Implement MSR_HWCR support
  2018-11-14 18:15 [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Borislav Petkov
  2018-11-14 18:15 ` [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Borislav Petkov
@ 2018-11-14 18:15 ` Borislav Petkov
  2018-11-26 16:41 ` [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Paolo Bonzini
  2 siblings, 0 replies; 6+ messages in thread
From: Borislav Petkov @ 2018-11-14 18:15 UTC (permalink / raw)
  To: KVM
  Cc: Paolo Bonzini, Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

From: Borislav Petkov <bp@suse.de>

The hardware configuration register has some useful bits which can be
used by guests. Implement McStatusWrEn which can be used by guests when
injecting MCEs with the in-kernel mce-inject module.

For that, we need to set bit 18 - McStatusWrEn - first, before writing
the MCi_STATUS registers (otherwise we #GP).

Add the required machinery to do so.

Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kvm/svm.c | 12 +++++++++---
 arch/x86/kvm/x86.c | 34 +++++++++++++++++++++++++++++++---
 2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5c9c26dc7d84..db8e943f7576 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -251,6 +251,9 @@ struct vcpu_svm {
 
 	/* which host CPU was used for running this vcpu */
 	unsigned int last_cpu;
+
+	/* MSRC001_0015 Hardware Configuration */
+	u64 msr_hwcr;
 };
 
 /*
@@ -4155,7 +4158,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		msr_info->data = svm->msr_decfg;
 		break;
 	case MSR_K7_HWCR:
-		msr_info->data = 0;
+		msr_info->data = svm->msr_hwcr;
 		break;
 	default:
 		return kvm_get_msr_common(vcpu, msr_info);
@@ -4365,8 +4368,11 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 		data &= ~(u64)0x40;	/* ignore flush filter disable */
 		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
 		data &= ~(u64)0x8;	/* ignore TLB cache disable */
-		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
-		if (data != 0) {
+
+		/* Handle McStatusWrEn */
+		if (data == BIT_ULL(18)) {
+			svm->msr_hwcr = data;
+		} else if (data != 0) {
 			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
 				    data);
 			return 1;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d9abbe24deb5..607fe883113c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2262,6 +2262,30 @@ static void kvmclock_sync_fn(struct work_struct *work)
 					KVMCLOCK_SYNC_PERIOD);
 }
 
+/*
+ * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
+ */
+static bool __set_mci_status(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
+{
+	if (guest_cpuid_is_amd(vcpu)) {
+		struct msr_data tmp;
+
+		tmp.index = MSR_K7_HWCR;
+
+		if (kvm_x86_ops->get_msr(vcpu, &tmp))
+			return false;
+
+		/* McStatusWrEn enabled? */
+		if (tmp.data & BIT_ULL(18))
+			return true;
+	}
+
+	if (msr_info->data != 0)
+		return false;
+
+	return true;
+}
+
 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
 	u64 mcg_cap = vcpu->arch.mcg_cap;
@@ -2293,9 +2317,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			if ((offset & 0x3) == 0 &&
 			    data != 0 && (data | (1 << 10)) != ~(u64)0)
 				return -1;
-			if (!msr_info->host_initiated &&
-				(offset & 0x3) == 1 && data != 0)
-				return -1;
+
+			/* MCi_STATUS */
+			if ((offset & 0x3) == 1 && !msr_info->host_initiated) {
+				if (!__set_mci_status(vcpu, msr_info))
+						return -1;
+			}
+
 			vcpu->arch.mce_banks[offset] = data;
 			break;
 		}
-- 
2.19.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c
  2018-11-14 18:15 ` [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Borislav Petkov
@ 2018-11-26 15:33   ` David Hildenbrand
  0 siblings, 0 replies; 6+ messages in thread
From: David Hildenbrand @ 2018-11-26 15:33 UTC (permalink / raw)
  To: Borislav Petkov, KVM
  Cc: Paolo Bonzini, Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

On 14.11.18 19:15, Borislav Petkov wrote:
> From: Borislav Petkov <bp@suse.de>
> 
> This is an AMD-specific MSR. Put it where it belongs.
> 
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Tested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
>  arch/x86/kvm/svm.c | 14 ++++++++++++++
>  arch/x86/kvm/x86.c | 12 ------------
>  2 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 0e21ccc46792..5c9c26dc7d84 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -4154,6 +4154,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  	case MSR_F10H_DECFG:
>  		msr_info->data = svm->msr_decfg;
>  		break;
> +	case MSR_K7_HWCR:
> +		msr_info->data = 0;
> +		break;
>  	default:
>  		return kvm_get_msr_common(vcpu, msr_info);
>  	}
> @@ -4358,6 +4361,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
>  		svm->msr_decfg = data;
>  		break;
>  	}
> +	case MSR_K7_HWCR:
> +		data &= ~(u64)0x40;	/* ignore flush filter disable */
> +		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
> +		data &= ~(u64)0x8;	/* ignore TLB cache disable */
> +		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
> +		if (data != 0) {

While touching this, I would turn this into "if (data)". Up to you.

Reviewed-by: David Hildenbrand <david@redhat.com>

> +			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
> +				    data);
> +			return 1;
> +		}
> +		break;
>  	case MSR_IA32_APICBASE:
>  		if (kvm_vcpu_apicv_active(vcpu))
>  			avic_update_vapic_bar(to_svm(vcpu), data);
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 5cd5647120f2..d9abbe24deb5 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2434,17 +2434,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  		break;
>  	case MSR_EFER:
>  		return set_efer(vcpu, data);
> -	case MSR_K7_HWCR:
> -		data &= ~(u64)0x40;	/* ignore flush filter disable */
> -		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
> -		data &= ~(u64)0x8;	/* ignore TLB cache disable */
> -		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
> -		if (data != 0) {
> -			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
> -				    data);
> -			return 1;
> -		}
> -		break;
>  	case MSR_FAM10H_MMIO_CONF_BASE:
>  		if (data != 0) {
>  			vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
> @@ -2713,7 +2702,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  	case MSR_K8_SYSCFG:
>  	case MSR_K8_TSEG_ADDR:
>  	case MSR_K8_TSEG_MASK:
> -	case MSR_K7_HWCR:
>  	case MSR_VM_HSAVE_PA:
>  	case MSR_K8_INT_PENDING_MSG:
>  	case MSR_AMD64_NB_CFG:
> 


-- 

Thanks,

David / dhildenb

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest
  2018-11-14 18:15 [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Borislav Petkov
  2018-11-14 18:15 ` [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Borislav Petkov
  2018-11-14 18:15 ` [PATCH v3 2/2] x86/kvm: Implement MSR_HWCR support Borislav Petkov
@ 2018-11-26 16:41 ` Paolo Bonzini
  2019-01-13 14:37   ` Borislav Petkov
  2 siblings, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2018-11-26 16:41 UTC (permalink / raw)
  To: Borislav Petkov, KVM
  Cc: Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

On 14/11/18 19:15, Borislav Petkov wrote:
> From: Borislav Petkov <bp@suse.de>
> 
> Hi all,
> 
> here's a rediff ontop of -rc2. No changes, only added Yazen's Tested-by.
> 
> Please queue,
> thx.
> 
> Changelog:
> ==========
> 
> v2:
> 
> here's v2, dropping patch 3 and incorporating hopefully all of Radim's
> feedback.
> 
> v1:
> 
> there's this mce-inject.ko module in the kernel which allows for
> injecting real MCEs and thus test the MCE handling code.
> 
> It is doubly useful to be able to inject same MCEs in a guest so that
> testing of the MCE handling code can happen even easier/faster. In order
> to be able to do that on an AMD guest, we need to emulate some bits
> and pieces like the HWCR[McStatusWrEn] bit which allows writes to the
> MCi_STATUS registers without a #GP.
> 
> The below does that and with it I'm able to properly inject MCEs in said
> guest.
> 
> --
> 
> Borislav Petkov (2):
>   kvm/x86: Move MSR_K7_HWCR to svm.c
>   x86/kvm: Implement MSR_HWCR support
> 
>  arch/x86/kvm/svm.c | 20 ++++++++++++++++++++
>  arch/x86/kvm/x86.c | 46 +++++++++++++++++++++++++++++++---------------
>  2 files changed, 51 insertions(+), 15 deletions(-)
> 

Queued, thanks.

Paolo

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest
  2018-11-26 16:41 ` [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Paolo Bonzini
@ 2019-01-13 14:37   ` Borislav Petkov
  0 siblings, 0 replies; 6+ messages in thread
From: Borislav Petkov @ 2019-01-13 14:37 UTC (permalink / raw)
  To: Paolo Bonzini
  Cc: KVM, Radim Krčmář,
	Joerg Roedel, Tom Lendacky, Tony Luck, Yazen Ghannam, LKML

On Mon, Nov 26, 2018 at 05:41:21PM +0100, Paolo Bonzini wrote:
> On 14/11/18 19:15, Borislav Petkov wrote:
> > From: Borislav Petkov <bp@suse.de>
> > 
> > Hi all,
> > 
> > here's a rediff ontop of -rc2. No changes, only added Yazen's Tested-by.
> > 
> > Please queue,
> > thx.
> > 
> > Changelog:
> > ==========
> > 
> > v2:
> > 
> > here's v2, dropping patch 3 and incorporating hopefully all of Radim's
> > feedback.
> > 
> > v1:
> > 
> > there's this mce-inject.ko module in the kernel which allows for
> > injecting real MCEs and thus test the MCE handling code.
> > 
> > It is doubly useful to be able to inject same MCEs in a guest so that
> > testing of the MCE handling code can happen even easier/faster. In order
> > to be able to do that on an AMD guest, we need to emulate some bits
> > and pieces like the HWCR[McStatusWrEn] bit which allows writes to the
> > MCi_STATUS registers without a #GP.
> > 
> > The below does that and with it I'm able to properly inject MCEs in said
> > guest.
> > 
> > --
> > 
> > Borislav Petkov (2):
> >   kvm/x86: Move MSR_K7_HWCR to svm.c
> >   x86/kvm: Implement MSR_HWCR support
> > 
> >  arch/x86/kvm/svm.c | 20 ++++++++++++++++++++
> >  arch/x86/kvm/x86.c | 46 +++++++++++++++++++++++++++++++---------------
> >  2 files changed, 51 insertions(+), 15 deletions(-)
> > 
> 
> Queued, thanks.

Where?

I don't see them in rc1...

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-01-13 14:37 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-14 18:15 [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Borislav Petkov
2018-11-14 18:15 ` [PATCH v3 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Borislav Petkov
2018-11-26 15:33   ` David Hildenbrand
2018-11-14 18:15 ` [PATCH v3 2/2] x86/kvm: Implement MSR_HWCR support Borislav Petkov
2018-11-26 16:41 ` [PATCH v3 0/2] x86/kvm: Enable MCE injection in the guest Paolo Bonzini
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