[PATCH 0/6] 32-bit Meson: add the ARM TWD and Global Timers

[PATCH 0/6] 32-bit Meson: add the ARM TWD and Global Timers

[Martin Blumenstingl]

The 32-bit Meson SoCs use Cortex-A9 or Cortex-A5 cores. These come
with the ARM TWD ("Timer Watchdog") which contains a timer and a
watchdog as well as the ARM Global Timer.

This enables the corresponding configs for the 32-bit Meson target.
Additionally this adds and enables the ARM TWD timer. The Global
Timer is added but currently disabled because it's clock input is
the PERIPH clock which is derived from the CPU clock. Thus the rate
of the PERIPH clock will change when changing the CPU frequency.
Unfortunately the Global Timer driver doesn't handle clocks with
changing rates yet (unlike the TWD timer), thus we keep it disabled
for now.

The whole series is inspired by an almost 3 year old patch from
Carlo: [0]


Dependencies:
- I build this on top of my other series "ARM: dts: meson: add the
  timer interrupts and clocks" from [1]
- CLKID_PERIPH requires updated clock driver headers. Neil provided
  a tag which includes the updated headers: [2]
- There is no runtime dependency on the PERIPH clock as we don't
  have CPU frequency scaling support enabled yet. In case the TWD
  timer driver can't find the clock it falls back to auto-detecting
  the clock rate at boot time. This is safe as long as we don't have
  .dts patches in place which allow changing the CPU clock rate. Once
  we enable CPU frequency scaling support for the PERIPH clock becomes
  mandatory so the TWD timer driver knows about changes to the PERIPH
  clock (which is derived from the CPU clock).


[0] https://patchwork.kernel.org/patch/7797581/
[1] https://patchwork.kernel.org/cover/10687005/
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009136.html


Martin Blumenstingl (6):
  ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER
  ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals
  ARM: dts: meson8: add the ARM TWD timer
  ARM: dts: meson8: add the Cortex-A9 global timer
  ARM: dts: meson8b: add the ARM TWD timer
  ARM: dts: meson8b: add the Cortex-A5 global timer

 arch/arm/boot/dts/meson.dtsi   | 24 ++++++++++++++++--------
 arch/arm/boot/dts/meson8.dtsi  | 32 +++++++++++++++++++++++++++-----
 arch/arm/boot/dts/meson8b.dtsi | 32 +++++++++++++++++++++++++++-----
 arch/arm/mach-meson/Kconfig    |  2 ++
 4 files changed, 72 insertions(+), 18 deletions(-)

-- 
2.19.2

[PATCH 1/6] ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER

[Martin Blumenstingl]

The 32-bit Meson SoCs use multiple Cortex-A9 (Meson8 and Meson8m2) or
Cortex-A5 (Meson8b) CPU cores. These come with the "ARM global timer"
and "Timer-Watchdog" (aka TWD, which provides both a per-cpu local timer
and watchdog).

Selecting ARM_GLOBAL_TIMER and HAVE_ARM_TWD allows us to add the timers
to the SoC.dtsi files.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/mach-meson/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index d51cfda953d4..b16831697183 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -4,12 +4,14 @@ menuconfig ARCH_MESON
 	select GPIOLIB
 	select GENERIC_IRQ_CHIP
 	select ARM_GIC
+	select ARM_GLOBAL_TIMER
 	select CACHE_L2X0
 	select PINCTRL
 	select PINCTRL_MESON
 	select COMMON_CLK
 	select COMMON_CLK_AMLOGIC
 	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
 
 if ARCH_MESON
 
-- 
2.19.2

[PATCH 2/6] ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals

[Martin Blumenstingl]

The public Meson8b (S805) datasheet describes a memory region called "A9
Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a
simple-bus node and move all peripherals that are part of this memory
region.
This makes the .dts a bit easier to read. No functional changes.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi   | 24 ++++++++++++++++--------
 arch/arm/boot/dts/meson8.dtsi  | 12 +++++++-----
 arch/arm/boot/dts/meson8b.dtsi | 12 +++++++-----
 3 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 0839da07a75c..e4645f612712 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -59,14 +59,6 @@
 		cache-level = <2>;
 	};
 
-	gic: interrupt-controller@c4301000 {
-		compatible = "arm,cortex-a9-gic";
-		reg = <0xc4301000 0x1000>,
-		      <0xc4300100 0x0100>;
-		interrupt-controller;
-		#interrupt-cells = <3>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -207,6 +199,22 @@
 			};
 		};
 
+		periph: bus@c4300000 {
+			compatible = "simple-bus";
+			reg = <0xc4300000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xc4300000 0x10000>;
+
+			gic: interrupt-controller@1000 {
+				compatible = "arm,cortex-a9-gic";
+				reg = <0x1000 0x1000>,
+				      <0x100 0x100>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+			};
+		};
+
 		aobus: aobus@c8100000 {
 			compatible = "simple-bus";
 			reg = <0xc8100000 0x100000>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 3be5fbd07997..28b9f6779993 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -129,11 +129,6 @@
 			no-map;
 		};
 	};
-
-	scu@c4300000 {
-		compatible = "arm,cortex-a9-scu";
-		reg = <0xc4300000 0x100>;
-	};
 }; /* end of / */
 
 &aobus {
@@ -362,6 +357,13 @@
 	arm,shared-override;
 };
 
+&periph {
+	scu@0 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0x0 0x100>;
+	};
+};
+
 &pwm_ab {
 	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 };
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 587a855f872b..6b097ab8637f 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -112,11 +112,6 @@
 			no-map;
 		};
 	};
-
-	scu@c4300000 {
-		compatible = "arm,cortex-a5-scu";
-		reg = <0xc4300000 0x100>;
-	};
 }; /* end of / */
 
 &aobus {
@@ -349,6 +344,13 @@
 	arm,shared-override;
 };
 
+&periph {
+	scu@0 {
+		compatible = "arm,cortex-a5-scu";
+		reg = <0x0 0x100>;
+	};
+};
+
 &pwm_ab {
 	compatible = "amlogic,meson8b-pwm";
 };
-- 
2.19.2

[PATCH 3/6] ARM: dts: meson8: add the ARM TWD timer

[Martin Blumenstingl]

The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which
come with a "TWD" (Timer-Watchdog) based timer. This adds support for
the ARM TWD Timer on these two SoCs.

Suggested-by: Carlo Caione <carlo@endlessm.com>
[ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of
  IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
  message during boot, use pre-processor macros to specify the IRQ,
  added the correct clock, dropped TWD watchdog node since there's no
  driver for it anymore ]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 28b9f6779993..2b0b3edbd896 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -362,6 +362,13 @@
 		compatible = "arm,cortex-a9-scu";
 		reg = <0x0 0x100>;
 	};
+
+	timer@600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0x600 0x20>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_PERIPH>;
+	};
 };
 
 &pwm_ab {
-- 
2.19.2

Re: [PATCH 3/6] ARM: dts: meson8: add the ARM TWD timer

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1138 bytes --]

Hi Martin,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.20-rc4 next-20181130]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Martin-Blumenstingl/32-bit-Meson-add-the-ARM-TWD-and-Global-Timers/20181124-133849
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/meson8.dtsi:358.19-20 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 44774 bytes --]

[PATCH 4/6] ARM: dts: meson8: add the Cortex-A9 global timer

[Martin Blumenstingl]

The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come
with an ARM global timer.
This adds the Cortex-A9 global timer but keeps it disabled for now. The
timer is clocked by the "PERIPH" clock whose rate can change during
runtime (when changing the frequency of the CPU clock). Unfortunately
the arm_global_timer driver does not handle changes to the clock rate
yet.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 2b0b3edbd896..2575a5835567 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -363,6 +363,19 @@
 		reg = <0x0 0x100>;
 	};
 
+	timer@200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x200 0x20>;
+		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_PERIPH>;
+
+		/*
+		 * the arm_global_timer driver currently does not handle clock
+		 * rate changes. Keep it disabled for now.
+		 */
+		status = "disabled";
+	};
+
 	timer@600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x600 0x20>;
-- 
2.19.2

[PATCH 5/6] ARM: dts: meson8b: add the ARM TWD timer

[Martin Blumenstingl]

The Meson8B SoC is using four ARM Cortex-A5 cores which come with a
"TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD
Timer on this SoC.

Suggested-by: Carlo Caione <carlo@endlessm.com>
[ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of
  IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
  message during boot, use pre-processor macros to specify the IRQ,
  added the correct clock, dropped TWD watchdog node since there's no
  driver for it anymore ]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 6b097ab8637f..a3a5649e32fa 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -349,6 +349,13 @@
 		compatible = "arm,cortex-a5-scu";
 		reg = <0x0 0x100>;
 	};
+
+	timer@600 {
+		compatible = "arm,cortex-a5-twd-timer";
+		reg = <0x600 0x20>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_PERIPH>;
+	};
 };
 
 &pwm_ab {
-- 
2.19.2

Re: [PATCH 5/6] ARM: dts: meson8b: add the ARM TWD timer

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1139 bytes --]

Hi Martin,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.20-rc4 next-20181130]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Martin-Blumenstingl/32-bit-Meson-add-the-ARM-TWD-and-Global-Timers/20181124-133849
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/meson8b.dtsi:348.19-20 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 44774 bytes --]

[PATCH 6/6] ARM: dts: meson8b: add the Cortex-A5 global timer

[Martin Blumenstingl]

The Meson8b SoC is using four Cortex-A5 cores. These come with an ARM
global timer.
This adds the Cortex-A5 global timer but keeps it disabled for now. The
timer is clocked by the "PERIPH" clock whose rate can change during
runtime (when changing the frequency of the CPU clock). Unfortunately
the arm_global_timer driver does not handle changes to the clock rate
yet.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index a3a5649e32fa..a38d187d3d6e 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -350,6 +350,19 @@
 		reg = <0x0 0x100>;
 	};
 
+	timer@200 {
+		compatible = "arm,cortex-a5-global-timer";
+		reg = <0x200 0x20>;
+		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+		clocks = <&clkc CLKID_PERIPH>;
+
+		/*
+		 * the arm_global_timer driver currently does not handle clock
+		 * rate changes. Keep it disabled for now.
+		 */
+		status = "disabled";
+	};
+
 	timer@600 {
 		compatible = "arm,cortex-a5-twd-timer";
 		reg = <0x600 0x20>;
-- 
2.19.2

Re: [PATCH 0/6] 32-bit Meson: add the ARM TWD and Global Timers

[Martin Blumenstingl]

Hi Kevin,

On Fri, Nov 23, 2018 at 8:53 PM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> The 32-bit Meson SoCs use Cortex-A9 or Cortex-A5 cores. These come
> with the ARM TWD ("Timer Watchdog") which contains a timer and a
> watchdog as well as the ARM Global Timer.
>
> This enables the corresponding configs for the 32-bit Meson target.
> Additionally this adds and enables the ARM TWD timer. The Global
> Timer is added but currently disabled because it's clock input is
> the PERIPH clock which is derived from the CPU clock. Thus the rate
> of the PERIPH clock will change when changing the CPU frequency.
> Unfortunately the Global Timer driver doesn't handle clocks with
> changing rates yet (unlike the TWD timer), thus we keep it disabled
> for now.
>
> The whole series is inspired by an almost 3 year old patch from
> Carlo: [0]
>
>
> Dependencies:
> - I build this on top of my other series "ARM: dts: meson: add the
>   timer interrupts and clocks" from [1]
this is already merged into your v4.21/dt branch

> - CLKID_PERIPH requires updated clock driver headers. Neil provided
>   a tag which includes the updated headers: [2]
this is still a dependency which you could easily pull in

> - There is no runtime dependency on the PERIPH clock as we don't
>   have CPU frequency scaling support enabled yet. In case the TWD
>   timer driver can't find the clock it falls back to auto-detecting
>   the clock rate at boot time. This is safe as long as we don't have
>   .dts patches in place which allow changing the CPU clock rate. Once
>   we enable CPU frequency scaling support for the PERIPH clock becomes
>   mandatory so the TWD timer driver knows about changes to the PERIPH
>   clock (which is derived from the CPU clock).
and there's still not a hard runtime dependency until you apply [3]
"ARM: dts: enable CPU frequency scaling on Meson8/Meson8b"

> Martin Blumenstingl (6):
>   ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER
>   ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals
>   ARM: dts: meson8: add the ARM TWD timer
>   ARM: dts: meson8: add the Cortex-A9 global timer
>   ARM: dts: meson8b: add the ARM TWD timer
>   ARM: dts: meson8b: add the Cortex-A5 global timer
>
>  arch/arm/boot/dts/meson.dtsi   | 24 ++++++++++++++++--------
>  arch/arm/boot/dts/meson8.dtsi  | 32 +++++++++++++++++++++++++++-----
>  arch/arm/boot/dts/meson8b.dtsi | 32 +++++++++++++++++++++++++++-----
>  arch/arm/mach-meson/Kconfig    |  2 ++
>  4 files changed, 72 insertions(+), 18 deletions(-)
if you plan to send another pull-request to the arm-soc tree then
please consider including this series.
it fixes some harmless (but still noisy) warnings during boot which
also also seen by Odroid-C1 in your KernelCI lab:
  Clockevents: could not switch to one-shot mode:
   dummy_timer is not functional.
  Clockevents: could not switch to one-shot mode:
   dummy_timer is not functional.
  Clockevents: could not switch to one-shot mode:
   dummy_timer is not functional.
  Clockevents: could not switch to one-shot mode:
   dummy_timer is not functional.
  Could not switch to high resolution mode on CPU 3
  Could not switch to high resolution mode on CPU 2
  Could not switch to high resolution mode on CPU 0
  Could not switch to high resolution mode on CPU 1


Regards
Martin


[0] https://patchwork.kernel.org/patch/7797581/
[1] https://patchwork.kernel.org/cover/10687005/
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009136.html
[3] https://patchwork.kernel.org/cover/10705475/

Re: [PATCH 0/6] 32-bit Meson: add the ARM TWD and Global Timers

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> The 32-bit Meson SoCs use Cortex-A9 or Cortex-A5 cores. These come
> with the ARM TWD ("Timer Watchdog") which contains a timer and a
> watchdog as well as the ARM Global Timer.
>
> This enables the corresponding configs for the 32-bit Meson target.
> Additionally this adds and enables the ARM TWD timer. The Global
> Timer is added but currently disabled because it's clock input is
> the PERIPH clock which is derived from the CPU clock. Thus the rate
> of the PERIPH clock will change when changing the CPU frequency.
> Unfortunately the Global Timer driver doesn't handle clocks with
> changing rates yet (unlike the TWD timer), thus we keep it disabled
> for now.
>
> The whole series is inspired by an almost 3 year old patch from
> Carlo: [0]
>
>
> Dependencies:
> - I build this on top of my other series "ARM: dts: meson: add the
>   timer interrupts and clocks" from [1]
> - CLKID_PERIPH requires updated clock driver headers. Neil provided
>   a tag which includes the updated headers: [2]

I pulled this branch into v4.21/dt

> - There is no runtime dependency on the PERIPH clock as we don't
>   have CPU frequency scaling support enabled yet. In case the TWD
>   timer driver can't find the clock it falls back to auto-detecting
>   the clock rate at boot time. This is safe as long as we don't have
>   .dts patches in place which allow changing the CPU clock rate. Once
>   we enable CPU frequency scaling support for the PERIPH clock becomes
>   mandatory so the TWD timer driver knows about changes to the PERIPH
>   clock (which is derived from the CPU clock).
>
>
> [0] https://patchwork.kernel.org/patch/7797581/
> [1] https://patchwork.kernel.org/cover/10687005/
> [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009136.html
>
>
> Martin Blumenstingl (6):
>   ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER

Applied to v4.21/defconfig

>   ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals
>   ARM: dts: meson8: add the ARM TWD timer
>   ARM: dts: meson8: add the Cortex-A9 global timer
>   ARM: dts: meson8b: add the ARM TWD timer
>   ARM: dts: meson8b: add the Cortex-A5 global timer

Applied to v4.21/dt

Kevin