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From: Lina Iyer <ilina@codeaurora.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: evgreen@chromium.org, marc.zyngier@arm.com,
	linux-kernel@vger.kernel.org, rplsssn@codeaurora.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	thierry.reding@gmail.com
Subject: Re: [RFC v3 2/3] dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO
Date: Mon, 26 Nov 2018 09:14:55 -0700	[thread overview]
Message-ID: <20181126161455.GA28236@codeaurora.org> (raw)
In-Reply-To: <154283618199.88331.10217252750356423959@swboyd.mtv.corp.google.com>

On Wed, Nov 21 2018 at 14:36 -0700, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-11-20 16:06:47)
>> SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
>> routed to the PDC as interrupts that can be used to wake the system up
>> from deep low power modes and suspend.
>>
>> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
>> ---
>>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 31 ++++++++++++++++++-
>>  1 file changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> index 665aadb5ea28..bedfa0b57fa6 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> @@ -29,6 +29,17 @@ SDM845 platform.
>>         Definition: must be 2. Specifying the pin number and flags, as defined
>>                     in <dt-bindings/interrupt-controller/irq.h>
>>
>> +- wakeup-parent:
>> +       Usage: optional
>> +       Value type: <phandle>
>> +       Definition: A phandle to the wakeup interrupt controller for the SoC.
>> +
>> +- wakeup-irq:
>
>This shouldn't be needed. TLMM driver can probe for the possibility of
>wakeup capable irqs from irq allocation step. The only place we should
>need to know what TLMM pins map to what PDC lines is in the PDC driver.
>
Why? Every driver seems to translate the hardware IRQ and pass it to
it's parent. Why should this be any different ? The PDC is an interrupt
controller that just knows an interrupt port and maps it to the GIC. Not
sure, I understand the reasoning for this. It seems to add more
confusing relationship with the PDC interrupt controller, that way.

-- Lina


  reply	other threads:[~2018-11-26 16:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-21  0:06 [RFC v3 0/3] qcom: GPIO IRQ wakeup using PDC irqchip Lina Iyer
2018-11-21  0:06 ` [RFC v3 1/3] drivers: pinctrl: msm: setup gpio irqchip in hierarchy with pdc irqchip Lina Iyer
2018-11-21  0:06 ` [RFC v3 2/3] dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO Lina Iyer
2018-11-21 21:36   ` Stephen Boyd
2018-11-26 16:14     ` Lina Iyer [this message]
2018-11-27  9:12       ` Stephen Boyd
2018-11-27 18:21         ` Lina Iyer
2018-11-27 21:45           ` Stephen Boyd
2018-11-28 17:39             ` Lina Iyer
2018-11-29  0:24               ` Bjorn Andersson
2018-11-29 21:45                 ` Lina Iyer
2018-11-30  7:10                   ` Bjorn Andersson
2018-11-30 18:33                   ` Lina Iyer
2018-12-03 23:48                     ` Stephen Boyd
2018-12-18 18:01                       ` Lina Iyer
2018-11-21  0:06 ` [RFC v3 3/3] arm64: dts: msm: add PDC wake irq maps for GPIOs for SDM845 Lina Iyer

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