From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>
Cc: ashok.raj@intel.com, sanjay.k.kumar@intel.com,
jacob.jun.pan@intel.com, kevin.tian@intel.com,
yi.l.liu@intel.com, yi.y.sun@intel.com, peterx@redhat.com,
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Lu Baolu <baolu.lu@linux.intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: [PATCH v5 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support
Date: Wed, 28 Nov 2018 11:54:44 +0800 [thread overview]
Message-ID: <20181128035449.10226-8-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20181128035449.10226-1-baolu.lu@linux.intel.com>
when the scalable mode is enabled, there is no second level
page translation pointer in the context entry any more (for
DMA request without PASID). Instead, a new RID2PASID field
is introduced in the context entry. Software can choose any
PASID value to set RID2PASID and then setup the translation
in the corresponding PASID entry. Upon receiving a DMA request
without PASID, hardware will firstly look at this RID2PASID
field and then treat this request as a request with a pasid
value specified in RID2PASID field.
Though software is allowed to use any PASID for the RID2PASID,
we will always use the PASID 0 as a sort of design decision.
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com>
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Ashok Raj <ashok.raj@intel.com>
---
drivers/iommu/intel-iommu.c | 19 +++++++++++++++++++
drivers/iommu/intel-pasid.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 373fda89aaa4..a63aa01a2e88 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -2457,6 +2457,21 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
spin_unlock_irqrestore(&device_domain_lock, flags);
return NULL;
}
+
+ /* Setup the PASID entry for requests without PASID: */
+ spin_lock(&iommu->lock);
+ if (hw_pass_through && domain_type_is_si(domain))
+ ret = intel_pasid_setup_pass_through(iommu, domain,
+ dev, PASID_RID2PASID);
+ else
+ ret = intel_pasid_setup_second_level(iommu, domain,
+ dev, PASID_RID2PASID);
+ spin_unlock(&iommu->lock);
+ if (ret) {
+ __dmar_remove_one_dev_info(info);
+ spin_unlock_irqrestore(&device_domain_lock, flags);
+ return NULL;
+ }
}
spin_unlock_irqrestore(&device_domain_lock, flags);
@@ -4821,6 +4836,10 @@ static void __dmar_remove_one_dev_info(struct device_domain_info *info)
iommu = info->iommu;
if (info->dev) {
+ if (dev_is_pci(info->dev) && sm_supported(iommu))
+ intel_pasid_tear_down_entry(iommu, info->dev,
+ PASID_RID2PASID);
+
iommu_disable_dev_iotlb(info);
domain_context_clear(iommu, info->dev);
intel_pasid_free_table(info->dev);
diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
index 3c70522091d3..d6f4fead4491 100644
--- a/drivers/iommu/intel-pasid.h
+++ b/drivers/iommu/intel-pasid.h
@@ -10,6 +10,7 @@
#ifndef __INTEL_PASID_H
#define __INTEL_PASID_H
+#define PASID_RID2PASID 0x0
#define PASID_MIN 0x1
#define PASID_MAX 0x100000
#define PASID_PTE_MASK 0x3F
--
2.17.1
next prev parent reply other threads:[~2018-11-28 3:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 3:54 [PATCH v5 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-11-28 3:54 ` [PATCH v5 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-11-28 3:54 ` [PATCH v5 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-12-03 13:44 ` Joerg Roedel
2018-12-03 17:23 ` Liu, Yi L
2018-12-04 5:58 ` Lu Baolu
2018-12-05 15:50 ` Joerg Roedel
2018-12-06 1:13 ` Lu Baolu
2018-12-05 15:47 ` Joerg Roedel
2018-11-28 3:54 ` [PATCH v5 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-11-28 3:54 ` [PATCH v5 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-12-03 13:48 ` Joerg Roedel
2018-12-03 17:23 ` Liu, Yi L
2018-12-04 6:13 ` Lu Baolu
2018-12-05 15:56 ` Joerg Roedel
2018-12-06 1:19 ` Lu Baolu
2018-11-28 3:54 ` [PATCH v5 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-11-28 3:54 ` [PATCH v5 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-11-28 3:54 ` Lu Baolu [this message]
2018-11-28 3:54 ` [PATCH v5 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-11-28 3:54 ` [PATCH v5 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-11-28 3:54 ` [PATCH v5 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-11-28 3:54 ` [PATCH v5 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-11-28 3:54 ` [PATCH v5 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu
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