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From: Joerg Roedel <joro@8bytes.org>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: "Liu, Yi L" <yi.l.liu@intel.com>,
	David Woodhouse <dwmw2@infradead.org>,
	"Raj, Ashok" <ashok.raj@intel.com>,
	"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
	"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
	"Tian, Kevin" <kevin.tian@intel.com>,
	"Sun, Yi Y" <yi.y.sun@intel.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [PATCH v5 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support
Date: Wed, 5 Dec 2018 16:56:46 +0100	[thread overview]
Message-ID: <20181205155646.GD16835@8bytes.org> (raw)
In-Reply-To: <3b0eadd2-b99f-98d6-594f-0419f0542789@linux.intel.com>

On Tue, Dec 04, 2018 at 02:13:31PM +0800, Lu Baolu wrote:
> The existing code uses GFP_ATOMIC, this patch only changes the size of
> the allocated desc_page.
> 
> I don't think we really need GFP_ATOMIC here (and also for some other
> places). I will clean up them in a separated patch.

Okay, thanks.

> > In this patch, there is some code like the code below. It calculates
> > destination address of memcpy with qi->desc. If it's still struct qi_desc
> > pointer, the calculation result would be wrong.
> > 
> > +			memcpy(desc, qi->desc + (wait_index << shift),
> > +			       1 << shift);
> > 
> > The change of the calculation method is to support 128 bits invalidation
> > descriptors and 256 invalidation descriptors in this unified code logic.
> > 
> > Also, the conversation between Baolu and me may help.
> > 
> > https://lore.kernel.org/patchwork/patch/1006756/
> 
> Yes. We need to support different descriptor size.

Okay, pointer arithmetic on void* isn't well defined in the C standard,
afaik. But it should work with GCC, so it's probably fine.

Unrelated to this patch-set, the whole qi management code needs some
cleanups, it queues a sync after every command and has very tricky
locking. This patch-set further complicates matters there, so it is
probably time for a clean re-write of that part?

Regards,

	Joerg

  reply	other threads:[~2018-12-05 15:56 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28  3:54 [PATCH v5 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-11-28  3:54 ` [PATCH v5 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-11-28  3:54 ` [PATCH v5 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-12-03 13:44   ` Joerg Roedel
2018-12-03 17:23     ` Liu, Yi L
2018-12-04  5:58       ` Lu Baolu
2018-12-05 15:50         ` Joerg Roedel
2018-12-06  1:13           ` Lu Baolu
2018-12-05 15:47       ` Joerg Roedel
2018-11-28  3:54 ` [PATCH v5 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-11-28  3:54 ` [PATCH v5 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-12-03 13:48   ` Joerg Roedel
2018-12-03 17:23     ` Liu, Yi L
2018-12-04  6:13       ` Lu Baolu
2018-12-05 15:56         ` Joerg Roedel [this message]
2018-12-06  1:19           ` Lu Baolu
2018-11-28  3:54 ` [PATCH v5 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-11-28  3:54 ` [PATCH v5 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-11-28  3:54 ` [PATCH v5 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-11-28  3:54 ` [PATCH v5 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-11-28  3:54 ` [PATCH v5 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-11-28  3:54 ` [PATCH v5 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-11-28  3:54 ` [PATCH v5 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-11-28  3:54 ` [PATCH v5 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu

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