From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>
Cc: baolu.lu@linux.intel.com, David Woodhouse <dwmw2@infradead.org>,
"Raj, Ashok" <ashok.raj@intel.com>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"Sun, Yi Y" <yi.y.sun@intel.com>,
"peterx@redhat.com" <peterx@redhat.com>,
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [PATCH v5 02/12] iommu/vt-d: Manage scalalble mode PASID tables
Date: Tue, 4 Dec 2018 13:58:06 +0800 [thread overview]
Message-ID: <5c81008b-30e8-177d-0182-db366608562f@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C257439D838B9@SHSMSX104.ccr.corp.intel.com>
Hi,
On 12/4/18 1:23 AM, Liu, Yi L wrote:
> Hi Joerg,
>
>> From: Joerg Roedel [mailto:joro@8bytes.org]
>> Sent: Monday, December 3, 2018 5:44 AM
>> To: Lu Baolu <baolu.lu@linux.intel.com>
>> Subject: Re: [PATCH v5 02/12] iommu/vt-d: Manage scalalble mode PASID tables
>>
>> Hi Baolu,
>>
>> On Wed, Nov 28, 2018 at 11:54:39AM +0800, Lu Baolu wrote:
>>> @@ -2482,12 +2482,13 @@ static struct dmar_domain
>> *dmar_insert_one_dev_info(struct intel_iommu *iommu,
>>> if (dev)
>>> dev->archdata.iommu = info;
>>>
>>> - if (dev && dev_is_pci(dev) && info->pasid_supported) {
>>> + /* PASID table is mandatory for a PCI device in scalable mode. */
>>> + if (dev && dev_is_pci(dev) && sm_supported(iommu)) {
>>
>> This will also allocate a PASID table if the device does not support
>> PASIDs, right? Will the table not be used in that case or will the
>> device just use the fallback PASID? Isn't it better in that case to have
>> no PASID table?
>
> We need to allocate the PASID table in scalable mode, the reason is as below:
> In VT-d scalable mode, all address translation is done in PASID-granularity.
> For requests-with-PASID, the address translation would be subjected to the
> PASID entry specified by the PASID value in the DMA request. However, for
> requests-without-PASID, there is no PASID in the DMA request. To fulfil
> the translation logic, we've introduced RID2PASID field in sm-context-entry
> in VT-d 3.o spec. So that such DMA requests would be subjected to the pasid
> entry specified by the PASID value in the RID2PASID field of sm-context-entry.
>
> So for a device without PASID support, we need to at least to have a PASID
> entry so that its DMA request (without pasid) can be translated. Thus a PASID
> table is needed for such devices.
>
>>
>>> @@ -143,18 +143,20 @@ int intel_pasid_alloc_table(struct device *dev)
>>> return -ENOMEM;
>>> INIT_LIST_HEAD(&pasid_table->dev);
>>>
>>> - size = sizeof(struct pasid_entry);
>>> - count = min_t(int, pci_max_pasids(to_pci_dev(dev)), intel_pasid_max_id);
>>> - order = get_order(size * count);
>>> + if (info->pasid_supported)
>>> + max_pasid = min_t(int, pci_max_pasids(to_pci_dev(dev)),
>>> + intel_pasid_max_id);
>>> +
>>> + size = max_pasid >> (PASID_PDE_SHIFT - 3);
>>> + order = size ? get_order(size) : 0;
>>> pages = alloc_pages_node(info->iommu->node,
>>> - GFP_ATOMIC | __GFP_ZERO,
>>> - order);
>>> + GFP_ATOMIC | __GFP_ZERO, order);
>>
>> This is a simple data structure allocation path, does it need
>> GFP_ATOMIC?
>
This function is called in an unsleepable context.
spin_lock(&lock)
[...]
if (pasid_table_is_necessary)
allocate_pasid_table(dev)
[...]
spin_unlock(&lock)
We can move it out of the lock range.
How about
if (pasid_table_is_necessary)
pasid_table = allocate_pasid_table(dev)
spin_lock(&lock)
[...]
if (pasid_table_is_necessary)
set_up_pasid_table(pasid_table)
[...]
spin_unlock(&lock)
?
Best regards,
Lu Baolu
next prev parent reply other threads:[~2018-12-04 6:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 3:54 [PATCH v5 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-11-28 3:54 ` [PATCH v5 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-11-28 3:54 ` [PATCH v5 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-12-03 13:44 ` Joerg Roedel
2018-12-03 17:23 ` Liu, Yi L
2018-12-04 5:58 ` Lu Baolu [this message]
2018-12-05 15:50 ` Joerg Roedel
2018-12-06 1:13 ` Lu Baolu
2018-12-05 15:47 ` Joerg Roedel
2018-11-28 3:54 ` [PATCH v5 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-11-28 3:54 ` [PATCH v5 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-12-03 13:48 ` Joerg Roedel
2018-12-03 17:23 ` Liu, Yi L
2018-12-04 6:13 ` Lu Baolu
2018-12-05 15:56 ` Joerg Roedel
2018-12-06 1:19 ` Lu Baolu
2018-11-28 3:54 ` [PATCH v5 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-11-28 3:54 ` [PATCH v5 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-11-28 3:54 ` [PATCH v5 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-11-28 3:54 ` [PATCH v5 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-11-28 3:54 ` [PATCH v5 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-11-28 3:54 ` [PATCH v5 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-11-28 3:54 ` [PATCH v5 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-11-28 3:54 ` [PATCH v5 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu
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