* [PATCH 0/2] ARM errata 814220 @ 2019-02-13 9:56 Benjamin Gaignard 2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Benjamin Gaignard @ 2019-02-13 9:56 UTC (permalink / raw) To: linux, arnd, alexandre.torgue Cc: linux-arm-kernel, linux-kernel, linux-stm32, Benjamin Gaignard Implement ARM errata 814220 for Cortex A7. This patch has been wroten by Jason Liu years ago but never send upstream. I have tried to contact the author on multiple email addresses but I haven't found any valid one... I have keep Jason's sign-off and just rebase the patch on to v5-rc6. Benjamin Gaignard (2): ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order. ARM: stm32: select ARM errata 814220 arch/arm/Kconfig | 10 ++++++++++ arch/arm/mach-stm32/Kconfig | 1 + arch/arm/mm/cache-v7.S | 3 +++ 3 files changed, 14 insertions(+) -- 2.15.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order. 2019-02-13 9:56 [PATCH 0/2] ARM errata 814220 Benjamin Gaignard @ 2019-02-13 9:56 ` Benjamin Gaignard 2019-02-13 18:27 ` Russell King - ARM Linux admin 2019-02-13 9:56 ` [PATCH 2/2] ARM: stm32: select ARM errata 814220 Benjamin Gaignard 2019-02-13 14:52 ` [PATCH 0/2] " Arnd Bergmann 2 siblings, 1 reply; 6+ messages in thread From: Benjamin Gaignard @ 2019-02-13 9:56 UTC (permalink / raw) To: linux, arnd, alexandre.torgue Cc: linux-arm-kernel, linux-kernel, linux-stm32, Benjamin Gaignard, Jason Liu Description: The v7 ARM states that all cache and branch predictor maintenance operations that do not specify an address execute, relative to each other, in program order. However, because of this erratum, an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation, this would cause the data corruption. This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. This patch is the SW workaround by adding a DSB before changing cache levels as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/mm/cache-v7.S | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 664e918e2624..6f608558e22a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152 default y select DMABOUNCE +config ARM_ERRATA_814220 + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" + depends on CPU_V7 + help + The v7 ARM states that all cache and branch predictor maintenance operations + that do not specify an address execute, relative to each other, in program order. + However, because of this erratum, an L2 set/way cache maintenance operation can + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. + endmenu menu "Kernel Features" diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 2149b47a0c5a..7ff7b4c197cc 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -163,6 +163,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ switch back to cache level 0 -- 2.15.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order. 2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard @ 2019-02-13 18:27 ` Russell King - ARM Linux admin 0 siblings, 0 replies; 6+ messages in thread From: Russell King - ARM Linux admin @ 2019-02-13 18:27 UTC (permalink / raw) To: Benjamin Gaignard Cc: arnd, alexandre.torgue, Jason Liu, linux-kernel, linux-arm-kernel, linux-stm32 On Wed, Feb 13, 2019 at 10:56:12AM +0100, Benjamin Gaignard wrote: > Description: > The v7 ARM states that all cache and branch predictor maintenance operations > that do not specify an address execute, relative to each other, in program > order. However, because of this erratum, an L2 set/way cache maintenance > operation can overtake an L1 set/way cache maintenance operation, this would > cause the data corruption. > > This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. > > This patch is the SW workaround by adding a DSB before changing cache levels as > the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. > > Signed-off-by: Jason Liu <r64343@freescale.com> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> > --- > arch/arm/Kconfig | 10 ++++++++++ > arch/arm/mm/cache-v7.S | 3 +++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 664e918e2624..6f608558e22a 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152 > default y > select DMABOUNCE > > +config ARM_ERRATA_814220 > + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" > + depends on CPU_V7 > + help > + The v7 ARM states that all cache and branch predictor maintenance operations > + that do not specify an address execute, relative to each other, in program order. > + However, because of this erratum, an L2 set/way cache maintenance operation can > + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the > + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. We generally try to keep help lines so that when edited on an 80 column display, they do not wrap. Please can you reformat the above to satisfy that please? (means breaking the lines after "maintenance" on the first line.) Thanks. > + > endmenu > > menu "Kernel Features" > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S > index 2149b47a0c5a..7ff7b4c197cc 100644 > --- a/arch/arm/mm/cache-v7.S > +++ b/arch/arm/mm/cache-v7.S > @@ -163,6 +163,9 @@ loop2: > skip: > add r10, r10, #2 @ increment cache number > cmp r3, r10 > +#ifdef CONFIG_ARM_ERRATA_814220 > + dsb > +#endif > bgt flush_levels > finished: > mov r10, #0 @ switch back to cache level 0 > -- > 2.15.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] ARM: stm32: select ARM errata 814220 2019-02-13 9:56 [PATCH 0/2] ARM errata 814220 Benjamin Gaignard 2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard @ 2019-02-13 9:56 ` Benjamin Gaignard 2019-02-13 14:52 ` [PATCH 0/2] " Arnd Bergmann 2 siblings, 0 replies; 6+ messages in thread From: Benjamin Gaignard @ 2019-02-13 9:56 UTC (permalink / raw) To: linux, arnd, alexandre.torgue Cc: linux-arm-kernel, linux-kernel, linux-stm32, Benjamin Gaignard Make sure that ARM errata 814220 is selected by STM32MP157 SoC Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> --- arch/arm/mach-stm32/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 713c068b953f..be2403fa3deb 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -46,6 +46,7 @@ if ARCH_MULTI_V7 config MACH_STM32MP157 bool "STMicroelectronics STM32MP157" + select ARM_ERRATA_814220 default y endif # ARMv7-A -- 2.15.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] ARM errata 814220 2019-02-13 9:56 [PATCH 0/2] ARM errata 814220 Benjamin Gaignard 2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard 2019-02-13 9:56 ` [PATCH 2/2] ARM: stm32: select ARM errata 814220 Benjamin Gaignard @ 2019-02-13 14:52 ` Arnd Bergmann 2019-02-15 16:30 ` Alexandre Torgue 2 siblings, 1 reply; 6+ messages in thread From: Arnd Bergmann @ 2019-02-13 14:52 UTC (permalink / raw) To: Benjamin Gaignard Cc: Russell King - ARM Linux, Alexandre Torgue, Linux ARM, Linux Kernel Mailing List, linux-stm32 On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard <benjamin.gaignard@linaro.org> wrote: > > Implement ARM errata 814220 for Cortex A7. > > This patch has been wroten by Jason Liu years ago but never send upstream. > I have tried to contact the author on multiple email addresses but I haven't > found any valid one... > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > Benjamin Gaignard (2): > ARM: errata 814220-B-Cache maintenance by set/way operations can > execute out of order. > ARM: stm32: select ARM errata 814220 > > arch/arm/Kconfig | 10 ++++++++++ > arch/arm/mach-stm32/Kconfig | 1 + > arch/arm/mm/cache-v7.S | 3 +++ > 3 files changed, 14 insertions(+) Looks good to me, Acked-by: Arnd Bergmann <arnd@arndb.de> It probably makes most sense to keep them as a series, either through the soc tree or Russell's patch tracker, so feel free to add it there, and have them both in the stm32 soc branch for arm-soc if Russell prefers. As we have a number of Cortex-A7 based platforms with all kinds of revisions, I wonder if we should also select the workaround for the others. I can probably figure out which SoC platforms are based on Cortex-A7, but I have no idea about the revisions, so that might mean we'd have to do it for all of them. According to the latest TRM I found, only revisions r0p0 through r0p5 exist, and the erraturm text lists r0p2 through r0p5, which may mean all products ever shipped in practice (the oldest public TRM from 2012 already describe r0p3). Arnd ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] ARM errata 814220 2019-02-13 14:52 ` [PATCH 0/2] " Arnd Bergmann @ 2019-02-15 16:30 ` Alexandre Torgue 0 siblings, 0 replies; 6+ messages in thread From: Alexandre Torgue @ 2019-02-15 16:30 UTC (permalink / raw) To: Arnd Bergmann, Benjamin Gaignard Cc: Russell King - ARM Linux, Linux ARM, Linux Kernel Mailing List, linux-stm32 On 2/13/19 3:52 PM, Arnd Bergmann wrote: > On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard > <benjamin.gaignard@linaro.org> wrote: >> >> Implement ARM errata 814220 for Cortex A7. >> >> This patch has been wroten by Jason Liu years ago but never send upstream. >> I have tried to contact the author on multiple email addresses but I haven't >> found any valid one... >> I have keep Jason's sign-off and just rebase the patch on to v5-rc6. >> >> Benjamin Gaignard (2): >> ARM: errata 814220-B-Cache maintenance by set/way operations can >> execute out of order. >> ARM: stm32: select ARM errata 814220 >> >> arch/arm/Kconfig | 10 ++++++++++ >> arch/arm/mach-stm32/Kconfig | 1 + >> arch/arm/mm/cache-v7.S | 3 +++ >> 3 files changed, 14 insertions(+) > > Looks good to me, > > Acked-by: Arnd Bergmann <arnd@arndb.de> > > It probably makes most sense to keep them as a series, either > through the soc tree or Russell's patch tracker, so feel free to add > it there, and have them both in the stm32 soc branch for arm-soc > if Russell prefers. Russel, what do you think about Arnd proposition? I could take both patches in my stm32 tree. It'll make part of future v5.2 pull request. Alex > > As we have a number of Cortex-A7 based platforms with all > kinds of revisions, I wonder if we should also select the workaround > for the others. I can probably figure out which SoC platforms > are based on Cortex-A7, but I have no idea about the revisions, > so that might mean we'd have to do it for all of them. According > to the latest TRM I found, only revisions r0p0 through r0p5 > exist, and the erraturm text lists r0p2 through r0p5, which may > mean all products ever shipped in practice (the oldest public > TRM from 2012 already describe r0p3). > > > > > Arnd > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-02-15 16:31 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-02-13 9:56 [PATCH 0/2] ARM errata 814220 Benjamin Gaignard 2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard 2019-02-13 18:27 ` Russell King - ARM Linux admin 2019-02-13 9:56 ` [PATCH 2/2] ARM: stm32: select ARM errata 814220 Benjamin Gaignard 2019-02-13 14:52 ` [PATCH 0/2] " Arnd Bergmann 2019-02-15 16:30 ` Alexandre Torgue
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