From: Borislav Petkov <bp@alien8.de>
To: Yash Shah <yash.shah@sifive.com>
Cc: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org,
palmer@sifive.com, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, aou@eecs.berkeley.edu, mchehab@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
Date: Tue, 12 Mar 2019 10:28:42 +0100 [thread overview]
Message-ID: <20190312092842.GC28589@zn.tnic> (raw)
In-Reply-To: <1552382461-13051-3-git-send-email-yash.shah@sifive.com>
On Tue, Mar 12, 2019 at 02:51:01PM +0530, Yash Shah wrote:
> Add driver for the SiFive L2 cache controller
> on the HiFive Unleashed board
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/Kconfig | 1 +
> drivers/edac/Kconfig | 7 +
> drivers/edac/Makefile | 1 +
> drivers/edac/sifive_edac-l2.c | 292 ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 301 insertions(+)
> create mode 100644 drivers/edac/sifive_edac-l2.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 515fc3c..fede4b6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -49,6 +49,7 @@ config RISCV
> select RISCV_TIMER
> select GENERIC_IRQ_MULTI_HANDLER
> select ARCH_HAS_PTE_SPECIAL
> + select EDAC_SUPPORT
>
> config MMU
> def_bool y
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index e286b5b..63ccdf1 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -440,6 +440,13 @@ config EDAC_ALTERA_SDMMC
> Support for error detection and correction on the
> Altera SDMMC FIFO Memory for Altera SoCs.
>
> +config EDAC_SIFIVE_L2
> + tristate "Sifive L2 Cache"
> + depends on RISCV
> + help
> + Support for error detection and correction on the SiFive L2
> + cache controller.
Please no EDAC drivers for a single functional unit with RAS
capabilities. Rather, a sifive_edac or riscv_edac driver which covers
the whole platform or even architecture and contains support for all the
RAS functionality there. See altera_edac, for example.
HTH.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
next prev parent reply other threads:[~2019-03-12 9:28 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-12 9:20 [PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed Yash Shah
2019-03-12 9:21 ` [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Yash Shah
2019-03-28 13:16 ` Rob Herring
2019-03-28 18:47 ` James Morse
2019-03-29 14:11 ` Rob Herring
2019-03-29 14:27 ` Borislav Petkov
2019-03-29 19:41 ` Rob Herring
2019-03-29 20:24 ` Borislav Petkov
2019-04-04 1:04 ` Rob Herring
2019-04-01 16:36 ` James Morse
2019-04-04 1:17 ` Rob Herring
2019-03-12 9:21 ` [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller Yash Shah
2019-03-12 9:28 ` Borislav Petkov [this message]
2019-03-25 0:16 ` Paul Walmsley
2019-03-25 6:54 ` Borislav Petkov
2019-03-25 21:18 ` Paul Walmsley
2019-03-25 21:47 ` Borislav Petkov
2019-03-12 16:31 ` Paul Walmsley
2019-03-12 16:32 ` [PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed Paul Walmsley
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