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From: Mark Brown <broonie@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: Mark Brown <broonie@kernel.org>,
	thierry.reding@gmail.com, jonathanh@nvidia.com, talho@nvidia.com,
	skomatineni@nvidia.com, broonie@kernel.org, robh+dt@kernel.org,
	mark.rutland@arm.com, kyarlagadda@nvidia.com,
	ldewangan@nvidia.com, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, linux-spi@vger.kernel.org
Subject: Applied "spi: tegra114: fix for unpacked mode transfers" to the spi tree
Date: Mon,  1 Apr 2019 09:54:40 +0100 (BST)	[thread overview]
Message-ID: <20190401085440.B8359440082@finisterre.ee.mobilebroadband> (raw)
In-Reply-To: <1553666207-11414-3-git-send-email-skomatineni@nvidia.com>

The patch

   spi: tegra114: fix for unpacked mode transfers

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From 1a89ac5b91895127f7c586ec5075c3753ca25501 Mon Sep 17 00:00:00 2001
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: Tue, 26 Mar 2019 22:56:24 -0700
Subject: [PATCH] spi: tegra114: fix for unpacked mode transfers

Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked
mode when transfer length is not a multiple of requested bits per word.

unpacked mode transfers fails when the transfer includes partial bytes in
the last word.

Total words to be written/read to/from FIFO is computed based on transfer
length and bits per word. Unpacked mode includes 0 padding bytes for partial
words to align with bits per word and these extra bytes are also accounted
for calculating bytes left to transfer in the current driver.

This causes extra bytes access of tx/rx buffers along with buffer index
position crossing actual length where remain_len becomes negative and due to
unsigned type, negative value is a 32 bit representation of signed value
and transferred bytes never meets the actual transfer length resulting in
transfer timeout and a hang.

This patch fixes this with proper computation of the actual bytes to fill in
FIFO during transmit and the actual bytes to read from FIFO during receive
ignoring 0 padded bytes.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-tegra114.c | 43 +++++++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 1435792944c4..876eb2acdef1 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -307,10 +307,16 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 				x |= (u32)(*tx_buf++) << (i * 8);
 			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 		}
+
+		tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 	} else {
+		unsigned int write_bytes;
 		max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 		written_words = max_n_32bit;
 		nbytes = written_words * tspi->bytes_per_word;
+		if (nbytes > t->len - tspi->cur_pos)
+			nbytes = t->len - tspi->cur_pos;
+		write_bytes = nbytes;
 		for (count = 0; count < max_n_32bit; count++) {
 			u32 x = 0;
 
@@ -319,8 +325,10 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 				x |= (u32)(*tx_buf++) << (i * 8);
 			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 		}
+
+		tspi->cur_tx_pos += write_bytes;
 	}
-	tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
+
 	return written_words;
 }
 
@@ -344,20 +352,27 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 			for (i = 0; len && (i < 4); i++, len--)
 				*rx_buf++ = (x >> i*8) & 0xFF;
 		}
-		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 		read_words += tspi->curr_dma_words;
+		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 	} else {
 		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
+		u8 bytes_per_word = tspi->bytes_per_word;
+		unsigned int read_bytes;
 
+		len = rx_full_count * bytes_per_word;
+		if (len > t->len - tspi->cur_pos)
+			len = t->len - tspi->cur_pos;
+		read_bytes = len;
 		for (count = 0; count < rx_full_count; count++) {
 			u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
 
-			for (i = 0; (i < tspi->bytes_per_word); i++)
+			for (i = 0; len && (i < bytes_per_word); i++, len--)
 				*rx_buf++ = (x >> (i*8)) & 0xFF;
 		}
-		tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
 		read_words += rx_full_count;
+		tspi->cur_rx_pos += read_bytes;
 	}
+
 	return read_words;
 }
 
@@ -372,12 +387,17 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 
 		memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
+		tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 	} else {
 		unsigned int i;
 		unsigned int count;
 		u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
+		unsigned int write_bytes;
 
+		if (consume > t->len - tspi->cur_pos)
+			consume = t->len - tspi->cur_pos;
+		write_bytes = consume;
 		for (count = 0; count < tspi->curr_dma_words; count++) {
 			u32 x = 0;
 
@@ -386,8 +406,9 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 				x |= (u32)(*tx_buf++) << (i * 8);
 			tspi->tx_dma_buf[count] = x;
 		}
+
+		tspi->cur_tx_pos += write_bytes;
 	}
-	tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 
 	/* Make the dma buffer to read by dma */
 	dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
@@ -405,20 +426,28 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 
 		memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
+		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 	} else {
 		unsigned int i;
 		unsigned int count;
 		unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
+		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
+		unsigned int read_bytes;
 
+		if (consume > t->len - tspi->cur_pos)
+			consume = t->len - tspi->cur_pos;
+		read_bytes = consume;
 		for (count = 0; count < tspi->curr_dma_words; count++) {
 			u32 x = tspi->rx_dma_buf[count] & rx_mask;
 
-			for (i = 0; (i < tspi->bytes_per_word); i++)
+			for (i = 0; consume && (i < tspi->bytes_per_word);
+							i++, consume--)
 				*rx_buf++ = (x >> (i*8)) & 0xFF;
 		}
+
+		tspi->cur_rx_pos += read_bytes;
 	}
-	tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 
 	/* Make the dma buffer to read by dma */
 	dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
-- 
2.20.1


  reply	other threads:[~2019-04-01  8:54 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-27  5:56 [PATCH V1 01/26] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 02/26] spi: tegra114: clear packed bit for unpacked mode Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: clear packed bit for unpacked mode" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 03/26] spi: tegra114: fix for unpacked mode transfers Sowjanya Komatineni
2019-04-01  8:54   ` Mark Brown [this message]
2019-03-27  5:56 ` [PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word Sowjanya Komatineni
2019-04-01  7:39   ` Mark Brown
2019-04-01 18:38     ` Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: use packed mode for 32 bits per word" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 05/26] spi: tegra114: use unpacked mode for below 4 byte transfers Sowjanya Komatineni
2019-04-01  8:26   ` Mark Brown
2019-03-27  5:56 ` [PATCH V1 06/26] spi: tegra114: terminate dma and reset on transfer timeout Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: terminate dma and reset on transfer timeout" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 07/26] spi: tegra114: flush fifos Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: flush fifos" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 08/26] spi: tegra114: configure dma burst size to fifo trig level Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout Sowjanya Komatineni
2019-04-01  7:39   ` Mark Brown
2019-03-27  5:56 ` [PATCH V1 10/26] spi: tegra114: avoid reset call in atomic context Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 11/26] spi: tegra114: reset controller on probe Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: reset controller on probe" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 12/26] spi: tegra114: add SPI_LSB_FIRST support Sowjanya Komatineni
2019-04-01  8:54   ` Applied "spi: tegra114: add SPI_LSB_FIRST support" to the spi tree Mark Brown
2019-03-27  5:56 ` [PATCH V1 13/26] spi: tegra114: add dual mode support Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 14/26] spi: tegra114: add 3 wire transfer " Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 15/26] spi: tegra114: set supported bits_per_word Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 16/26] spi: tegra114: set bus number based on id Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 17/26] spi: tegra114: add support for interrupt mask Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 18/26] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-04-01  7:48   ` Mark Brown
2019-04-01 18:40     ` Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 19/26] DT bindings: spi: add spi client device properties Sowjanya Komatineni
2019-04-01  7:37   ` Mark Brown
2019-04-01 17:59     ` Sowjanya Komatineni
2019-04-02  4:52       ` Mark Brown
2019-03-27  5:56 ` [PATCH V1 20/26] spi: tegra114: add support for tuning HW CS timing Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Sowjanya Komatineni
2019-03-31  6:42   ` Rob Herring
2019-04-02 20:27     ` Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 22/26] spi: tegra114: add support for tuning clock delay Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 23/26] spi: tegra114: add support for gpio based cs Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default Sowjanya Komatineni
2019-04-01  7:49   ` Mark Brown
2019-04-01 18:07     ` Sowjanya Komatineni
2019-04-02  4:52       ` Mark Brown
2019-03-27  5:56 ` [PATCH V1 25/26] spi: expand mode and mode_bits support Sowjanya Komatineni
2019-03-27  5:56 ` [PATCH V1 26/26] spi: tegra114: add support for LSBYTE_FIRST Sowjanya Komatineni

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