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From: Fenghua Yu <fenghua.yu@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, H Peter Anvin <hpa@zytor.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Ashok Raj <ashok.raj@intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Kalle Valo <kvalo@codeaurora.org>,
	Xiaoyao Li <xiaoyao.li@intel.com>,
	Michael Chan <michael.chan@broadcom.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
	linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [PATCH v6 01/20] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long
Date: Thu, 4 Apr 2019 08:54:23 -0700	[thread overview]
Message-ID: <20190404155422.GA177894@romley-ivt3.sc.intel.com> (raw)
In-Reply-To: <20190404143942.GD22539@zn.tnic>

On Thu, Apr 04, 2019 at 04:39:43PM +0200, Borislav Petkov wrote:
> On Wed, Apr 03, 2019 at 02:21:47PM -0700, Fenghua Yu wrote:
> > cpu_caps_cleared and cpu_caps_set may not be aligned to unsigned long.
> > Atomic operations (i.e. set_bit and clear_bit) on the bitmaps may access
> 
> Please end function names with parentheses.

Sure.

> 
> > two cache lines (a.k.a. split lock) and lock the bus to block all memory
> 
> not "lock the bus" but "cause the CPU to do a bus lock... "

Sure.

> 
> > accesses from other processors to ensure atomicity.
> > 
> > To avoid the overall performance degradation from the bus locking, align
> > the two variables to unsigned long.
> > 
> > Defining the variables as unsigned long may also fix the issue because
> > they are naturally aligned to unsigned long. But that needs additional
> > code changes. Adding __aligned(unsigned long) is a simpler fix.
> > 
> > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> > ---
> >  arch/x86/kernel/cpu/common.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> With the above nitpicks addressed:
> 
> Reviewed-by: Borislav Petkov <bp@suse.de>

Thank you for your review!

-Fenghua

  reply	other threads:[~2019-04-04 16:02 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03 21:21 [PATCH v6 00/20] x86/split_lock: Enable split locked accesses detection Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 01/20] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-04 14:39   ` Borislav Petkov
2019-04-04 15:54     ` Fenghua Yu [this message]
2019-04-03 21:21 ` [PATCH v6 02/20] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 03/20] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 04/20] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-04 14:44   ` David Laight
2019-04-04 16:24     ` David Laight
2019-04-04 16:35       ` Sean Christopherson
2019-04-04 16:52       ` Thomas Gleixner
2019-04-04 17:29         ` Paolo Bonzini
2019-04-04 18:11           ` Thomas Gleixner
2019-04-05  9:23         ` David Laight
2019-04-03 21:21 ` [PATCH v6 05/20] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 06/20] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 07/20] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 08/20] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 09/20] x86/split_lock: Define MSR_TEST_CTL register Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 10/20] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-04 17:31   ` Thomas Gleixner
2019-04-04 22:49     ` Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 11/20] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-05 12:00   ` Thomas Gleixner
2019-04-09  6:03     ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 12/20] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-04 14:44   ` Sean Christopherson
2019-04-08  8:54     ` Xiaoyao Li
2019-04-05 12:30   ` Thomas Gleixner
2019-04-08  9:54     ` Xiaoyao Li
2019-04-08 17:48       ` Sean Christopherson
2019-04-10  5:03         ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 13/20] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-04 18:07   ` Thomas Gleixner
2019-04-04 18:14     ` Thomas Gleixner
2019-04-04 19:23     ` Fenghua Yu
2019-04-04 19:44       ` Thomas Gleixner
2019-04-10  0:02     ` Fenghua Yu
2019-04-10  6:31       ` Thomas Gleixner
2019-04-10 12:35         ` Fenghua Yu
2019-04-10  8:50       ` David Laight
2019-04-03 21:22 ` [PATCH v6 14/20] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-04 19:11   ` Thomas Gleixner
2019-04-03 21:22 ` [PATCH v6 15/20] x86/split_lock: Document the new sysfs file for split lock detection Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 16/20] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 17/20] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 18/20] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 19/20] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 20/20] x86/clearcpuid: Change document for kernel option clearcpuid Fenghua Yu

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