From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
H Peter Anvin <hpa@zytor.com>,
Dave Hansen <dave.hansen@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Ashok Raj <ashok.raj@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Kalle Valo <kvalo@codeaurora.org>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Michael Chan <michael.chan@broadcom.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
kvm@vger.kernel.org
Subject: Re: [PATCH v6 13/20] x86/split_lock: Enable split lock detection by default
Date: Thu, 4 Apr 2019 20:07:57 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1904041932500.1802@nanos.tec.linutronix.de> (raw)
In-Reply-To: <1554326526-172295-14-git-send-email-fenghua.yu@intel.com>
On Wed, 3 Apr 2019, Fenghua Yu wrote:
> A split locked access locks bus and degrades overall memory access
> performance. When split lock detection feature is enumerated, enable
> the feature by default to find any split lock issue and then fix
> the issue.
Enabling the feature allows to find the issues, but does not automagically
fix them. Come on.
> +#define DISABLE_SPLIT_LOCK_DETECT 0
> +#define ENABLE_SPLIT_LOCK_DETECT 1
If those defines have a value at all, please start with the facility not
with functionality, i.e. AC_SPLIT_LOCK_ENABLE....
> +
> +static DEFINE_MUTEX(split_lock_detect_mutex);
> +static int split_lock_detect_val;
detect_val? What value is that? Its supposed to hold those magic defines
above. So something like
static unsigned int ac_split_lock_enable;
> /*
> * Just in case our CPU detection goes bad, or you have a weird system,
> * allow a way to override the automatic disabling of MPX.
> @@ -161,10 +167,45 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
> return false;
> }
>
> +static u32 new_sp_test_ctl_val(u32 test_ctl_val)
> +{
> + /* Change the split lock setting. */
> + if (READ_ONCE(split_lock_detect_val) == DISABLE_SPLIT_LOCK_DETECT)
That READ_ONCE() is required because?
> + test_ctl_val &= ~TEST_CTL_ENABLE_SPLIT_LOCK_DETECT;
> + else
> + test_ctl_val |= TEST_CTL_ENABLE_SPLIT_LOCK_DETECT;
> +
> + return test_ctl_val;
> +}
Aside of that do we really need a misnomed function which replaces the
simple inline code at the call site:
rdmsr(l, h)
l &= ~TEST_CTL_ENABLE_SPLIT_LOCK_DETECT;
l |= ac_split_lock_enable << TEST_CTL_ENABLE_SPLIT_LOCK_DETECT_SHIFT;
wrmrs(...)
or the even more simple
if (ac_split_lock_enable)
msr_set_bit(...)
else
msr_clear_nit(...)
Hmm?
> +
> +static inline void show_split_lock_detection_info(void)
> +{
> + if (READ_ONCE(split_lock_detect_val))
That READ_ONCE() is required because?
> + pr_info_once("x86/split_lock: split lock detection enabled\n");
> + else
> + pr_info_once("x86/split_lock: split lock detection disabled\n");
pr_fmt exists for a reason and having 'split lock' repeated several times
in the same line is not making it more readable.
> +}
> +
> +static void init_split_lock_detect(struct cpuinfo_x86 *c)
> +{
> + if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT)) {
> + u32 l, h;
> +
> + mutex_lock(&split_lock_detect_mutex);
> + rdmsr(MSR_TEST_CTL, l, h);
> + l = new_sp_test_ctl_val(l);
> + wrmsr(MSR_TEST_CTL, l, h);
> + show_split_lock_detection_info();
> + mutex_unlock(&split_lock_detect_mutex);
> + }
> +}
> +
> static void early_init_intel(struct cpuinfo_x86 *c)
> {
> u64 misc_enable;
>
> + init_split_lock_detect(c);
so we have in early boot:
early_cpu_init()
early_identify_cpu()
this_cpu->c_early_init(c)
early_init_intel() {
init_split_lock_detect();
}
....
cpu_set_core_cap_bits(c)
set(FEATURE_SPLIT_LOCK)
I don't have to understand how init_split_lock_detect() will magically see
the feature bit which gets set afterwards, right?
> +
> /* Unmask CPUID levels if masked: */
> if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
> if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
> @@ -1032,6 +1073,7 @@ cpu_dev_register(intel_cpu_dev);
> static void __init set_split_lock_detect(void)
> {
> setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
> + split_lock_detect_val = 1;
Oh well. You add defines on top of the file and then you don't use them.
Thanks,
tglx
next prev parent reply other threads:[~2019-04-04 18:08 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-03 21:21 [PATCH v6 00/20] x86/split_lock: Enable split locked accesses detection Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 01/20] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-04 14:39 ` Borislav Petkov
2019-04-04 15:54 ` Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 02/20] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 03/20] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 04/20] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-04 14:44 ` David Laight
2019-04-04 16:24 ` David Laight
2019-04-04 16:35 ` Sean Christopherson
2019-04-04 16:52 ` Thomas Gleixner
2019-04-04 17:29 ` Paolo Bonzini
2019-04-04 18:11 ` Thomas Gleixner
2019-04-05 9:23 ` David Laight
2019-04-03 21:21 ` [PATCH v6 05/20] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 06/20] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 07/20] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 08/20] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 09/20] x86/split_lock: Define MSR_TEST_CTL register Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 10/20] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-04 17:31 ` Thomas Gleixner
2019-04-04 22:49 ` Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 11/20] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-05 12:00 ` Thomas Gleixner
2019-04-09 6:03 ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 12/20] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-04 14:44 ` Sean Christopherson
2019-04-08 8:54 ` Xiaoyao Li
2019-04-05 12:30 ` Thomas Gleixner
2019-04-08 9:54 ` Xiaoyao Li
2019-04-08 17:48 ` Sean Christopherson
2019-04-10 5:03 ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 13/20] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-04 18:07 ` Thomas Gleixner [this message]
2019-04-04 18:14 ` Thomas Gleixner
2019-04-04 19:23 ` Fenghua Yu
2019-04-04 19:44 ` Thomas Gleixner
2019-04-10 0:02 ` Fenghua Yu
2019-04-10 6:31 ` Thomas Gleixner
2019-04-10 12:35 ` Fenghua Yu
2019-04-10 8:50 ` David Laight
2019-04-03 21:22 ` [PATCH v6 14/20] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-04 19:11 ` Thomas Gleixner
2019-04-03 21:22 ` [PATCH v6 15/20] x86/split_lock: Document the new sysfs file for split lock detection Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 16/20] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 17/20] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 18/20] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 19/20] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 20/20] x86/clearcpuid: Change document for kernel option clearcpuid Fenghua Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.21.1904041932500.1802@nanos.tec.linutronix.de \
--to=tglx@linutronix.de \
--cc=ashok.raj@intel.com \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=fenghua.yu@intel.com \
--cc=hpa@zytor.com \
--cc=kvalo@codeaurora.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-wireless@vger.kernel.org \
--cc=michael.chan@broadcom.com \
--cc=mingo@redhat.com \
--cc=netdev@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=ravi.v.shankar@intel.com \
--cc=x86@kernel.org \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).