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From: Thomas Gleixner <tglx@linutronix.de>
To: David Laight <David.Laight@ACULAB.COM>
Cc: 'Fenghua Yu' <fenghua.yu@intel.com>,
	'Ingo Molnar' <mingo@redhat.com>,
	'Borislav Petkov' <bp@alien8.de>, 'H Peter Anvin' <hpa@zytor.com>,
	'Dave Hansen' <dave.hansen@intel.com>,
	'Paolo Bonzini' <pbonzini@redhat.com>,
	'Ashok Raj' <ashok.raj@intel.com>,
	'Peter Zijlstra' <peterz@infradead.org>,
	'Kalle Valo' <kvalo@codeaurora.org>,
	'Xiaoyao Li ' <xiaoyao.li@intel.com>,
	'Michael Chan' <michael.chan@broadcom.com>,
	'Ravi V Shankar' <ravi.v.shankar@intel.com>,
	'linux-kernel' <linux-kernel@vger.kernel.org>,
	'x86' <x86@kernel.org>,
	"'linux-wireless@vger.kernel.org'"
	<linux-wireless@vger.kernel.org>,
	"'netdev@vger.kernel.org'" <netdev@vger.kernel.org>,
	"'kvm@vger.kernel.org'" <kvm@vger.kernel.org>
Subject: RE: [PATCH v6 04/20] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access
Date: Thu, 4 Apr 2019 18:52:17 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1904041833480.1802@nanos.tec.linutronix.de> (raw)
In-Reply-To: <c0d43317cce34389ac4a1e91e97d909b@AcuMS.aculab.com>

[-- Attachment #1: Type: text/plain, Size: 1261 bytes --]

On Thu, 4 Apr 2019, David Laight wrote:
> From: David Laight Sent: 04 April 2019 15:45
> > From: Fenghua Yu Sent: 03 April 2019 22:22
> > That is not true.
> > The BTS/BTR instructions access the memory word that contains the
> > expected bit.
> > The 'operand size' only affects the size of the register use for the
> > bit offset.
> > If the 'operand size' is 16 bits wide (+/- 32k bit offset) the cpu might
> > do an aligned 16bit memory access, otherwise (32 or 64bit bit offset) it
> > might do an aligned 32 bit access.
> > It should never do an 64bit access and never a misaligned one (even if
> > the base address is misaligned).
> 
> Hmmm... I may have misread things slightly.
> The accessed address is 'Effective Address + (4 ∗ (BitOffset DIV 32))'.
> However nothing suggests that it ever does 64bit accesses.
>
> If it does do 64bit accesses when the operand size is 64 bits then the
> asm stubs ought to be changed to only specify 32bit operand size.

bitops operate on unsigned long arrays, so the RMW on the affected array
member has to be atomic vs. other RMW operations on the same array
member. If we make the bitops 32bit wide on x86/64 we break that.

So selecting 64bit access (REX.W prefix) is correct and has to stay.

Thanks,

	tglx


  parent reply	other threads:[~2019-04-04 16:52 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03 21:21 [PATCH v6 00/20] x86/split_lock: Enable split locked accesses detection Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 01/20] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-04-04 14:39   ` Borislav Petkov
2019-04-04 15:54     ` Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 02/20] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 03/20] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 04/20] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-04-04 14:44   ` David Laight
2019-04-04 16:24     ` David Laight
2019-04-04 16:35       ` Sean Christopherson
2019-04-04 16:52       ` Thomas Gleixner [this message]
2019-04-04 17:29         ` Paolo Bonzini
2019-04-04 18:11           ` Thomas Gleixner
2019-04-05  9:23         ` David Laight
2019-04-03 21:21 ` [PATCH v6 05/20] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 06/20] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 07/20] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 08/20] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 09/20] x86/split_lock: Define MSR_TEST_CTL register Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 10/20] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-04-04 17:31   ` Thomas Gleixner
2019-04-04 22:49     ` Fenghua Yu
2019-04-03 21:21 ` [PATCH v6 11/20] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-04-05 12:00   ` Thomas Gleixner
2019-04-09  6:03     ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 12/20] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-04-04 14:44   ` Sean Christopherson
2019-04-08  8:54     ` Xiaoyao Li
2019-04-05 12:30   ` Thomas Gleixner
2019-04-08  9:54     ` Xiaoyao Li
2019-04-08 17:48       ` Sean Christopherson
2019-04-10  5:03         ` Xiaoyao Li
2019-04-03 21:21 ` [PATCH v6 13/20] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-04-04 18:07   ` Thomas Gleixner
2019-04-04 18:14     ` Thomas Gleixner
2019-04-04 19:23     ` Fenghua Yu
2019-04-04 19:44       ` Thomas Gleixner
2019-04-10  0:02     ` Fenghua Yu
2019-04-10  6:31       ` Thomas Gleixner
2019-04-10 12:35         ` Fenghua Yu
2019-04-10  8:50       ` David Laight
2019-04-03 21:22 ` [PATCH v6 14/20] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-04-04 19:11   ` Thomas Gleixner
2019-04-03 21:22 ` [PATCH v6 15/20] x86/split_lock: Document the new sysfs file for split lock detection Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 16/20] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 17/20] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 18/20] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 19/20] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-04-03 21:22 ` [PATCH v6 20/20] x86/clearcpuid: Change document for kernel option clearcpuid Fenghua Yu

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