[PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver

[PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver

[Lukasz Luba]

Hi all,

This is v8 of the patch set which adds support of Dynamic Memory Controller
for Exynos5422 SoC.
The driver supports Dynamic Voltage and Frequency Scaling
for the DMC and DRAM. It also provides needed timings for different
speed operations of the DRAM memory.
There is also new generic code in of_memory and headers which allows to parse
LPDDR3 memories defined in device-tree.

The patch set has been cut to land mainline quickly and the dependency
on PPMU patches are removed. It implies that the debugging code which was
presenting details about traffic on the AXI slots has been removed.
It will be added when this driver got mainline and the PPMU code got mainline.
Also DT dependency of PPMU header has been removed.

changes:
v8:
- removed chipID dependency, as Krzysztof suggested and drop the whole checking
  code in the driver (which also Marek suggested offline) (it might be needed
  in future when other configuration would be supported). It also avoids
  a misunderstandings and simplifies the documentation.
- reordered clock IDs in 1st patch to keep the old IDs and add the new clocks
  at the end as Chanwoo suggested (added also his ACK there)
- in patch 6 (dt-bindings) added explicit clocks and names in the right order
  needed for the driver
- added proper address for the memory node in the documentation and in the DT
  (lpddr3-timings@0 -> @80000000)
- fixed wrong reg offset for pause feature
- removed debug code which shows AXI slots traffic and removed DT ppmu events
- in the driver code usage of 'dev', 'pdev->dev' has been aligned
- manipulating clocks has been aligned as Krzysztof suggested, now it enables
  only two clocks (and disables) and enables/disables the 'bypass' clocks
  on demand
- added comments in the documentation why there is a need of clock registers
  to be accessed via syscon regmap
- added proper link to Documentation/devicetree/bindings/ddr/lpddr3.txt
  in dt-bindings for memory controller doc
- removed unneeded prints when there was a deferred probe or during remove
- added 'syscon' also to exynos5420-clock node as Krzysztof suggested
- from 2nd patch removed blank line and added Acked-by: Chanwoo Choi
- collecting ACKs, which makes the clock related 3 patches
  ready to be merged (4 ACKs),
- patches 4,5 got 'Reviewed-by' from Rob
- it is now based on v5.2-rc3 tag
v7 [2]:
- added using regmap in chipid registers and clock registers
- in DT added "syscon" to compatible field in clock and chipid
- added two addition clocks in clocks definition file which were there
  in first implementation but now are grouped and commented properly
  (CLK_DOUT_PCLK_DREX0, CLK_DOUT_PCLK_DREX1)
- the BPLL ratio table now is set for Exynos 5422 and 5800 and not for 5420
- in DMC driver, changed code macro which generates functions for setup events
  into normal three functions as Krzysztof suggested
- moved 'clock_prepare_enable()' calls into the same function where 'disable'
  were called
- changed 'timing_reg' static variables into static const
- in DMC driver: the proper device_node *np_ddr is now put correctly
- in DMC driver: removed code related to counters_enabled
- mapped only 0x100 from DREX registers
- in DT memory node there is now 'reg' as Rob suggested instead of 'max-freq'
- in Documentation/devicetree/bindings/lpddr2 renamed into 'ddr' and the lpdd3*
  files landed there.
- cleaned the commit subject and message as Rob suggested for the patch 4/10 in v6
- added doxygen comments to exported functions in of_memory file
- cleaned minor issues like: missing space, 2 empty lines, in the doc JESD209-2 ->
  JESD209-3C, removed 'status = "okay"' from the doc file, etc
- based on v5.1 (+ PPMU patches from [1])
v6:
- driver code has been converted to use generic code which parses DT memory
  definition in drivers/memory/of_memory.c
- extended of_memory by LPDDR3 support (there was LPDDR2 made by TI)
- extended jedec_lpddr.h by the needed structures for LPDDR3 (AC timings)
- driver file moved to proper directory, where other memory controllers
  live, which is in this case drivers/memory/samsung/
- driver code now uses regmap_{read|write} to access registers for pausing
  and changing timings set, as suggested by Chanwoo
- DT contains simple definition of memory device, similar to LPDDR2 made by TI
- driver code generates the needed timings for registered OPPs, based on
  memory description in DT
- patch 1 contains Rob's ACK,
- simplified memory bandwidth calculation
- added debug information files with timings, raw counters and statistics
- updated dt-bindings files accordingly
- based on v5.1-rc5 (+ PPMU patches from [1])
v5:
- removed unneeded wrapper functions i.e. for regulator_set_voltage
- removed unused defines
- removed direct access to clock register base and used CCF for
  pause and timing set usage
- switched to OPP comming from DT according to Chanowoo's comments
- switched to timings comming from DT, added parsing function
- extended dt-binding with description of OPPs and timings
- according to Rob Herring comment, moved dt-binding file before driver code
  in the patch set.
- rebased on top of v5.0
v4:
- removed unneeded DPLL and G3D clocks IDs
- changed names of parent clocks for mout_mx_mspll_ccore_phy_p
  and added one more parent: mout_sclk_epll
- removed 933Mhz and 138MHz from the BPLL ratio table
v3:
- in DTS align to proper indent the clocks and clock-names entries
v2:
- changed file name exynos5-dmc.c -> exynos5422-dmc.c
  and related entries in other files
- changed dt-binding file name
- changed config entry to CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ
- removed sysfs and print info messages (print only one line)
- removed function exynos5_read_chip_info and compact code
- changed dt-binding patch and move it up in the patch set
- new entries in MAINTAINERS are added with the driver c code
- clean-up in DTS file: renamed nodes to 'ppmu' and 'memory-controller',
  entries moved to suggested location (before nocp nodes or after),
  moved according to alfabetical order, compacted clocks names with right indent.

Regards,
Lukasz Luba

[1] https://lkml.org/lkml/2019/4/19/158
[2] https://lkml.org/lkml/2019/5/6/829

Lukasz Luba (13):
  clk: samsung: add needed IDs for DMC clocks in Exynos5420
  clk: samsung: add new clocks for DMC for Exynos5422 SoC
  clk: samsung: add BPLL rate table for Exynos 5422 SoC
  dt-bindings: ddr: rename lpddr2 directory
  dt-bindings: ddr: add LPDDR3 memories
  drivers: memory: extend of_memory by LPDDR3 support
  dt-bindings: memory-controllers: add Exynos5422 DMC device description
  drivers: memory: add DMC driver for Exynos5422
  drivers: devfreq: events: add Exynos PPMU new events
  ARM: dts: exynos: add chipid label and syscon compatible
  ARM: dts: exynos: add syscon to clock compatible
  ARM: dts: exynos: add DMC device for exynos5422
  ARM: exynos_defconfig: enable DMC driver

 .../{lpddr2 => ddr}/lpddr2-timings.txt        |    0
 .../bindings/{lpddr2 => ddr}/lpddr2.txt       |    2 +-
 .../bindings/ddr/lpddr3-timings.txt           |   58 +
 .../devicetree/bindings/ddr/lpddr3.txt        |   97 ++
 .../memory-controllers/exynos5422-dmc.txt     |   84 ++
 MAINTAINERS                                   |    8 +
 arch/arm/boot/dts/exynos5.dtsi                |    4 +-
 arch/arm/boot/dts/exynos5420.dtsi             |   81 +-
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  116 ++
 arch/arm/boot/dts/exynos5800.dtsi             |    2 +-
 arch/arm/configs/exynos_defconfig             |    1 +
 drivers/clk/samsung/clk-exynos5420.c          |   74 +-
 drivers/devfreq/event/exynos-ppmu.c           |    6 +
 drivers/memory/of_memory.c                    |  154 ++
 drivers/memory/of_memory.h                    |   18 +
 drivers/memory/samsung/Kconfig                |   17 +
 drivers/memory/samsung/Makefile               |    1 +
 drivers/memory/samsung/exynos5422-dmc.c       | 1265 +++++++++++++++++
 include/dt-bindings/clock/exynos5420.h        |   18 +-
 include/memory/jedec_ddr.h                    |   62 +
 20 files changed, 2057 insertions(+), 11 deletions(-)
 rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%)
 rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%)
 create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
 create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
 create mode 100644 drivers/memory/samsung/exynos5422-dmc.c

-- 
2.17.1

[PATCH v8 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420

[Lukasz Luba]

Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469943f1..02d5ac469a3d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
 #define CLK_MAU_EPLL		159
 #define CLK_SCLK_HSIC_12M	160
 #define CLK_SCLK_MPHY_IXTAL24	161
+#define CLK_SCLK_BPLL		162
 
 /* gate clocks */
 #define CLK_UART0		257
@@ -195,6 +196,16 @@
 #define CLK_ACLK432_CAM		518
 #define CLK_ACLK_FL1550_CAM	519
 #define CLK_ACLK550_CAM		520
+#define CLK_CLKM_PHY0		521
+#define CLK_CLKM_PHY1		522
+#define CLK_ACLK_PPMU_DREX0_0	523
+#define CLK_ACLK_PPMU_DREX0_1	524
+#define CLK_ACLK_PPMU_DREX1_0	525
+#define CLK_ACLK_PPMU_DREX1_1	526
+#define CLK_PCLK_PPMU_DREX0_0	527
+#define CLK_PCLK_PPMU_DREX0_1	528
+#define CLK_PCLK_PPMU_DREX1_0	529
+#define CLK_PCLK_PPMU_DREX1_1	530
 
 /* mux clocks */
 #define CLK_MOUT_HDMI		640
@@ -217,6 +228,8 @@
 #define CLK_MOUT_EPLL		657
 #define CLK_MOUT_MAU_EPLL	658
 #define CLK_MOUT_USER_MAU_EPLL	659
+#define CLK_MOUT_SCLK_SPLL	660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
@@ -248,8 +261,11 @@
 #define CLK_DOUT_CCLK_DREX0	794
 #define CLK_DOUT_CLK2X_PHY0	795
 #define CLK_DOUT_PCLK_CORE_MEM	796
+#define CLK_FF_DOUT_SPLL2	797
+#define CLK_DOUT_PCLK_DREX0	798
+#define CLK_DOUT_PCLK_DREX1	799
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		797
+#define CLK_NR_CLKS		800
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
-- 
2.17.1

Re: [PATCH v8 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Define new IDs for clocks used by Dynamic Memory Controller in
> Exynos5422 SoC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v8 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC

[Lukasz Luba]

This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 57 ++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34cce3c5898f..eecbfcc6b3cf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -134,6 +134,8 @@
 #define SRC_CDREX		0x20200
 #define DIV_CDREX0		0x20500
 #define DIV_CDREX1		0x20504
+#define GATE_BUS_CDREX0		0x20700
+#define GATE_BUS_CDREX1		0x20704
 #define KPLL_LOCK		0x28000
 #define KPLL_CON0		0x28100
 #define SRC_KFC			0x28200
@@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
 	DIV_CDREX1,
 	SRC_KFC,
 	DIV_KFC0,
+	GATE_BUS_CDREX0,
+	GATE_BUS_CDREX1,
 };
 
 static const unsigned long exynos5800_clk_regs[] __initconst = {
@@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p)	= { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 PNAME(mout_group14_5800_p)	= { "dout_aclk550_cam", "dout_sclk_sw" };
 PNAME(mout_group15_5800_p)	= { "dout_osc_div", "mout_sw_aclk550_cam" };
 PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
+PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
+					"mout_sclk_mpll", "ff_dout_spll2",
+					"mout_sclk_spll", "mout_sclk_epll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock
@@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock
 static const struct samsung_fixed_factor_clock
 		exynos5800_fixed_factor_clks[] __initconst = {
 	FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
-	FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
+	FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 };
 
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
@@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 	MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 
+	MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
+		mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
+
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
-			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
+			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
 	MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
 			SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
-	MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
+	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 
 	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
@@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 
 	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
-	MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 			"mout_aclk400_disp1", DIV_TOP2, 4, 3),
 
 	/* CDREX Block */
+	/*
+	 * The three clocks below are controlled using the same register and
+	 * bits. They are put into one because there is a need of
+	 * synchronization between the BUS and DREXs (two external memory
+	 * interfaces).
+	 * They are put here to show this HW assumption and for clock
+	 * information summary completeness.
+	 */
 	DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
 			DIV_CDREX0, 28, 3),
+	DIV(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
+			DIV_CDREX0, 28, 3),
+	DIV(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
+			DIV_CDREX0, 28, 3),
+
 	DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
 			DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
 	DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
@@ -1170,6 +1193,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
 
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+
+	/* CDREX */
+	GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
+			GATE_BUS_CDREX0, 0, 0, 0),
+	GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
+			GATE_BUS_CDREX0, 1, 0, 0),
+	GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
+			SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
 };
 
 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
-- 
2.17.1

Re: [PATCH v8 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> This patch provides support for clocks needed for Dynamic Memory Controller
> in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
> GATE entries.
>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 57 ++++++++++++++++++++++++++--
>  1 file changed, 53 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 34cce3c5898f..eecbfcc6b3cf 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -134,6 +134,8 @@
>  #define SRC_CDREX              0x20200
>  #define DIV_CDREX0             0x20500
>  #define DIV_CDREX1             0x20504
> +#define GATE_BUS_CDREX0                0x20700
> +#define GATE_BUS_CDREX1                0x20704
>  #define KPLL_LOCK              0x28000
>  #define KPLL_CON0              0x28100
>  #define SRC_KFC                        0x28200
> @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
>         DIV_CDREX1,
>         SRC_KFC,
>         DIV_KFC0,
> +       GATE_BUS_CDREX0,
> +       GATE_BUS_CDREX1,
>  };
>
>  static const unsigned long exynos5800_clk_regs[] __initconst = {
> @@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p)  = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
>  PNAME(mout_group14_5800_p)     = { "dout_aclk550_cam", "dout_sclk_sw" };
>  PNAME(mout_group15_5800_p)     = { "dout_osc_div", "mout_sw_aclk550_cam" };
>  PNAME(mout_group16_5800_p)     = { "dout_osc_div", "mout_mau_epll_clk" };
> +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
> +                                       "mout_sclk_mpll", "ff_dout_spll2",
> +                                       "mout_sclk_spll", "mout_sclk_epll"};
>
>  /* fixed rate clocks generated outside the soc */
>  static struct samsung_fixed_rate_clock
> @@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock
>  static const struct samsung_fixed_factor_clock
>                 exynos5800_fixed_factor_clks[] __initconst = {
>         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
> -       FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
> +       FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
>  };
>
>  static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> @@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
>         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
>
> +       MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
> +               mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
> +
>         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
> -                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
> +                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
>         MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
>                         SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
> -       MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
> +       MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>
>         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
> @@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>
>         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
>         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
> -       MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
> +       MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
>         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
>         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
>         MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
> @@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
>                         "mout_aclk400_disp1", DIV_TOP2, 4, 3),
>
>         /* CDREX Block */
> +       /*
> +        * The three clocks below are controlled using the same register and
> +        * bits. They are put into one because there is a need of
> +        * synchronization between the BUS and DREXs (two external memory
> +        * interfaces).
> +        * They are put here to show this HW assumption and for clock
> +        * information summary completeness.
> +        */
>         DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
>                         DIV_CDREX0, 28, 3),
> +       DIV(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
> +                       DIV_CDREX0, 28, 3),
> +       DIV(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
> +                       DIV_CDREX0, 28, 3),

Offline discussion with Marek and Sylwester suggested to add NOCACHE
for the two clocks using the same bits. Otherwise I am fine:

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH v8 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC

[Lukasz Luba]

Hi Krzysztof,

On 6/6/19 10:34 AM, Krzysztof Kozlowski wrote:
> On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> This patch provides support for clocks needed for Dynamic Memory Controller
>> in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
>> GATE entries.
>>
>> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 57 ++++++++++++++++++++++++++--
>>   1 file changed, 53 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 34cce3c5898f..eecbfcc6b3cf 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -134,6 +134,8 @@
>>   #define SRC_CDREX              0x20200
>>   #define DIV_CDREX0             0x20500
>>   #define DIV_CDREX1             0x20504
>> +#define GATE_BUS_CDREX0                0x20700
>> +#define GATE_BUS_CDREX1                0x20704
>>   #define KPLL_LOCK              0x28000
>>   #define KPLL_CON0              0x28100
>>   #define SRC_KFC                        0x28200
>> @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
>>          DIV_CDREX1,
>>          SRC_KFC,
>>          DIV_KFC0,
>> +       GATE_BUS_CDREX0,
>> +       GATE_BUS_CDREX1,
>>   };
>>
>>   static const unsigned long exynos5800_clk_regs[] __initconst = {
>> @@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p)  = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
>>   PNAME(mout_group14_5800_p)     = { "dout_aclk550_cam", "dout_sclk_sw" };
>>   PNAME(mout_group15_5800_p)     = { "dout_osc_div", "mout_sw_aclk550_cam" };
>>   PNAME(mout_group16_5800_p)     = { "dout_osc_div", "mout_mau_epll_clk" };
>> +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
>> +                                       "mout_sclk_mpll", "ff_dout_spll2",
>> +                                       "mout_sclk_spll", "mout_sclk_epll"};
>>
>>   /* fixed rate clocks generated outside the soc */
>>   static struct samsung_fixed_rate_clock
>> @@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock
>>   static const struct samsung_fixed_factor_clock
>>                  exynos5800_fixed_factor_clks[] __initconst = {
>>          FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
>> -       FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
>> +       FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
>>   };
>>
>>   static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>> @@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>          MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
>>          MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
>>
>> +       MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
>> +               mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
>> +
>>          MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
>> -                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
>> +                       mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
>>          MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
>>                          SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
>> -       MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>> +       MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>>          MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>>
>>          MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
>> @@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>
>>          MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
>>          MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
>> -       MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
>> +       MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
>>          MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
>>          MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
>>          MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
>> @@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
>>                          "mout_aclk400_disp1", DIV_TOP2, 4, 3),
>>
>>          /* CDREX Block */
>> +       /*
>> +        * The three clocks below are controlled using the same register and
>> +        * bits. They are put into one because there is a need of
>> +        * synchronization between the BUS and DREXs (two external memory
>> +        * interfaces).
>> +        * They are put here to show this HW assumption and for clock
>> +        * information summary completeness.
>> +        */
>>          DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
>>                          DIV_CDREX0, 28, 3),
>> +       DIV(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
>> +                       DIV_CDREX0, 28, 3),
>> +       DIV(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
>> +                       DIV_CDREX0, 28, 3),
> 
> Offline discussion with Marek and Sylwester suggested to add NOCACHE
> for the two clocks using the same bits. Otherwise I am fine:
Indeed, I have changed it and run some tests of these three clocks with:
-----------8<-------------------------
DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
	DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
	DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
	DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
--------------->8---------------------
> 
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Thank you for the review and ACK.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

Re: [PATCH v8 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC

[Lukasz Luba]

From 9a7532004606875744eb67ad2ce17197ba2fe61e Mon Sep 17 00:00:00 2001
From: Lukasz Luba <l.luba@partner.samsung.com>
Date: Tue, 15 Jan 2019 17:12:16 +0100
Subject: [PATCH 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC

This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
Regarding the discussions of clocks mapped to the same registers,
this is a fix which adds the needed flag 'NOCACHE'.
It also has the ACK from Krzysztof.

Regards,
Lukasz

 drivers/clk/samsung/clk-exynos5420.c | 61 +++++++++++++++++++++++++---
 1 file changed, 55 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34cce3c5898f..514e16310227 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -134,6 +134,8 @@
 #define SRC_CDREX		0x20200
 #define DIV_CDREX0		0x20500
 #define DIV_CDREX1		0x20504
+#define GATE_BUS_CDREX0		0x20700
+#define GATE_BUS_CDREX1		0x20704
 #define KPLL_LOCK		0x28000
 #define KPLL_CON0		0x28100
 #define SRC_KFC			0x28200
@@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
 	DIV_CDREX1,
 	SRC_KFC,
 	DIV_KFC0,
+	GATE_BUS_CDREX0,
+	GATE_BUS_CDREX1,
 };
 
 static const unsigned long exynos5800_clk_regs[] __initconst = {
@@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p)	= { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 PNAME(mout_group14_5800_p)	= { "dout_aclk550_cam", "dout_sclk_sw" };
 PNAME(mout_group15_5800_p)	= { "dout_osc_div", "mout_sw_aclk550_cam" };
 PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
+PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
+					"mout_sclk_mpll", "ff_dout_spll2",
+					"mout_sclk_spll", "mout_sclk_epll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock
@@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock
 static const struct samsung_fixed_factor_clock
 		exynos5800_fixed_factor_clks[] __initconst = {
 	FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
-	FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
+	FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 };
 
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
@@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 	MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 
+	MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
+		mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
+
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
-			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
+			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
 	MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
 			SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
-	MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
+	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 
 	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
@@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 
 	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
-	MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 			"mout_aclk400_disp1", DIV_TOP2, 4, 3),
 
 	/* CDREX Block */
-	DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
-			DIV_CDREX0, 28, 3),
+	/*
+	 * The three clocks below are controlled using the same register and
+	 * bits. They are put into one because there is a need of
+	 * synchronization between the BUS and DREXs (two external memory
+	 * interfaces).
+	 * They are put here to show this HW assumption and for clock
+	 * information summary completeness.
+	 */
+	DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
+			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
+	DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
+			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
+	DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
+			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
+
 	DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
 			DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
 	DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
@@ -1170,6 +1193,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
 
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+
+	/* CDREX */
+	GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
+			GATE_BUS_CDREX0, 0, 0, 0),
+	GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
+			GATE_BUS_CDREX0, 1, 0, 0),
+	GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
+			SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
+			GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
+			GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
 };
 
 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
-- 
2.17.1

[PATCH v8 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC

[Lukasz Luba]

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index eecbfcc6b3cf..7ba6bf6700b2 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1334,6 +1334,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
 	PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
 };
 
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
+	PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
+	PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
+	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
+	PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
+	PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
+	PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
+	PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
+	PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
+};
+
 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
 	PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
 	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
@@ -1476,9 +1487,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
 		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
 		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
-		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 	}
 
+	if (soc == EXYNOS5420)
+		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+	else
+		exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
+
 	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
 					reg_base);
 	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
-- 
2.17.1

Re: [PATCH v8 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
> Controller frequencies for driver's DRAM timings.
>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v8 04/13] dt-bindings: ddr: rename lpddr2 directory

[Lukasz Luba]

Change directory name to be ready for new types of memories.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt      | 0
 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt    | 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%)
 rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%)

diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt
similarity index 100%
rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt
similarity index 96%
rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt
rename to Documentation/devicetree/bindings/ddr/lpddr2.txt
index 58354a075e13..ddd40121e6f6 100644
--- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
+++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt
@@ -36,7 +36,7 @@ Child nodes:
   "lpddr2-timings" provides AC timing parameters of the device for
   a given speed-bin. The user may provide the timings for as many
   speed-bins as is required. Please see Documentation/devicetree/
-  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+  bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
 
 Example:
 
-- 
2.17.1

[PATCH v8 05/13] dt-bindings: ddr: add LPDDR3 memories

[Lukasz Luba]

Specifies the AC timing parameters of the LPDDR3 memory device.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 .../bindings/ddr/lpddr3-timings.txt           | 58 +++++++++++
 .../devicetree/bindings/ddr/lpddr3.txt        | 97 +++++++++++++++++++
 2 files changed, 155 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
 create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt

diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
new file mode 100644
index 000000000000..84705e50a3fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
@@ -0,0 +1,58 @@
+* AC timing parameters of LPDDR3 memories for a given speed-bin.
+
+The structures are based on LPDDR2 and extended where needed.
+
+Required properties:
+- compatible : Should be "jedec,lpddr3-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds).
+- tRFC
+- tRRD
+- tRPab
+- tRPpb
+- tRCD
+- tRC
+- tRAS
+- tWTR
+- tWR
+- tRTP
+- tW2W-C2C
+- tR2R-C2C
+- tFAW
+- tXSR
+- tXP
+- tCKE
+- tCKESR
+- tMRD
+
+Example:
+
+timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+	compatible	= "jedec,lpddr3-timings";
+	reg		= <800000000>; /* workaround: it shows max-freq */
+	min-freq	= <100000000>;
+	tRFC		= <65000>;
+	tRRD		= <6000>;
+	tRPab		= <12000>;
+	tRPpb		= <12000>;
+	tRCD		= <10000>;
+	tRC		= <33750>;
+	tRAS		= <23000>;
+	tWTR		= <3750>;
+	tWR		= <7500>;
+	tRTP		= <3750>;
+	tW2W-C2C	= <0>;
+	tR2R-C2C	= <0>;
+	tFAW		= <25000>;
+	tXSR		= <70000>;
+	tXP		= <3750>;
+	tCKE		= <3750>;
+	tCKESR		= <3750>;
+	tMRD		= <7000>;
+};
diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt
new file mode 100644
index 000000000000..3b2485b84b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt
@@ -0,0 +1,97 @@
+* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
+
+Required properties:
+- compatible : Should be  - "jedec,lpddr3"
+- density  : <u32> representing density in Mb (Mega bits)
+- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
+- #address-cells: Must be set to 1
+- #size-cells: Must be set to 0
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRFC-min-tck
+- tRRD-min-tck
+- tRPab-min-tck
+- tRPpb-min-tck
+- tRCD-min-tck
+- tRC-min-tck
+- tRAS-min-tck
+- tWTR-min-tck
+- tWR-min-tck
+- tRTP-min-tck
+- tW2W-C2C-min-tck
+- tR2R-C2C-min-tck
+- tWL-min-tck
+- tDQSCK-min-tck
+- tRL-min-tck
+- tFAW-min-tck
+- tXSR-min-tck
+- tXP-min-tck
+- tCKE-min-tck
+- tCKESR-min-tck
+- tMRD-min-tck
+
+Child nodes:
+- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
+  "lpddr3-timings" provides AC timing parameters of the device for
+  a given speed-bin. Please see Documentation/devicetree/
+  bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"
+
+Example:
+
+samsung_K3QF2F20DB: lpddr3 {
+	compatible	= "Samsung,K3QF2F20DB", "jedec,lpddr3";
+	density		= <16384>;
+	io-width	= <32>;
+	#address-cells	= <1>;
+	#size-cells	= <0>;
+
+	tRFC-min-tck		= <17>;
+	tRRD-min-tck		= <2>;
+	tRPab-min-tck		= <2>;
+	tRPpb-min-tck		= <2>;
+	tRCD-min-tck		= <3>;
+	tRC-min-tck		= <6>;
+	tRAS-min-tck		= <5>;
+	tWTR-min-tck		= <2>;
+	tWR-min-tck		= <7>;
+	tRTP-min-tck		= <2>;
+	tW2W-C2C-min-tck	= <0>;
+	tR2R-C2C-min-tck	= <0>;
+	tWL-min-tck		= <8>;
+	tDQSCK-min-tck		= <5>;
+	tRL-min-tck		= <14>;
+	tFAW-min-tck		= <5>;
+	tXSR-min-tck		= <12>;
+	tXP-min-tck		= <2>;
+	tCKE-min-tck		= <2>;
+	tCKESR-min-tck		= <2>;
+	tMRD-min-tck		= <5>;
+
+	timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+		compatible	= "jedec,lpddr3-timings";
+		reg		= <800000000>; /* workaround: it shows max-freq */
+		min-freq	= <100000000>;
+		tRFC		= <65000>;
+		tRRD		= <6000>;
+		tRPab		= <12000>;
+		tRPpb		= <12000>;
+		tRCD		= <10000>;
+		tRC		= <33750>;
+		tRAS		= <23000>;
+		tWTR		= <3750>;
+		tWR		= <7500>;
+		tRTP		= <3750>;
+		tW2W-C2C	= <0>;
+		tR2R-C2C	= <0>;
+		tFAW		= <25000>;
+		tXSR		= <70000>;
+		tXP		= <3750>;
+		tCKE		= <3750>;
+		tCKESR		= <3750>;
+		tMRD		= <7000>;
+	};
+}
-- 
2.17.1

[PATCH v8 06/13] drivers: memory: extend of_memory by LPDDR3 support

[Lukasz Luba]

The patch adds AC timings information needed to support LPDDR3 and memory
controllers. The structure is used in of_memory and currently in Exynos
5422 DMC. Add parsing data needed for LPDDR3 support.
It is currently used in Exynos5422 Dynamic Memory Controller.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/memory/of_memory.c | 154 +++++++++++++++++++++++++++++++++++++
 drivers/memory/of_memory.h |  18 +++++
 include/memory/jedec_ddr.h |  62 +++++++++++++++
 3 files changed, 234 insertions(+)

diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
index 12a61f558644..30f3a3e75063 100644
--- a/drivers/memory/of_memory.c
+++ b/drivers/memory/of_memory.c
@@ -3,6 +3,12 @@
  * OpenFirmware helpers for memory drivers
  *
  * Copyright (C) 2012 Texas Instruments, Inc.
+ * Copyright (C) 2019 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  */
 
 #include <linux/device.h>
@@ -148,3 +154,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr,
 	return lpddr2_jedec_timings;
 }
 EXPORT_SYMBOL(of_get_ddr_timings);
+
+/**
+ * of_lpddr3_get_min_tck() - extract min timing values for lpddr3
+ * @np: pointer to ddr device tree node
+ * @device: device requesting for min timing values
+ *
+ * Populates the lpddr3_min_tck structure by extracting data
+ * from device tree node. Returns a pointer to the populated
+ * structure. If any error in populating the structure, returns NULL.
+ */
+const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
+						   struct device *dev)
+{
+	int			ret = 0;
+	struct lpddr3_min_tck	*min;
+
+	min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
+	if (!min)
+		goto default_min_tck;
+
+	ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC);
+	ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
+	ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
+	ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb);
+	ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
+	ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC);
+	ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS);
+	ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
+	ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
+	ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
+	ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C);
+	ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C);
+	ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL);
+	ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK);
+	ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL);
+	ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
+	ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR);
+	ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
+	ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
+	ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
+	ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD);
+
+	if (ret) {
+		dev_warn(dev, "%s: errors while parsing min-tck values\n",
+			 __func__);
+		devm_kfree(dev, min);
+		goto default_min_tck;
+	}
+
+	return min;
+
+default_min_tck:
+	dev_warn(dev, "%s: using default min-tck values\n", __func__);
+	return NULL;
+}
+EXPORT_SYMBOL(of_lpddr3_get_min_tck);
+
+static int of_lpddr3_do_get_timings(struct device_node *np,
+				    struct lpddr3_timings *tim)
+{
+	int ret;
+
+	/* The 'reg' param required since DT has changed, used as 'max-freq' */
+	ret = of_property_read_u32(np, "reg", &tim->max_freq);
+	ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
+	ret |= of_property_read_u32(np, "tRFC", &tim->tRFC);
+	ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
+	ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
+	ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb);
+	ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
+	ret |= of_property_read_u32(np, "tRC", &tim->tRC);
+	ret |= of_property_read_u32(np, "tRAS", &tim->tRAS);
+	ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
+	ret |= of_property_read_u32(np, "tWR", &tim->tWR);
+	ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
+	ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C);
+	ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C);
+	ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
+	ret |= of_property_read_u32(np, "tXSR", &tim->tXSR);
+	ret |= of_property_read_u32(np, "tXP", &tim->tXP);
+	ret |= of_property_read_u32(np, "tCKE", &tim->tCKE);
+	ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
+	ret |= of_property_read_u32(np, "tMRD", &tim->tMRD);
+
+	return ret;
+}
+
+/**
+ * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of
+ * frequencies available.
+ * @np_ddr: Pointer to ddr device tree node
+ * @dev: Device requesting for ddr timings
+ * @device_type: Type of ddr
+ * @nr_frequencies: No of frequencies available for ddr
+ * (updated by this function)
+ *
+ * Populates lpddr3_timings structure by extracting data from device
+ * tree node. Returns pointer to populated structure. If any error
+ * while populating, returns NULL.
+ */
+const struct lpddr3_timings
+*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
+			   u32 device_type, u32 *nr_frequencies)
+{
+	struct lpddr3_timings	*timings = NULL;
+	u32			arr_sz = 0, i = 0;
+	struct device_node	*np_tim;
+	char			*tim_compat = NULL;
+
+	switch (device_type) {
+	case DDR_TYPE_LPDDR3:
+		tim_compat = "jedec,lpddr3-timings";
+		break;
+	default:
+		dev_warn(dev, "%s: un-supported memory type\n", __func__);
+	}
+
+	for_each_child_of_node(np_ddr, np_tim)
+		if (of_device_is_compatible(np_tim, tim_compat))
+			arr_sz++;
+
+	if (arr_sz)
+		timings = devm_kcalloc(dev, arr_sz, sizeof(*timings),
+				       GFP_KERNEL);
+
+	if (!timings)
+		goto default_timings;
+
+	for_each_child_of_node(np_ddr, np_tim) {
+		if (of_device_is_compatible(np_tim, tim_compat)) {
+			if (of_lpddr3_do_get_timings(np_tim, &timings[i])) {
+				devm_kfree(dev, timings);
+				goto default_timings;
+			}
+			i++;
+		}
+	}
+
+	*nr_frequencies = arr_sz;
+
+	return timings;
+
+default_timings:
+	dev_warn(dev, "%s: using default timings\n", __func__);
+	*nr_frequencies = 0;
+	return NULL;
+}
+EXPORT_SYMBOL(of_lpddr3_get_ddr_timings);
diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h
index b077cc836b0b..e39ecc4c733d 100644
--- a/drivers/memory/of_memory.h
+++ b/drivers/memory/of_memory.h
@@ -14,6 +14,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np,
 extern const struct lpddr2_timings
 	*of_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
 	u32 device_type, u32 *nr_frequencies);
+extern const struct lpddr3_min_tck
+	*of_lpddr3_get_min_tck(struct device_node *np, struct device *dev);
+extern const struct lpddr3_timings
+	*of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
+	struct device *dev, u32 device_type, u32 *nr_frequencies);
 #else
 static inline const struct lpddr2_min_tck
 	*of_get_min_tck(struct device_node *np, struct device *dev)
@@ -27,6 +32,19 @@ static inline const struct lpddr2_timings
 {
 	return NULL;
 }
+
+static inline const struct lpddr3_min_tck
+	*of_lpddr3_get_min_tck(struct device_node *np, struct device *dev)
+{
+	return NULL;
+}
+
+static inline const struct lpddr3_timings
+	*of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
+	struct device *dev, u32 device_type, u32 *nr_frequencies)
+{
+	return NULL;
+}
 #endif /* CONFIG_OF && CONFIG_DDR */
 
 #endif /* __LINUX_MEMORY_OF_REG_ */
diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h
index ddad0f870e5d..3601825f807d 100644
--- a/include/memory/jedec_ddr.h
+++ b/include/memory/jedec_ddr.h
@@ -32,6 +32,7 @@
 #define DDR_TYPE_LPDDR2_S4	3
 #define DDR_TYPE_LPDDR2_S2	4
 #define DDR_TYPE_LPDDR2_NVM	5
+#define DDR_TYPE_LPDDR3		6
 
 /* DDR IO width */
 #define DDR_IO_WIDTH_4		1
@@ -172,4 +173,65 @@ extern const struct lpddr2_timings
 	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
 extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
 
+
+/*
+ * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr3_timings {
+	u32 max_freq;
+	u32 min_freq;
+	u32 tRFC;
+	u32 tRRD;
+	u32 tRPab;
+	u32 tRPpb;
+	u32 tRCD;
+	u32 tRC;
+	u32 tRAS;
+	u32 tWTR;
+	u32 tWR;
+	u32 tRTP;
+	u32 tW2W_C2C;
+	u32 tR2R_C2C;
+	u32 tWL;
+	u32 tDQSCK;
+	u32 tRL;
+	u32 tFAW;
+	u32 tXSR;
+	u32 tXP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tMRD;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr3_min_tck {
+	u32 tRFC;
+	u32 tRRD;
+	u32 tRPab;
+	u32 tRPpb;
+	u32 tRCD;
+	u32 tRC;
+	u32 tRAS;
+	u32 tWTR;
+	u32 tWR;
+	u32 tRTP;
+	u32 tW2W_C2C;
+	u32 tR2R_C2C;
+	u32 tWL;
+	u32 tDQSCK;
+	u32 tRL;
+	u32 tFAW;
+	u32 tXSR;
+	u32 tXP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tMRD;
+};
+
 #endif /* __LINUX_JEDEC_DDR_H */
-- 
2.17.1

Re: [PATCH v8 06/13] drivers: memory: extend of_memory by LPDDR3 support

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The patch adds AC timings information needed to support LPDDR3 and memory
> controllers. The structure is used in of_memory and currently in Exynos
> 5422 DMC. Add parsing data needed for LPDDR3 support.
> It is currently used in Exynos5422 Dynamic Memory Controller.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/memory/of_memory.c | 154 +++++++++++++++++++++++++++++++++++++
>  drivers/memory/of_memory.h |  18 +++++
>  include/memory/jedec_ddr.h |  62 +++++++++++++++
>  3 files changed, 234 insertions(+)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v8 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description

[Lukasz Luba]

The patch adds description for DT binding for a new Exynos5422 Dynamic
Memory Controller device.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 .../memory-controllers/exynos5422-dmc.txt     | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
new file mode 100644
index 000000000000..989ee0839fdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
@@ -0,0 +1,84 @@
+* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
+
+The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
+memory chips are connected. The driver is to monitor the controller in runtime
+and switch frequency and voltage. To monitor the usage of the controller in
+runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
+is able to measure the current load of the memory.
+When 'userspace' governor is used for the driver, an application is able to
+switch the DMC and memory frequency.
+
+Required properties for DMC device for Exynos5422:
+- compatible: Should be "samsung,exynos5422-dmc".
+- clocks : list of clock specifiers, must contain an entry for each
+  required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
+  CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
+  CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
+  CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
+- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
+  "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
+  "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
+  "clkm_phy1" entries
+- devfreq-events : phandles for PPMU devices connected to this DMC.
+- vdd-supply : phandle for voltage regulator which is connected.
+- reg : registers of two CDREX controllers.
+- operating-points-v2 : phandle for OPPs described in v2 definition.
+- device-handle : phandle of the connected DRAM memory device. For more
+	information please refer to documentation file:
+	Documentation/devicetree/bindings/ddr/lpddr3.txt
+- devfreq-events : phandles of the PPMU events used by the controller.
+- samsung,syscon-clk : phandle of the clock register set used by the controller,
+	these registers are used for enabling a 'pause' feature and are not
+	exposed by clock framework but they must be used in a safe way.
+	The register offsets are in the driver code and specyfic for this SoC
+	type.
+
+Example:
+
+	ppmu_dmc0_0: ppmu@10d00000 {
+		compatible = "samsung,exynos-ppmu";
+		reg = <0x10d00000 0x2000>;
+		clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+		clock-names = "ppmu";
+		events {
+			ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+				event-name = "ppmu-event3-dmc0_0";
+			};
+		};
+	};
+
+	dmc: memory-controller@10c20000 {
+		compatible = "samsung,exynos5422-dmc";
+		reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
+		clocks = 	<&clock CLK_FOUT_SPLL>,
+				<&clock CLK_MOUT_SCLK_SPLL>,
+				<&clock CLK_FF_DOUT_SPLL2>,
+				<&clock CLK_FOUT_BPLL>,
+				<&clock CLK_MOUT_BPLL>,
+				<&clock CLK_SCLK_BPLL>,
+				<&clock CLK_MOUT_MX_MSPLL_CCORE>,
+				<&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+				<&clock CLK_MOUT_MCLK_CDREX>,
+				<&clock CLK_DOUT_CLK2X_PHY0>,
+				<&clock CLK_CLKM_PHY0>,
+				<&clock CLK_CLKM_PHY1>;
+		clock-names =	"fout_spll",
+				"mout_sclk_spll",
+				"ff_dout_spll2",
+				"fout_bpll",
+				"mout_bpll",
+				"sclk_bpll",
+				"mout_mx_mspll_ccore",
+				"mout_mx_mspll_ccore_phy",
+				"mout_mclk_cdrex",
+				"dout_clk2x_phy0",
+				"clkm_phy0",
+			        "clkm_phy1";
+		operating-points-v2 = <&dmc_opp_table>;
+		devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,
+				<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+		operating-points-v2 = <&dmc_opp_table>;
+		device-handle = <&samsung_K3QF2F20DB>;
+		vdd-supply = <&buck1_reg>;
+		samsung,syscon-clk = <&clock>;
+	};
-- 
2.17.1

Re: [PATCH v8 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The patch adds description for DT binding for a new Exynos5422 Dynamic
> Memory Controller device.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  .../memory-controllers/exynos5422-dmc.txt     | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> new file mode 100644
> index 000000000000..989ee0839fdf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> @@ -0,0 +1,84 @@
> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
> +
> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
> +memory chips are connected. The driver is to monitor the controller in runtime
> +and switch frequency and voltage. To monitor the usage of the controller in
> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
> +is able to measure the current load of the memory.
> +When 'userspace' governor is used for the driver, an application is able to
> +switch the DMC and memory frequency.
> +
> +Required properties for DMC device for Exynos5422:
> +- compatible: Should be "samsung,exynos5422-dmc".
> +- clocks : list of clock specifiers, must contain an entry for each
> +  required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
> +  CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
> +  CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
> +  CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
> +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
> +  "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
> +  "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
> +  "clkm_phy1" entries
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
> +- vdd-supply : phandle for voltage regulator which is connected.
> +- reg : registers of two CDREX controllers.
> +- operating-points-v2 : phandle for OPPs described in v2 definition.
> +- device-handle : phandle of the connected DRAM memory device. For more
> +       information please refer to documentation file:
> +       Documentation/devicetree/bindings/ddr/lpddr3.txt
> +- devfreq-events : phandles of the PPMU events used by the controller.
> +- samsung,syscon-clk : phandle of the clock register set used by the controller,
> +       these registers are used for enabling a 'pause' feature and are not
> +       exposed by clock framework but they must be used in a safe way.
> +       The register offsets are in the driver code and specyfic for this SoC
> +       type.
> +
> +Example:
> +
> +       ppmu_dmc0_0: ppmu@10d00000 {
> +               compatible = "samsung,exynos-ppmu";
> +               reg = <0x10d00000 0x2000>;
> +               clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> +               clock-names = "ppmu";
> +               events {
> +                       ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> +                               event-name = "ppmu-event3-dmc0_0";
> +                       };
> +               };
> +       };
> +
> +       dmc: memory-controller@10c20000 {
> +               compatible = "samsung,exynos5422-dmc";
> +               reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
> +               clocks =        <&clock CLK_FOUT_SPLL>,

I think you should not have tab after '='. Instead align consecutive
lines with the first one.

> +                               <&clock CLK_MOUT_SCLK_SPLL>,
> +                               <&clock CLK_FF_DOUT_SPLL2>,
> +                               <&clock CLK_FOUT_BPLL>,
> +                               <&clock CLK_MOUT_BPLL>,
> +                               <&clock CLK_SCLK_BPLL>,
> +                               <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> +                               <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> +                               <&clock CLK_MOUT_MCLK_CDREX>,
> +                               <&clock CLK_DOUT_CLK2X_PHY0>,
> +                               <&clock CLK_CLKM_PHY0>,
> +                               <&clock CLK_CLKM_PHY1>;
> +               clock-names =   "fout_spll",
> +                               "mout_sclk_spll",
> +                               "ff_dout_spll2",
> +                               "fout_bpll",
> +                               "mout_bpll",
> +                               "sclk_bpll",
> +                               "mout_mx_mspll_ccore",
> +                               "mout_mx_mspll_ccore_phy",
> +                               "mout_mclk_cdrex",
> +                               "dout_clk2x_phy0",
> +                               "clkm_phy0",
> +                               "clkm_phy1";
> +               operating-points-v2 = <&dmc_opp_table>;
> +               devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
> +                               <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
> +               operating-points-v2 = <&dmc_opp_table>;

Duplicated property.

Beside that:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

> +               device-handle = <&samsung_K3QF2F20DB>;
> +               vdd-supply = <&buck1_reg>;
> +               samsung,syscon-clk = <&clock>;
> +       };
> --
> 2.17.1
>

Re: [PATCH v8 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description

[Lukasz Luba]

Hi Krzysztof,

On 6/6/19 10:29 AM, Krzysztof Kozlowski wrote:
> On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>> Memory Controller device.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   .../memory-controllers/exynos5422-dmc.txt     | 84 +++++++++++++++++++
>>   1 file changed, 84 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> new file mode 100644
>> index 000000000000..989ee0839fdf
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> @@ -0,0 +1,84 @@
>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>> +
>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>> +memory chips are connected. The driver is to monitor the controller in runtime
>> +and switch frequency and voltage. To monitor the usage of the controller in
>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>> +is able to measure the current load of the memory.
>> +When 'userspace' governor is used for the driver, an application is able to
>> +switch the DMC and memory frequency.
>> +
>> +Required properties for DMC device for Exynos5422:
>> +- compatible: Should be "samsung,exynos5422-dmc".
>> +- clocks : list of clock specifiers, must contain an entry for each
>> +  required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
>> +  CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
>> +  CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
>> +  CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
>> +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
>> +  "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
>> +  "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
>> +  "clkm_phy1" entries
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>> +- vdd-supply : phandle for voltage regulator which is connected.
>> +- reg : registers of two CDREX controllers.
>> +- operating-points-v2 : phandle for OPPs described in v2 definition.
>> +- device-handle : phandle of the connected DRAM memory device. For more
>> +       information please refer to documentation file:
>> +       Documentation/devicetree/bindings/ddr/lpddr3.txt
>> +- devfreq-events : phandles of the PPMU events used by the controller.
>> +- samsung,syscon-clk : phandle of the clock register set used by the controller,
>> +       these registers are used for enabling a 'pause' feature and are not
>> +       exposed by clock framework but they must be used in a safe way.
>> +       The register offsets are in the driver code and specyfic for this SoC
>> +       type.
>> +
>> +Example:
>> +
>> +       ppmu_dmc0_0: ppmu@10d00000 {
>> +               compatible = "samsung,exynos-ppmu";
>> +               reg = <0x10d00000 0x2000>;
>> +               clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> +               clock-names = "ppmu";
>> +               events {
>> +                       ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> +                               event-name = "ppmu-event3-dmc0_0";
>> +                       };
>> +               };
>> +       };
>> +
>> +       dmc: memory-controller@10c20000 {
>> +               compatible = "samsung,exynos5422-dmc";
>> +               reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
>> +               clocks =        <&clock CLK_FOUT_SPLL>,
> 
> I think you should not have tab after '='. Instead align consecutive
> lines with the first one.
I will change it, since there is a need of removing the duplicates below
> 
>> +                               <&clock CLK_MOUT_SCLK_SPLL>,
>> +                               <&clock CLK_FF_DOUT_SPLL2>,
>> +                               <&clock CLK_FOUT_BPLL>,
>> +                               <&clock CLK_MOUT_BPLL>,
>> +                               <&clock CLK_SCLK_BPLL>,
>> +                               <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> +                               <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> +                               <&clock CLK_MOUT_MCLK_CDREX>,
>> +                               <&clock CLK_DOUT_CLK2X_PHY0>,
>> +                               <&clock CLK_CLKM_PHY0>,
>> +                               <&clock CLK_CLKM_PHY1>;
>> +               clock-names =   "fout_spll",
>> +                               "mout_sclk_spll",
>> +                               "ff_dout_spll2",
>> +                               "fout_bpll",
>> +                               "mout_bpll",
>> +                               "sclk_bpll",
>> +                               "mout_mx_mspll_ccore",
>> +                               "mout_mx_mspll_ccore_phy",
>> +                               "mout_mclk_cdrex",
>> +                               "dout_clk2x_phy0",
>> +                               "clkm_phy0",
>> +                               "clkm_phy1";
>> +               operating-points-v2 = <&dmc_opp_table>;
>> +               devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
>> +                               <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
>> +               operating-points-v2 = <&dmc_opp_table>;
> 
> Duplicated property.
Right, I will remove it and re-send it.
> 
> Beside that:
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Thank you

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
>> +               device-handle = <&samsung_K3QF2F20DB>;
>> +               vdd-supply = <&buck1_reg>;
>> +               samsung,syscon-clk = <&clock>;
>> +       };
>> --
>> 2.17.1
>>
> 
> 

[PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422

[Lukasz Luba]

This patch adds driver for Exynos5422 Dynamic Memory Controller.
The driver provides support for dynamic frequency and voltage scaling for
DMC and DRAM. It supports changing timings of DRAM running with different
frequency. There is also an algorithm to calculate timigns based on
memory description provided in DT.
The patch also contains needed MAINTAINERS file update.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 MAINTAINERS                             |    8 +
 drivers/memory/samsung/Kconfig          |   17 +
 drivers/memory/samsung/Makefile         |    1 +
 drivers/memory/samsung/exynos5422-dmc.c | 1265 +++++++++++++++++++++++
 4 files changed, 1291 insertions(+)
 create mode 100644 drivers/memory/samsung/exynos5422-dmc.c

diff --git a/MAINTAINERS b/MAINTAINERS
index a6954776a37e..d57cf4be1e51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3470,6 +3470,14 @@ S:	Maintained
 F:	drivers/devfreq/exynos-bus.c
 F:	Documentation/devicetree/bindings/devfreq/exynos-bus.txt
 
+DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
+M:	Lukasz Luba <l.luba@partner.samsung.com>
+L:	linux-pm@vger.kernel.org
+L:	linux-samsung-soc@vger.kernel.org
+S:	Maintained
+F:	drivers/memory/samsung/exynos5422-dmc.c
+F:	Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
+
 BUSLOGIC SCSI DRIVER
 M:	Khalid Aziz <khalid@gonehiking.org>
 L:	linux-scsi@vger.kernel.org
diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig
index 79ce7ea58903..c93baa029654 100644
--- a/drivers/memory/samsung/Kconfig
+++ b/drivers/memory/samsung/Kconfig
@@ -5,6 +5,23 @@ config SAMSUNG_MC
 	  Support for the Memory Controller (MC) devices found on
 	  Samsung Exynos SoCs.
 
+config ARM_EXYNOS5422_DMC
+	tristate "ARM EXYNOS5422 Dynamic Memory Controller driver"
+	depends on ARCH_EXYNOS
+	select DDR
+	select PM_DEVFREQ
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select DEVFREQ_GOV_USERSPACE
+	select PM_DEVFREQ_EVENT
+	select PM_OPP
+	help
+	  This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
+	  The driver provides support for Dynamic Voltage and Frequency Scaling in
+	  DMC and DRAM. It also supports changing timings of DRAM running with
+	  different frequency. The timings are calculated based on DT memory
+	  information.
+
+
 if SAMSUNG_MC
 
 config EXYNOS_SROM
diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile
index 00587be66211..4f6e4383bab7 100644
--- a/drivers/memory/samsung/Makefile
+++ b/drivers/memory/samsung/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_ARM_EXYNOS5422_DMC)	+= exynos5422-dmc.o
 obj-$(CONFIG_EXYNOS_SROM)	+= exynos-srom.o
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
new file mode 100644
index 000000000000..6fca9e4c45ff
--- /dev/null
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -0,0 +1,1265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd.
+ * Author: Lukasz Luba <l.luba@partner.samsung.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <memory/jedec_ddr.h>
+#include "../of_memory.h"
+
+#define EXYNOS5_DREXI_TIMINGAREF		(0x0030)
+#define EXYNOS5_DREXI_TIMINGROW0		(0x0034)
+#define EXYNOS5_DREXI_TIMINGDATA0		(0x0038)
+#define EXYNOS5_DREXI_TIMINGPOWER0		(0x003C)
+#define EXYNOS5_DREXI_TIMINGROW1		(0x00E4)
+#define EXYNOS5_DREXI_TIMINGDATA1		(0x00E8)
+#define EXYNOS5_DREXI_TIMINGPOWER1		(0x00EC)
+#define CDREX_PAUSE				(0x2091c)
+#define CDREX_LPDDR3PHY_CON3			(0x20a20)
+#define EXYNOS5_TIMING_SET_SWI                  (1UL << 28)
+#define USE_MX_MSPLL_TIMINGS			(1)
+#define USE_BPLL_TIMINGS			(0)
+#define EXYNOS5_AREF_NORMAL			(0x2e)
+
+/**
+ * struct dmc_opp_table - Operating level desciption
+ *
+ * Covers frequency and voltage settings of the DMC operating mode.
+ */
+struct dmc_opp_table {
+	u32 freq_hz;
+	u32 volt_uv;
+};
+
+/**
+ * struct exynos5_dmc - main structure describing DMC device
+ *
+ * The main structure for the Dynamic Memory Controller which covers clocks,
+ * memory regions, HW information, parameters and current operating mode.
+ */
+struct exynos5_dmc {
+	struct device *dev;
+	struct devfreq *df;
+	struct devfreq_simple_ondemand_data gov_data;
+	void __iomem *base_drexi0;
+	void __iomem *base_drexi1;
+	struct regmap *clk_regmap;
+	struct mutex lock;
+	unsigned long curr_rate;
+	unsigned long curr_volt;
+	unsigned long bypass_rate;
+	struct dmc_opp_table *opp;
+	struct dmc_opp_table opp_bypass;
+	int opp_count;
+	u32 timings_arr_size;
+	u32 *timing_row;
+	u32 *timing_data;
+	u32 *timing_power;
+	const struct lpddr3_timings *timings;
+	const struct lpddr3_min_tck *min_tck;
+	u32 bypass_timing_row;
+	u32 bypass_timing_data;
+	u32 bypass_timing_power;
+	struct regulator *vdd_mif;
+	struct clk *fout_spll;
+	struct clk *fout_bpll;
+	struct clk *mout_spll;
+	struct clk *mout_bpll;
+	struct clk *mout_mclk_cdrex;
+	struct clk *dout_clk2x_phy0;
+	struct clk *mout_mx_mspll_ccore;
+	struct clk *mx_mspll_ccore_phy;
+	struct clk *mout_mx_mspll_ccore_phy;
+	struct devfreq_event_dev **counter;
+	int num_counters;
+};
+
+#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
+	{ .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
+
+#define TIMING_VAL(timing_array, id, t_val)			\
+({								\
+		u32 __val;				\
+		__val = t_val << timing_array[id].bit_beg;	\
+		__val;						\
+})
+
+#define TIMING_VAL2REG(timing, t_val)			\
+({								\
+		u32 __val;				\
+		__val = t_val << timing->bit_beg;	\
+		__val;						\
+})
+
+#define TIMING_REG2VAL(reg, timing)			\
+({								\
+		u32 __val;				\
+		reg <<= (31 - timing->bit_end);		\
+		reg >>= (31 - timing->bit_end);		\
+		__val = reg >> timing->bit_beg;	\
+		__val;						\
+})
+
+struct timing_reg {
+	char *name;
+	int bit_beg;
+	int bit_end;
+	unsigned int val;
+};
+
+static const struct timing_reg timing_row[] = {
+	TIMING_FIELD("tRFC", 24, 31),
+	TIMING_FIELD("tRRD", 20, 23),
+	TIMING_FIELD("tRP", 16, 19),
+	TIMING_FIELD("tRCD", 12, 15),
+	TIMING_FIELD("tRC", 6, 11),
+	TIMING_FIELD("tRAS", 0, 5),
+};
+
+static const struct timing_reg timing_data[] = {
+	TIMING_FIELD("tWTR", 28, 31),
+	TIMING_FIELD("tWR", 24, 27),
+	TIMING_FIELD("tRTP", 20, 23),
+	TIMING_FIELD("tW2W-C2C", 14, 14),
+	TIMING_FIELD("tR2R-C2C", 12, 12),
+	TIMING_FIELD("WL", 8, 11),
+	TIMING_FIELD("tDQSCK", 4, 7),
+	TIMING_FIELD("RL", 0, 3),
+};
+
+static const struct timing_reg timing_power[] = {
+	TIMING_FIELD("tFAW", 26, 31),
+	TIMING_FIELD("tXSR", 16, 25),
+	TIMING_FIELD("tXP", 8, 15),
+	TIMING_FIELD("tCKE", 4, 7),
+	TIMING_FIELD("tMRD", 0, 3),
+};
+
+#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
+		      ARRAY_SIZE(timing_power))
+
+static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
+{
+	int i, ret;
+
+	for (i = 0; i < dmc->num_counters; i++) {
+		if (!dmc->counter[i])
+			continue;
+		ret = devfreq_event_set_event(dmc->counter[i]);
+		if (ret < 0)
+			return ret;
+	}
+	return 0;
+}
+
+static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
+{
+	int i, ret;
+
+	for (i = 0; i < dmc->num_counters; i++) {
+		if (!dmc->counter[i])
+			continue;
+		ret = devfreq_event_enable_edev(dmc->counter[i]);
+		if (ret < 0)
+			return ret;
+	}
+	return 0;
+}
+
+static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
+{
+	int i, ret;
+
+	for (i = 0; i < dmc->num_counters; i++) {
+		if (!dmc->counter[i])
+			continue;
+		ret = devfreq_event_disable_edev(dmc->counter[i]);
+		if (ret < 0)
+			return ret;
+	}
+	return 0;
+}
+
+/**
+ * find_target_freq_id() - Finds requested frequency in local DMC configuration
+ * @dmc:	device for which the information is checked
+ * @target_rate:	requested frequency in KHz
+ *
+ * Seeks in the local DMC driver structure for the requested frequency value
+ * and returns index or error value.
+ */
+static int find_target_freq_idx(struct exynos5_dmc *dmc,
+				unsigned long target_rate)
+{
+	int i;
+
+	for (i = dmc->opp_count - 1; i >= 0; i--)
+		if (dmc->opp[i].freq_hz <= target_rate)
+			return i;
+
+	return -EINVAL;
+}
+
+/**
+ * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
+ * @dmc:	device for which the new settings is going to be applied
+ * @set:	boolean variable passing set value
+ *
+ * Changes the register set, which holds timing parameters.
+ * There is two register sets: 0 and 1. The register set 0
+ * is used in normal operation when the clock is provided from main PLL.
+ * The bank register set 1 is used when the main PLL frequency is going to be
+ * changed and the clock is taken from alternative, stable source.
+ * This function switches between these banks according to the
+ * currently used clock source.
+ */
+static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
+{
+	unsigned int reg;
+	int ret;
+
+	ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg);
+
+	if (set)
+		reg |= EXYNOS5_TIMING_SET_SWI;
+	else
+		reg &= ~EXYNOS5_TIMING_SET_SWI;
+
+	regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
+}
+
+/**
+ * exynos5_init_freq_table() - Initialized PM OPP framework
+ * @dmc:	DMC device for which the frequencies are used for OPP init
+ * @profile:	devfreq device's profile
+ *
+ * Populate the devfreq device's OPP table based on current frequency, voltage.
+ */
+static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
+				   struct devfreq_dev_profile *profile)
+{
+	int i, ret;
+	int idx;
+	unsigned long freq;
+
+	ret = dev_pm_opp_of_add_table(dmc->dev);
+	if (ret < 0) {
+		dev_err(dmc->dev, "Failed to get OPP table\n");
+		return ret;
+	}
+
+	dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
+
+	dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
+				      sizeof(struct dmc_opp_table), GFP_KERNEL);
+	if (!dmc->opp)
+		goto err_opp;
+
+	idx = dmc->opp_count - 1;
+	for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
+		struct dev_pm_opp *opp;
+
+		opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
+		if (IS_ERR(opp))
+			goto err_free_tables;
+
+		dmc->opp[idx - i].freq_hz = freq;
+		dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
+
+		dev_pm_opp_put(opp);
+	}
+
+	return 0;
+
+err_free_tables:
+	kfree(dmc->opp);
+err_opp:
+	dev_pm_opp_of_remove_table(dmc->dev);
+
+	return -EINVAL;
+}
+
+/**
+ * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
+ * @dmc:	device for which the new settings is going to be applied
+ * @param:	DRAM parameters which passes timing data
+ *
+ * Low-level function for changing timings for DRAM memory clocking from
+ * 'bypass' clock source (fixed frequency @400MHz).
+ * It uses timing bank registers set 1.
+ */
+static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
+{
+	writel(EXYNOS5_AREF_NORMAL,
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
+
+	writel(dmc->bypass_timing_row,
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
+	writel(dmc->bypass_timing_row,
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
+	writel(dmc->bypass_timing_data,
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
+	writel(dmc->bypass_timing_data,
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
+	writel(dmc->bypass_timing_power,
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
+	writel(dmc->bypass_timing_power,
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
+}
+
+/**
+ * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
+ * @dmc:	device for which the new settings is going to be applied
+ * @target_rate:	target frequency of the DMC
+ *
+ * Low-level function for changing timings for DRAM memory operating from main
+ * clock source (BPLL), which can have different frequencies. Thus, each
+ * frequency must have corresponding timings register values in order to keep
+ * the needed delays.
+ * It uses timing bank registers set 0.
+ */
+static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
+				       unsigned long target_rate)
+{
+	int idx;
+
+	for (idx = dmc->opp_count - 1; idx >= 0; idx--)
+		if (dmc->opp[idx].freq_hz <= target_rate)
+			break;
+
+	if (idx < 0)
+		return -EINVAL;
+
+	writel(EXYNOS5_AREF_NORMAL,
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
+
+	writel(dmc->timing_row[idx],
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
+	writel(dmc->timing_row[idx],
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
+	writel(dmc->timing_data[idx],
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
+	writel(dmc->timing_data[idx],
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
+	writel(dmc->timing_power[idx],
+	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
+	writel(dmc->timing_power[idx],
+	       dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
+ * @dmc:	device for which it is going to be set
+ * @target_volt:	new voltage which is chosen to be final
+ *
+ * Function tries to align voltage to the safe level for 'normal' mode.
+ * It checks the need of higher voltage and changes the value. The target
+ * voltage might be lower that currently set and still the system will be
+ * stable.
+ */
+static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
+					    unsigned long target_volt)
+{
+	int ret = 0;
+
+	if (dmc->curr_volt > target_volt) {
+		ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
+					    target_volt);
+		if (!ret)
+			dmc->curr_volt = target_volt;
+	}
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
+ * @dmc:	device for which it is going to be set
+ * @target_volt:	new voltage which is chosen to be final
+ *
+ * Function tries to align voltage to the safe level for the 'bypass' mode.
+ * It checks the need of higher voltage and changes the value.
+ * The target voltage must not be less than currently needed, because
+ * for current frequency the device might become unstable.
+ */
+static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
+					    unsigned long target_volt)
+{
+	int ret = 0;
+	unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
+
+	target_volt = max(bypass_volt, target_volt);
+
+	if (dmc->curr_volt >= target_volt)
+		return 0;
+
+	ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
+				    target_volt);
+	if (!ret)
+		dmc->curr_volt = target_volt;
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
+ * @dmc:	device for which it is going to be set
+ * @target_rate:	new frequency which is chosen to be final
+ *
+ * Function changes the DRAM timings for the temporary 'bypass' mode.
+ */
+static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
+						 unsigned long target_rate)
+{
+	int idx = find_target_freq_idx(dmc, target_rate);
+
+	if (idx < 0)
+		return -EINVAL;
+
+	exynos5_set_bypass_dram_timings(dmc);
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
+ * @dmc:	DMC device for which the switching is going to happen
+ * @target_rate:	new frequency which is going to be set as a final
+ * @target_volt:	new voltage which is going to be set as a final
+ *
+ * Function configures DMC and clocks for operating in temporary 'bypass' mode.
+ * This mode is used only temporary but if required, changes voltage and timings
+ * for DRAM chips. It switches the main clock to stable clock source for the
+ * period of the main PLL reconfiguration.
+ */
+static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
+				   unsigned long target_rate,
+				   unsigned long target_volt)
+{
+	int ret;
+
+	/*
+	 * Having higher voltage for a particular frequency does not harm
+	 * the chip. Use it for the temporary frequency change when one
+	 * voltage manipulation might be avoided.
+	 */
+	ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
+	if (ret)
+		return ret;
+
+	/*
+	 * Longer delays for DRAM does not cause crash, the opposite does.
+	 */
+	ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
+	if (ret)
+		return ret;
+
+	/*
+	 * Delays are long enough, so use them for the new coming clock.
+	 */
+	exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
+ * using safe procedure
+ * @dmc:	device for which the frequency is going to be changed
+ * @target_rate:	requested new frequency
+ * @target_volt:	requested voltage which corresponds to the new frequency
+ *
+ * The DMC frequency change procedure requires a few steps.
+ * The main requirement is to change the clock source in the clk mux
+ * for the time of main clock PLL locking. The assumption is that the
+ * alternative clock source set as parent is stable.
+ * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
+ * clock. This requires alignment in DRAM timing parameters for the new
+ * T-period. There is two bank sets for keeping DRAM
+ * timings: set 0 and set 1. The set 0 is used when main clock source is
+ * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
+ * the two bank sets is part of the process.
+ * The voltage must also be aligned to the minimum required level. There is
+ * this intermediate step with switching to 'bypass' parent clock source.
+ * if the old voltage is lower, it requires an increase of the voltage level.
+ * The complexity of the voltage manipulation is hidden in low level function.
+ * In this function there is last alignment of the voltage level at the end.
+ */
+static int
+exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
+				 unsigned long target_rate,
+				 unsigned long target_volt)
+{
+	int ret;
+
+	ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
+							 target_volt);
+	if (ret)
+		return ret;
+
+	/*
+	 * Voltage is set at least to a level needed for this frequency,
+	 * so switching clock source is safe now.
+	 */
+	clk_prepare_enable(dmc->fout_spll);
+	clk_prepare_enable(dmc->mout_spll);
+	clk_prepare_enable(dmc->mout_mx_mspll_ccore);
+
+	ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
+	if (ret)
+		return ret;
+
+	/*
+	 * We are safe to increase the timings for current bypass frequency.
+	 * Thanks to this the settings we be ready for the upcoming clock source
+	 * change.
+	 */
+	exynos5_dram_change_timings(dmc, target_rate);
+
+	clk_set_rate(dmc->fout_bpll, target_rate);
+
+	exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
+
+	ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
+	if (ret)
+		return ret;
+
+	clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
+	clk_disable_unprepare(dmc->mout_spll);
+	clk_disable_unprepare(dmc->fout_spll);
+
+	/*
+	 * Make sure if the voltage is not from 'bypass' settings and align to
+	 * the right level for power efficiency.
+	 */
+	ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
+ * table.
+ * @dmc:	device for which the frequency is going to be changed
+ * @freq:       requested frequency in KHz
+ * @target_rate:	returned frequency which is the same or lower than
+ *			requested
+ * @target_volt:	returned voltage which corresponds to the returned
+ *			frequency
+ *
+ * Function gets requested frequency and checks OPP framework for needed
+ * frequency and voltage. It populates the values 'target_rate' and
+ * 'target_volt' or returns error value when OPP framework fails.
+ */
+static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
+				     unsigned long *freq,
+				     unsigned long *target_rate,
+				     unsigned long *target_volt, u32 flags)
+{
+	struct dev_pm_opp *opp;
+
+	opp = devfreq_recommended_opp(dmc->dev, freq, flags);
+	if (IS_ERR(opp))
+		return PTR_ERR(opp);
+
+	*target_rate = dev_pm_opp_get_freq(opp);
+	*target_volt = dev_pm_opp_get_voltage(opp);
+	dev_pm_opp_put(opp);
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_target() - Function responsible for changing frequency of DMC
+ * @dev:	device for which the frequency is going to be changed
+ * @freq:	requested frequency in KHz
+ * @flags:	flags provided for this frequency change request
+ *
+ * An entry function provided to the devfreq framework which provides frequency
+ * change of the DMC. The function gets the possible rate from OPP table based
+ * on requested frequency. It calls the next function responsible for the
+ * frequency and voltage change. In case of failure, does not set 'curr_rate'
+ * and returns error value to the framework.
+ */
+static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
+			      u32 flags)
+{
+	struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+	unsigned long target_rate = 0;
+	unsigned long target_volt = 0;
+	int ret;
+
+	ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
+					flags);
+
+	if (ret)
+		return ret;
+
+	if (target_rate == dmc->curr_rate)
+		return 0;
+
+	mutex_lock(&dmc->lock);
+
+	ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
+
+	if (ret) {
+		mutex_unlock(&dmc->lock);
+		return ret;
+	}
+
+	dmc->curr_rate = target_rate;
+
+	mutex_unlock(&dmc->lock);
+	return 0;
+}
+
+/**
+ * exynos5_counters_get() - Gets the performance counters values.
+ * @dmc:	device for which the counters are going to be checked
+ * @load_count:	variable which is populated with counter value
+ * @total_count:	variable which is used as 'wall clock' reference
+ *
+ * Function which provides performance counters values. It sums up counters for
+ * two DMC channels. The 'total_count' is used as a reference and max value.
+ * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
+ */
+static int exynos5_counters_get(struct exynos5_dmc *dmc,
+				unsigned long *load_count,
+				unsigned long *total_count)
+{
+	unsigned long total = 0;
+	struct devfreq_event_data event;
+	int ret, i;
+
+	*load_count = 0;
+
+	/* Take into account only read+write counters, but stop all */
+	for (i = 0; i < dmc->num_counters; i++) {
+		if (!dmc->counter[i])
+			continue;
+
+		ret = devfreq_event_get_event(dmc->counter[i], &event);
+		if (ret < 0)
+			return ret;
+
+		*load_count += event.load_count;
+
+		if (total < event.total_count)
+			total = event.total_count;
+	}
+
+	*total_count = total;
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_get_status() - Read current DMC performance statistics.
+ * @dev:	device for which the statistics are requested
+ * @stat:	structure which has statistic fields
+ *
+ * Function reads the DMC performance counters and calculates 'busy_time'
+ * and 'total_time'. To protect from overflow, the values are shifted right
+ * by 10. After read out the counters are setup to count again.
+ */
+static int exynos5_dmc_get_status(struct device *dev,
+				  struct devfreq_dev_status *stat)
+{
+	struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+	unsigned long load, total;
+	int ret;
+
+	ret = exynos5_counters_get(dmc, &load, &total);
+	if (ret < 0)
+		return -EINVAL;
+
+	/* To protect from overflow in calculation ratios, divide by 1024 */
+	stat->busy_time = load >> 10;
+	stat->total_time = total >> 10;
+
+	ret = exynos5_counters_set_event(dmc);
+	if (ret < 0) {
+		dev_err(dev, "could not set event counter\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
+ * @dev:	device for which the framework checks operating frequency
+ * @freq:	returned frequency value
+ *
+ * It returns the currently used frequency of the DMC. The real operating
+ * frequency might be lower when the clock source value could not be divided
+ * to the requested value.
+ */
+static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+	struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+
+	mutex_lock(&dmc->lock);
+	*freq = dmc->curr_rate;
+	mutex_unlock(&dmc->lock);
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_df_profile - Devfreq governor's profile structure
+ *
+ * It provides to the devfreq framework needed functions and polling period.
+ */
+static struct devfreq_dev_profile exynos5_dmc_df_profile = {
+	.polling_ms = 500,
+	.target = exynos5_dmc_target,
+	.get_dev_status = exynos5_dmc_get_status,
+	.get_cur_freq = exynos5_dmc_get_cur_freq,
+};
+
+/**
+ * exynos5_dmc_align_initial_frequency() - Align initial frequency value
+ * @dmc:	device for which the frequency is going to be set
+ * @bootloader_init_freq:	initial frequency set by the bootloader in KHz
+ *
+ * The initial bootloader frequency, which is present during boot, might be
+ * different that supported frequency values in the driver. It is possible
+ * due to different PLL settings or used PLL as a source.
+ * This function provides the 'initial_freq' for the devfreq framework
+ * statistics engine which supports only registered values. Thus, some alignment
+ * must be made.
+ */
+unsigned long
+exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
+			    unsigned long bootloader_init_freq)
+{
+	unsigned long aligned_freq;
+	int idx;
+
+	idx = find_target_freq_idx(dmc, bootloader_init_freq);
+	if (idx >= 0)
+		aligned_freq = dmc->opp[idx].freq_hz;
+	else
+		aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
+
+	return aligned_freq;
+}
+
+/**
+ * create_timings_aligned() - Create register values and align with standard
+ * @dmc:	device for which the frequency is going to be set
+ * @idx:	speed bin in the OPP table
+ * @clk_period_ps:	the period of the clock, known as tCK
+ *
+ * The function calculates timings and creates a register value ready for
+ * a frequency transition. The register contains a few timings. They are
+ * shifted by a known offset. The timing value is calculated based on memory
+ * specyfication: minimal time required and minimal cycles required.
+ */
+static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
+				  u32 *reg_timing_data, u32 *reg_timing_power,
+				  u32 clk_period_ps)
+{
+	u32 val;
+	const struct timing_reg *reg;
+
+	if (clk_period_ps == 0)
+		return -EINVAL;
+
+	*reg_timing_row = 0;
+	*reg_timing_data = 0;
+	*reg_timing_power = 0;
+
+	val = dmc->timings->tRFC / clk_period_ps;
+	val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRFC);
+	reg = &timing_row[0];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRRD / clk_period_ps;
+	val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRRD);
+	reg = &timing_row[1];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRPab / clk_period_ps;
+	val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRPab);
+	reg = &timing_row[2];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRCD / clk_period_ps;
+	val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRCD);
+	reg = &timing_row[3];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRC / clk_period_ps;
+	val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRC);
+	reg = &timing_row[4];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRAS / clk_period_ps;
+	val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRAS);
+	reg = &timing_row[5];
+	*reg_timing_row |= TIMING_VAL2REG(reg, val);
+
+	/* data related timings */
+	val = dmc->timings->tWTR / clk_period_ps;
+	val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tWTR);
+	reg = &timing_data[0];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tWR / clk_period_ps;
+	val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tWR);
+	reg = &timing_data[1];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRTP / clk_period_ps;
+	val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRTP);
+	reg = &timing_data[2];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tW2W_C2C / clk_period_ps;
+	val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tW2W_C2C);
+	reg = &timing_data[3];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tR2R_C2C / clk_period_ps;
+	val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tR2R_C2C);
+	reg = &timing_data[4];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tWL / clk_period_ps;
+	val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tWL);
+	reg = &timing_data[5];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tDQSCK / clk_period_ps;
+	val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tDQSCK);
+	reg = &timing_data[6];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tRL / clk_period_ps;
+	val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tRL);
+	reg = &timing_data[7];
+	*reg_timing_data |= TIMING_VAL2REG(reg, val);
+
+	/* power related timings */
+	val = dmc->timings->tFAW / clk_period_ps;
+	val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tXP);
+	reg = &timing_power[0];
+	*reg_timing_power |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tXSR / clk_period_ps;
+	val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tXSR);
+	reg = &timing_power[1];
+	*reg_timing_power |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tXP / clk_period_ps;
+	val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tXP);
+	reg = &timing_power[2];
+	*reg_timing_power |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tCKE / clk_period_ps;
+	val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tCKE);
+	reg = &timing_power[3];
+	*reg_timing_power |= TIMING_VAL2REG(reg, val);
+
+	val = dmc->timings->tMRD / clk_period_ps;
+	val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
+	val = max(val, dmc->min_tck->tMRD);
+	reg = &timing_power[4];
+	*reg_timing_power |= TIMING_VAL2REG(reg, val);
+
+	return 0;
+}
+
+/**
+ * of_get_dram_timings() - helper function for parsing DT settings for DRAM
+ * @dmc:        device for which the frequency is going to be set
+ *
+ * The function parses DT entries with DRAM information.
+ */
+static int of_get_dram_timings(struct exynos5_dmc *dmc)
+{
+	int ret = 0;
+	int idx;
+	struct device_node *np_ddr;
+	u32 freq_mhz, clk_period_ps;
+
+	np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
+	if (!np_ddr) {
+		dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
+		return -EINVAL;
+	}
+
+	dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
+					     sizeof(u32), GFP_KERNEL);
+	if (!dmc->timing_row)
+		return -ENOMEM;
+
+	dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
+					      sizeof(u32), GFP_KERNEL);
+	if (!dmc->timing_data)
+		return -ENOMEM;
+
+	dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
+					       sizeof(u32), GFP_KERNEL);
+	if (!dmc->timing_power)
+		return -ENOMEM;
+
+	dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
+						 DDR_TYPE_LPDDR3,
+						 &dmc->timings_arr_size);
+	if (!dmc->timings) {
+		of_node_put(np_ddr);
+		dev_warn(dmc->dev, "could not get timings from DT\n");
+		return -EINVAL;
+	}
+
+	dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
+	if (!dmc->min_tck) {
+		of_node_put(np_ddr);
+		dev_warn(dmc->dev, "could not get tck from DT\n");
+		return -EINVAL;
+	}
+
+	/* Sorted array of OPPs with frequency ascending */
+	for (idx = 0; idx < dmc->opp_count; idx++) {
+		freq_mhz = dmc->opp[idx].freq_hz / 1000000;
+		clk_period_ps = 1000000 / freq_mhz;
+
+		ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
+					     &dmc->timing_data[idx],
+					     &dmc->timing_power[idx],
+					     clk_period_ps);
+	}
+
+	of_node_put(np_ddr);
+
+	/* Take the highest frequency's timings as 'bypass' */
+	dmc->bypass_timing_row = dmc->timing_row[idx - 1];
+	dmc->bypass_timing_data = dmc->timing_data[idx - 1];
+	dmc->bypass_timing_power = dmc->timing_power[idx - 1];
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
+ * @dmc:	DMC structure containing needed fields
+ *
+ * Get the needed clocks defined in DT device, enable and set the right parents.
+ * Read current frequency and initialize the initial rate for governor.
+ */
+static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
+{
+	int ret;
+	unsigned long target_volt = 0;
+	unsigned long target_rate = 0;
+
+	dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
+	if (IS_ERR(dmc->fout_spll))
+		return PTR_ERR(dmc->fout_spll);
+
+	dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
+	if (IS_ERR(dmc->fout_bpll))
+		return PTR_ERR(dmc->fout_bpll);
+
+	dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
+	if (IS_ERR(dmc->mout_mclk_cdrex))
+		return PTR_ERR(dmc->mout_mclk_cdrex);
+
+	dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
+	if (IS_ERR(dmc->mout_bpll))
+		return PTR_ERR(dmc->mout_bpll);
+
+	dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
+						"mout_mx_mspll_ccore");
+	if (IS_ERR(dmc->mout_mx_mspll_ccore))
+		return PTR_ERR(dmc->mout_mx_mspll_ccore);
+
+	dmc->dout_clk2x_phy0 = devm_clk_get(dmc->dev, "dout_clk2x_phy0");
+	if (IS_ERR(dmc->dout_clk2x_phy0))
+		return PTR_ERR(dmc->dout_clk2x_phy0);
+
+	dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
+	if (IS_ERR(dmc->mout_spll)) {
+		dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
+		if (IS_ERR(dmc->mout_spll))
+			return PTR_ERR(dmc->mout_spll);
+	}
+
+	/*
+	 * Convert frequency to KHz values and set it for the governor.
+	 */
+	dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
+	dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
+	exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
+
+	ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
+					&target_volt, 0);
+	if (ret)
+		return ret;
+
+	dmc->curr_volt = target_volt;
+
+	clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
+
+	dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
+
+	clk_prepare_enable(dmc->fout_bpll);
+	clk_prepare_enable(dmc->mout_bpll);
+
+	return 0;
+}
+
+/**
+ * exynos5_performance_counters_init() - Initializes performance DMC's counters
+ * @dmc:	DMC for which it does the setup
+ *
+ * Initialization of performance counters in DMC for estimating usage.
+ * The counter's values are used for calculation of a memory bandwidth and based
+ * on that the governor changes the frequency.
+ * The counters are not used when the governor is GOVERNOR_USERSPACE.
+ */
+static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
+{
+	int counters_size;
+	int ret, i;
+
+	dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
+	if (dmc->num_counters < 0) {
+		dev_err(dmc->dev, "could not get devfreq-event counters\n");
+		return dmc->num_counters;
+	}
+
+	counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
+	dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
+	if (!dmc->counter)
+		return -ENOMEM;
+
+	for (i = 0; i < dmc->num_counters; i++) {
+		dmc->counter[i] =
+			devfreq_event_get_edev_by_phandle(dmc->dev, i);
+		if (IS_ERR_OR_NULL(dmc->counter[i]))
+			return -EPROBE_DEFER;
+	}
+
+	ret = exynos5_counters_enable_edev(dmc);
+	if (ret < 0) {
+		dev_err(dmc->dev, "could not enable event counter\n");
+		return ret;
+	}
+
+	ret = exynos5_counters_set_event(dmc);
+	if (ret < 0) {
+		dev_err(dmc->dev, "counld not set event counter\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
+ * @dmc:	device which is used for changing this feature
+ * @set:	a boolean state passing enable/disable request
+ *
+ * There is a need of pausing DREX DMC when divider or MUX in clock tree
+ * changes its configuration. In such situation access to the memory is blocked
+ * in DMC automatically. This feature is used when clock frequency change
+ * request appears and touches clock tree.
+ */
+static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
+{
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
+	if (ret)
+		return ret;
+
+	val |= 1UL;
+	regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
+
+	return 0;
+}
+
+/**
+ * exynos5_dmc_probe() - Probe function for the DMC driver
+ * @pdev:	platform device for which the driver is going to be initialized
+ *
+ * Initialize basic components: clocks, regulators, performance counters, etc.
+ * Read out product version and based on the information setup
+ * internal structures for the controller (frequency and voltage) and for DRAM
+ * memory parameters: timings for each operating frequency.
+ * Register new devfreq device for controlling DVFS of the DMC.
+ */
+static int exynos5_dmc_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct exynos5_dmc *dmc;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct resource *res;
+
+	dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
+	if (!dmc)
+		return -ENOMEM;
+
+	mutex_init(&dmc->lock);
+
+	dmc->dev = dev;
+	platform_set_drvdata(pdev, dmc);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dmc->base_drexi0 = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dmc->base_drexi0))
+		return PTR_ERR(dmc->base_drexi0);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	dmc->base_drexi1 = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dmc->base_drexi1))
+		return PTR_ERR(dmc->base_drexi1);
+
+	dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
+				"samsung,syscon-clk");
+	if (IS_ERR(dmc->clk_regmap))
+		return PTR_ERR(dmc->clk_regmap);
+
+	ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
+	if (ret) {
+		dev_warn(dev, "couldn't initialize frequency settings\n");
+		return ret;
+	}
+
+	dmc->vdd_mif = devm_regulator_get(dev, "vdd");
+	if (IS_ERR(dmc->vdd_mif)) {
+		ret = PTR_ERR(dmc->vdd_mif);
+		return ret;
+	}
+
+	ret = exynos5_dmc_init_clks(dmc);
+	if (ret)
+		return ret;
+
+	ret = of_get_dram_timings(dmc);
+	if (ret) {
+		dev_warn(dev, "couldn't initialize timings settings\n");
+		return ret;
+	}
+
+	ret = exynos5_performance_counters_init(dmc);
+	if (ret) {
+		dev_warn(dev, "couldn't probe performance counters\n");
+		goto remove_clocks;
+	}
+
+	ret = exynos5_dmc_set_pause_on_switching(dmc);
+	if (ret) {
+		dev_warn(dev, "couldn't get access to PAUSE register\n");
+		goto remove_clocks;
+	}
+
+	/*
+	 * Setup default thresholds for the devfreq governor.
+	 * The values are chosen based on experiments.
+	 */
+	dmc->gov_data.upthreshold = 30;
+	dmc->gov_data.downdifferential = 5;
+
+	dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
+					  DEVFREQ_GOV_USERSPACE,
+					  &dmc->gov_data);
+
+	if (IS_ERR(dmc->df)) {
+		ret = PTR_ERR(dmc->df);
+		goto err_devfreq_add;
+	}
+
+	dev_info(dev, "DMC initialized\n");
+
+	return 0;
+
+err_devfreq_add:
+	exynos5_counters_disable_edev(dmc);
+remove_clocks:
+	clk_disable_unprepare(dmc->mout_spll);
+	clk_disable_unprepare(dmc->fout_spll);
+
+	return ret;
+}
+
+/**
+ * exynos5_dmc_remove() - Remove function for the platform device
+ * @pdev:	platform device which is going to be removed
+ *
+ * The function relies on 'devm' framework function which automatically
+ * clean the device's resources. It just calls explicitly disable function for
+ * the performance counters.
+ */
+static int exynos5_dmc_remove(struct platform_device *pdev)
+{
+	struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
+
+	exynos5_counters_disable_edev(dmc);
+
+	clk_disable_unprepare(dmc->mout_bpll);
+	clk_disable_unprepare(dmc->fout_bpll);
+
+	dev_pm_opp_remove_table(dmc->dev);
+
+	return 0;
+}
+
+static const struct of_device_id exynos5_dmc_of_match[] = {
+	{ .compatible = "samsung,exynos5422-dmc", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
+
+static struct platform_driver exynos5_dmc_platdrv = {
+	.probe	= exynos5_dmc_probe,
+	.remove = exynos5_dmc_remove,
+	.driver = {
+		.name	= "exynos5-dmc",
+		.of_match_table = exynos5_dmc_of_match,
+	},
+};
+module_platform_driver(exynos5_dmc_platdrv);
+MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Samsung");
-- 
2.17.1

Re: [PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422

[Krzysztof Kozlowski]

On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> This patch adds driver for Exynos5422 Dynamic Memory Controller.
> The driver provides support for dynamic frequency and voltage scaling for
> DMC and DRAM. It supports changing timings of DRAM running with different
> frequency. There is also an algorithm to calculate timigns based on
> memory description provided in DT.
> The patch also contains needed MAINTAINERS file update.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  MAINTAINERS                             |    8 +
>  drivers/memory/samsung/Kconfig          |   17 +
>  drivers/memory/samsung/Makefile         |    1 +
>  drivers/memory/samsung/exynos5422-dmc.c | 1265 +++++++++++++++++++++++
>  4 files changed, 1291 insertions(+)
>  create mode 100644 drivers/memory/samsung/exynos5422-dmc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a6954776a37e..d57cf4be1e51 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3470,6 +3470,14 @@ S:       Maintained
>  F:     drivers/devfreq/exynos-bus.c
>  F:     Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>
> +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
> +M:     Lukasz Luba <l.luba@partner.samsung.com>
> +L:     linux-pm@vger.kernel.org
> +L:     linux-samsung-soc@vger.kernel.org
> +S:     Maintained
> +F:     drivers/memory/samsung/exynos5422-dmc.c
> +F:     Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> +
>  BUSLOGIC SCSI DRIVER
>  M:     Khalid Aziz <khalid@gonehiking.org>
>  L:     linux-scsi@vger.kernel.org
> diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig
> index 79ce7ea58903..c93baa029654 100644
> --- a/drivers/memory/samsung/Kconfig
> +++ b/drivers/memory/samsung/Kconfig
> @@ -5,6 +5,23 @@ config SAMSUNG_MC
>           Support for the Memory Controller (MC) devices found on
>           Samsung Exynos SoCs.
>
> +config ARM_EXYNOS5422_DMC
> +       tristate "ARM EXYNOS5422 Dynamic Memory Controller driver"
> +       depends on ARCH_EXYNOS
> +       select DDR
> +       select PM_DEVFREQ
> +       select DEVFREQ_GOV_SIMPLE_ONDEMAND
> +       select DEVFREQ_GOV_USERSPACE
> +       select PM_DEVFREQ_EVENT
> +       select PM_OPP
> +       help
> +         This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
> +         The driver provides support for Dynamic Voltage and Frequency Scaling in
> +         DMC and DRAM. It also supports changing timings of DRAM running with
> +         different frequency. The timings are calculated based on DT memory
> +         information.
> +
> +
>  if SAMSUNG_MC
>
>  config EXYNOS_SROM
> diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile
> index 00587be66211..4f6e4383bab7 100644
> --- a/drivers/memory/samsung/Makefile
> +++ b/drivers/memory/samsung/Makefile
> @@ -1,2 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0
> +obj-$(CONFIG_ARM_EXYNOS5422_DMC)       += exynos5422-dmc.o
>  obj-$(CONFIG_EXYNOS_SROM)      += exynos-srom.o
> diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
> new file mode 100644
> index 000000000000..6fca9e4c45ff
> --- /dev/null
> +++ b/drivers/memory/samsung/exynos5422-dmc.c
> @@ -0,0 +1,1265 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + * Author: Lukasz Luba <l.luba@partner.samsung.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/devfreq.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +#include <memory/jedec_ddr.h>
> +#include "../of_memory.h"
> +
> +#define EXYNOS5_DREXI_TIMINGAREF               (0x0030)
> +#define EXYNOS5_DREXI_TIMINGROW0               (0x0034)
> +#define EXYNOS5_DREXI_TIMINGDATA0              (0x0038)
> +#define EXYNOS5_DREXI_TIMINGPOWER0             (0x003C)
> +#define EXYNOS5_DREXI_TIMINGROW1               (0x00E4)
> +#define EXYNOS5_DREXI_TIMINGDATA1              (0x00E8)
> +#define EXYNOS5_DREXI_TIMINGPOWER1             (0x00EC)
> +#define CDREX_PAUSE                            (0x2091c)
> +#define CDREX_LPDDR3PHY_CON3                   (0x20a20)
> +#define EXYNOS5_TIMING_SET_SWI                  (1UL << 28)

You have mixed indentation here (spaces instead of tabs).

> +#define USE_MX_MSPLL_TIMINGS                   (1)
> +#define USE_BPLL_TIMINGS                       (0)
> +#define EXYNOS5_AREF_NORMAL                    (0x2e)
> +
> +/**
> + * struct dmc_opp_table - Operating level desciption
> + *
> + * Covers frequency and voltage settings of the DMC operating mode.
> + */
> +struct dmc_opp_table {
> +       u32 freq_hz;
> +       u32 volt_uv;
> +};
> +
> +/**
> + * struct exynos5_dmc - main structure describing DMC device
> + *
> + * The main structure for the Dynamic Memory Controller which covers clocks,
> + * memory regions, HW information, parameters and current operating mode.
> + */
> +struct exynos5_dmc {
> +       struct device *dev;
> +       struct devfreq *df;
> +       struct devfreq_simple_ondemand_data gov_data;
> +       void __iomem *base_drexi0;
> +       void __iomem *base_drexi1;
> +       struct regmap *clk_regmap;
> +       struct mutex lock;
> +       unsigned long curr_rate;
> +       unsigned long curr_volt;
> +       unsigned long bypass_rate;
> +       struct dmc_opp_table *opp;
> +       struct dmc_opp_table opp_bypass;
> +       int opp_count;
> +       u32 timings_arr_size;
> +       u32 *timing_row;
> +       u32 *timing_data;
> +       u32 *timing_power;
> +       const struct lpddr3_timings *timings;
> +       const struct lpddr3_min_tck *min_tck;
> +       u32 bypass_timing_row;
> +       u32 bypass_timing_data;
> +       u32 bypass_timing_power;
> +       struct regulator *vdd_mif;
> +       struct clk *fout_spll;
> +       struct clk *fout_bpll;
> +       struct clk *mout_spll;
> +       struct clk *mout_bpll;
> +       struct clk *mout_mclk_cdrex;
> +       struct clk *dout_clk2x_phy0;
> +       struct clk *mout_mx_mspll_ccore;
> +       struct clk *mx_mspll_ccore_phy;
> +       struct clk *mout_mx_mspll_ccore_phy;
> +       struct devfreq_event_dev **counter;
> +       int num_counters;
> +};
> +
> +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
> +       { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
> +
> +#define TIMING_VAL(timing_array, id, t_val)                    \
> +({                                                             \
> +               u32 __val;                              \
> +               __val = t_val << timing_array[id].bit_beg;      \
> +               __val;                                          \
> +})
> +
> +#define TIMING_VAL2REG(timing, t_val)                  \
> +({                                                             \
> +               u32 __val;                              \
> +               __val = t_val << timing->bit_beg;       \
> +               __val;                                          \
> +})
> +
> +#define TIMING_REG2VAL(reg, timing)                    \
> +({                                                             \
> +               u32 __val;                              \
> +               reg <<= (31 - timing->bit_end);         \
> +               reg >>= (31 - timing->bit_end);         \
> +               __val = reg >> timing->bit_beg; \
> +               __val;                                          \
> +})
> +
> +struct timing_reg {
> +       char *name;
> +       int bit_beg;
> +       int bit_end;
> +       unsigned int val;
> +};
> +
> +static const struct timing_reg timing_row[] = {
> +       TIMING_FIELD("tRFC", 24, 31),
> +       TIMING_FIELD("tRRD", 20, 23),
> +       TIMING_FIELD("tRP", 16, 19),
> +       TIMING_FIELD("tRCD", 12, 15),
> +       TIMING_FIELD("tRC", 6, 11),
> +       TIMING_FIELD("tRAS", 0, 5),
> +};
> +
> +static const struct timing_reg timing_data[] = {
> +       TIMING_FIELD("tWTR", 28, 31),
> +       TIMING_FIELD("tWR", 24, 27),
> +       TIMING_FIELD("tRTP", 20, 23),
> +       TIMING_FIELD("tW2W-C2C", 14, 14),
> +       TIMING_FIELD("tR2R-C2C", 12, 12),
> +       TIMING_FIELD("WL", 8, 11),
> +       TIMING_FIELD("tDQSCK", 4, 7),
> +       TIMING_FIELD("RL", 0, 3),
> +};
> +
> +static const struct timing_reg timing_power[] = {
> +       TIMING_FIELD("tFAW", 26, 31),
> +       TIMING_FIELD("tXSR", 16, 25),
> +       TIMING_FIELD("tXP", 8, 15),
> +       TIMING_FIELD("tCKE", 4, 7),
> +       TIMING_FIELD("tMRD", 0, 3),
> +};
> +
> +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
> +                     ARRAY_SIZE(timing_power))
> +
> +static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
> +{
> +       int i, ret;
> +
> +       for (i = 0; i < dmc->num_counters; i++) {
> +               if (!dmc->counter[i])
> +                       continue;
> +               ret = devfreq_event_set_event(dmc->counter[i]);
> +               if (ret < 0)
> +                       return ret;
> +       }
> +       return 0;
> +}
> +
> +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
> +{
> +       int i, ret;
> +
> +       for (i = 0; i < dmc->num_counters; i++) {
> +               if (!dmc->counter[i])
> +                       continue;
> +               ret = devfreq_event_enable_edev(dmc->counter[i]);
> +               if (ret < 0)
> +                       return ret;
> +       }
> +       return 0;
> +}
> +
> +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
> +{
> +       int i, ret;
> +
> +       for (i = 0; i < dmc->num_counters; i++) {
> +               if (!dmc->counter[i])
> +                       continue;
> +               ret = devfreq_event_disable_edev(dmc->counter[i]);
> +               if (ret < 0)
> +                       return ret;
> +       }
> +       return 0;
> +}
> +
> +/**
> + * find_target_freq_id() - Finds requested frequency in local DMC configuration
> + * @dmc:       device for which the information is checked
> + * @target_rate:       requested frequency in KHz
> + *
> + * Seeks in the local DMC driver structure for the requested frequency value
> + * and returns index or error value.
> + */
> +static int find_target_freq_idx(struct exynos5_dmc *dmc,
> +                               unsigned long target_rate)
> +{
> +       int i;
> +
> +       for (i = dmc->opp_count - 1; i >= 0; i--)
> +               if (dmc->opp[i].freq_hz <= target_rate)
> +                       return i;
> +
> +       return -EINVAL;
> +}
> +
> +/**
> + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
> + * @dmc:       device for which the new settings is going to be applied
> + * @set:       boolean variable passing set value
> + *
> + * Changes the register set, which holds timing parameters.
> + * There is two register sets: 0 and 1. The register set 0
> + * is used in normal operation when the clock is provided from main PLL.
> + * The bank register set 1 is used when the main PLL frequency is going to be
> + * changed and the clock is taken from alternative, stable source.
> + * This function switches between these banks according to the
> + * currently used clock source.
> + */
> +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
> +{
> +       unsigned int reg;
> +       int ret;
> +
> +       ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg);
> +
> +       if (set)
> +               reg |= EXYNOS5_TIMING_SET_SWI;
> +       else
> +               reg &= ~EXYNOS5_TIMING_SET_SWI;
> +
> +       regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
> +}
> +
> +/**
> + * exynos5_init_freq_table() - Initialized PM OPP framework
> + * @dmc:       DMC device for which the frequencies are used for OPP init
> + * @profile:   devfreq device's profile
> + *
> + * Populate the devfreq device's OPP table based on current frequency, voltage.
> + */
> +static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
> +                                  struct devfreq_dev_profile *profile)
> +{
> +       int i, ret;
> +       int idx;
> +       unsigned long freq;
> +
> +       ret = dev_pm_opp_of_add_table(dmc->dev);
> +       if (ret < 0) {
> +               dev_err(dmc->dev, "Failed to get OPP table\n");
> +               return ret;
> +       }
> +
> +       dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
> +
> +       dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
> +                                     sizeof(struct dmc_opp_table), GFP_KERNEL);
> +       if (!dmc->opp)
> +               goto err_opp;
> +
> +       idx = dmc->opp_count - 1;
> +       for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
> +               struct dev_pm_opp *opp;
> +
> +               opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
> +               if (IS_ERR(opp))
> +                       goto err_free_tables;
> +
> +               dmc->opp[idx - i].freq_hz = freq;
> +               dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
> +
> +               dev_pm_opp_put(opp);
> +       }
> +
> +       return 0;
> +
> +err_free_tables:
> +       kfree(dmc->opp);
> +err_opp:
> +       dev_pm_opp_of_remove_table(dmc->dev);
> +
> +       return -EINVAL;
> +}
> +
> +/**
> + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
> + * @dmc:       device for which the new settings is going to be applied
> + * @param:     DRAM parameters which passes timing data
> + *
> + * Low-level function for changing timings for DRAM memory clocking from
> + * 'bypass' clock source (fixed frequency @400MHz).
> + * It uses timing bank registers set 1.
> + */
> +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
> +{
> +       writel(EXYNOS5_AREF_NORMAL,
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
> +
> +       writel(dmc->bypass_timing_row,
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
> +       writel(dmc->bypass_timing_row,
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
> +       writel(dmc->bypass_timing_data,
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
> +       writel(dmc->bypass_timing_data,
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
> +       writel(dmc->bypass_timing_power,
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
> +       writel(dmc->bypass_timing_power,
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
> +}
> +
> +/**
> + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
> + * @dmc:       device for which the new settings is going to be applied
> + * @target_rate:       target frequency of the DMC
> + *
> + * Low-level function for changing timings for DRAM memory operating from main
> + * clock source (BPLL), which can have different frequencies. Thus, each
> + * frequency must have corresponding timings register values in order to keep
> + * the needed delays.
> + * It uses timing bank registers set 0.
> + */
> +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
> +                                      unsigned long target_rate)
> +{
> +       int idx;
> +
> +       for (idx = dmc->opp_count - 1; idx >= 0; idx--)
> +               if (dmc->opp[idx].freq_hz <= target_rate)
> +                       break;
> +
> +       if (idx < 0)
> +               return -EINVAL;
> +
> +       writel(EXYNOS5_AREF_NORMAL,
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
> +
> +       writel(dmc->timing_row[idx],
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
> +       writel(dmc->timing_row[idx],
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
> +       writel(dmc->timing_data[idx],
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
> +       writel(dmc->timing_data[idx],
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
> +       writel(dmc->timing_power[idx],
> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
> +       writel(dmc->timing_power[idx],
> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
> + * @dmc:       device for which it is going to be set
> + * @target_volt:       new voltage which is chosen to be final
> + *
> + * Function tries to align voltage to the safe level for 'normal' mode.
> + * It checks the need of higher voltage and changes the value. The target
> + * voltage might be lower that currently set and still the system will be
> + * stable.
> + */
> +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
> +                                           unsigned long target_volt)
> +{
> +       int ret = 0;
> +
> +       if (dmc->curr_volt > target_volt) {

A nit: I would prefer to use the same style as in
exynos5_dmc_align_bypass_voltage(), so "return 0" after "if", to have
consistent pattern easily understand which function bumps and which
lowers the voltage.


> +               ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
> +                                           target_volt);
> +               if (!ret)
> +                       dmc->curr_volt = target_volt;
> +       }
> +
> +       return ret;
> +}
> +
> +/**
> + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
> + * @dmc:       device for which it is going to be set
> + * @target_volt:       new voltage which is chosen to be final
> + *
> + * Function tries to align voltage to the safe level for the 'bypass' mode.
> + * It checks the need of higher voltage and changes the value.
> + * The target voltage must not be less than currently needed, because
> + * for current frequency the device might become unstable.
> + */
> +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
> +                                           unsigned long target_volt)
> +{
> +       int ret = 0;
> +       unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
> +
> +       target_volt = max(bypass_volt, target_volt);
> +
> +       if (dmc->curr_volt >= target_volt)
> +               return 0;
> +
> +       ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
> +                                   target_volt);
> +       if (!ret)
> +               dmc->curr_volt = target_volt;
> +
> +       return ret;
> +}
> +
> +/**
> + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
> + * @dmc:       device for which it is going to be set
> + * @target_rate:       new frequency which is chosen to be final
> + *
> + * Function changes the DRAM timings for the temporary 'bypass' mode.
> + */
> +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
> +                                                unsigned long target_rate)
> +{
> +       int idx = find_target_freq_idx(dmc, target_rate);
> +
> +       if (idx < 0)
> +               return -EINVAL;
> +
> +       exynos5_set_bypass_dram_timings(dmc);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
> + * @dmc:       DMC device for which the switching is going to happen
> + * @target_rate:       new frequency which is going to be set as a final
> + * @target_volt:       new voltage which is going to be set as a final
> + *
> + * Function configures DMC and clocks for operating in temporary 'bypass' mode.
> + * This mode is used only temporary but if required, changes voltage and timings
> + * for DRAM chips. It switches the main clock to stable clock source for the
> + * period of the main PLL reconfiguration.
> + */
> +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
> +                                  unsigned long target_rate,
> +                                  unsigned long target_volt)
> +{
> +       int ret;
> +
> +       /*
> +        * Having higher voltage for a particular frequency does not harm
> +        * the chip. Use it for the temporary frequency change when one
> +        * voltage manipulation might be avoided.
> +        */
> +       ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * Longer delays for DRAM does not cause crash, the opposite does.
> +        */
> +       ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * Delays are long enough, so use them for the new coming clock.
> +        */
> +       exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
> +
> +       return ret;
> +}
> +
> +/**
> + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
> + * using safe procedure
> + * @dmc:       device for which the frequency is going to be changed
> + * @target_rate:       requested new frequency
> + * @target_volt:       requested voltage which corresponds to the new frequency
> + *
> + * The DMC frequency change procedure requires a few steps.
> + * The main requirement is to change the clock source in the clk mux
> + * for the time of main clock PLL locking. The assumption is that the
> + * alternative clock source set as parent is stable.
> + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
> + * clock. This requires alignment in DRAM timing parameters for the new
> + * T-period. There is two bank sets for keeping DRAM
> + * timings: set 0 and set 1. The set 0 is used when main clock source is
> + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
> + * the two bank sets is part of the process.
> + * The voltage must also be aligned to the minimum required level. There is
> + * this intermediate step with switching to 'bypass' parent clock source.
> + * if the old voltage is lower, it requires an increase of the voltage level.
> + * The complexity of the voltage manipulation is hidden in low level function.
> + * In this function there is last alignment of the voltage level at the end.
> + */
> +static int
> +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
> +                                unsigned long target_rate,
> +                                unsigned long target_volt)
> +{
> +       int ret;
> +
> +       ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
> +                                                        target_volt);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * Voltage is set at least to a level needed for this frequency,
> +        * so switching clock source is safe now.
> +        */
> +       clk_prepare_enable(dmc->fout_spll);
> +       clk_prepare_enable(dmc->mout_spll);
> +       clk_prepare_enable(dmc->mout_mx_mspll_ccore);
> +
> +       ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
> +       if (ret)

What about error path and disabling clocks?

> +               return ret;
> +
> +       /*
> +        * We are safe to increase the timings for current bypass frequency.
> +        * Thanks to this the settings we be ready for the upcoming clock source
> +        * change.
> +        */
> +       exynos5_dram_change_timings(dmc, target_rate);
> +
> +       clk_set_rate(dmc->fout_bpll, target_rate);
> +
> +       exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
> +
> +       ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
> +       if (ret)

Ditto.

> +               return ret;
> +
> +       clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
> +       clk_disable_unprepare(dmc->mout_spll);
> +       clk_disable_unprepare(dmc->fout_spll);
> +
> +       /*
> +        * Make sure if the voltage is not from 'bypass' settings and align to
> +        * the right level for power efficiency.
> +        */
> +       ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
> +
> +       return ret;
> +}
> +
> +/**
> + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
> + * table.
> + * @dmc:       device for which the frequency is going to be changed
> + * @freq:       requested frequency in KHz
> + * @target_rate:       returned frequency which is the same or lower than
> + *                     requested
> + * @target_volt:       returned voltage which corresponds to the returned
> + *                     frequency
> + *
> + * Function gets requested frequency and checks OPP framework for needed
> + * frequency and voltage. It populates the values 'target_rate' and
> + * 'target_volt' or returns error value when OPP framework fails.
> + */
> +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
> +                                    unsigned long *freq,
> +                                    unsigned long *target_rate,
> +                                    unsigned long *target_volt, u32 flags)
> +{
> +       struct dev_pm_opp *opp;
> +
> +       opp = devfreq_recommended_opp(dmc->dev, freq, flags);
> +       if (IS_ERR(opp))
> +               return PTR_ERR(opp);
> +
> +       *target_rate = dev_pm_opp_get_freq(opp);
> +       *target_volt = dev_pm_opp_get_voltage(opp);
> +       dev_pm_opp_put(opp);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_target() - Function responsible for changing frequency of DMC
> + * @dev:       device for which the frequency is going to be changed
> + * @freq:      requested frequency in KHz
> + * @flags:     flags provided for this frequency change request
> + *
> + * An entry function provided to the devfreq framework which provides frequency
> + * change of the DMC. The function gets the possible rate from OPP table based
> + * on requested frequency. It calls the next function responsible for the
> + * frequency and voltage change. In case of failure, does not set 'curr_rate'
> + * and returns error value to the framework.
> + */
> +static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
> +                             u32 flags)
> +{
> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> +       unsigned long target_rate = 0;
> +       unsigned long target_volt = 0;
> +       int ret;
> +
> +       ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
> +                                       flags);
> +
> +       if (ret)
> +               return ret;
> +
> +       if (target_rate == dmc->curr_rate)
> +               return 0;
> +
> +       mutex_lock(&dmc->lock);
> +
> +       ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
> +
> +       if (ret) {
> +               mutex_unlock(&dmc->lock);
> +               return ret;
> +       }
> +
> +       dmc->curr_rate = target_rate;
> +
> +       mutex_unlock(&dmc->lock);
> +       return 0;
> +}
> +
> +/**
> + * exynos5_counters_get() - Gets the performance counters values.
> + * @dmc:       device for which the counters are going to be checked
> + * @load_count:        variable which is populated with counter value
> + * @total_count:       variable which is used as 'wall clock' reference
> + *
> + * Function which provides performance counters values. It sums up counters for
> + * two DMC channels. The 'total_count' is used as a reference and max value.
> + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
> + */
> +static int exynos5_counters_get(struct exynos5_dmc *dmc,
> +                               unsigned long *load_count,
> +                               unsigned long *total_count)
> +{
> +       unsigned long total = 0;
> +       struct devfreq_event_data event;
> +       int ret, i;
> +
> +       *load_count = 0;
> +
> +       /* Take into account only read+write counters, but stop all */
> +       for (i = 0; i < dmc->num_counters; i++) {
> +               if (!dmc->counter[i])
> +                       continue;
> +
> +               ret = devfreq_event_get_event(dmc->counter[i], &event);
> +               if (ret < 0)
> +                       return ret;
> +
> +               *load_count += event.load_count;
> +
> +               if (total < event.total_count)
> +                       total = event.total_count;
> +       }
> +
> +       *total_count = total;
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_get_status() - Read current DMC performance statistics.
> + * @dev:       device for which the statistics are requested
> + * @stat:      structure which has statistic fields
> + *
> + * Function reads the DMC performance counters and calculates 'busy_time'
> + * and 'total_time'. To protect from overflow, the values are shifted right
> + * by 10. After read out the counters are setup to count again.
> + */
> +static int exynos5_dmc_get_status(struct device *dev,
> +                                 struct devfreq_dev_status *stat)
> +{
> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> +       unsigned long load, total;
> +       int ret;
> +
> +       ret = exynos5_counters_get(dmc, &load, &total);
> +       if (ret < 0)
> +               return -EINVAL;
> +
> +       /* To protect from overflow in calculation ratios, divide by 1024 */
> +       stat->busy_time = load >> 10;
> +       stat->total_time = total >> 10;
> +
> +       ret = exynos5_counters_set_event(dmc);
> +       if (ret < 0) {
> +               dev_err(dev, "could not set event counter\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
> + * @dev:       device for which the framework checks operating frequency
> + * @freq:      returned frequency value
> + *
> + * It returns the currently used frequency of the DMC. The real operating
> + * frequency might be lower when the clock source value could not be divided
> + * to the requested value.
> + */
> +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
> +{
> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> +
> +       mutex_lock(&dmc->lock);
> +       *freq = dmc->curr_rate;
> +       mutex_unlock(&dmc->lock);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_df_profile - Devfreq governor's profile structure
> + *
> + * It provides to the devfreq framework needed functions and polling period.
> + */
> +static struct devfreq_dev_profile exynos5_dmc_df_profile = {
> +       .polling_ms = 500,
> +       .target = exynos5_dmc_target,
> +       .get_dev_status = exynos5_dmc_get_status,
> +       .get_cur_freq = exynos5_dmc_get_cur_freq,
> +};
> +
> +/**
> + * exynos5_dmc_align_initial_frequency() - Align initial frequency value
> + * @dmc:       device for which the frequency is going to be set
> + * @bootloader_init_freq:      initial frequency set by the bootloader in KHz
> + *
> + * The initial bootloader frequency, which is present during boot, might be
> + * different that supported frequency values in the driver. It is possible
> + * due to different PLL settings or used PLL as a source.
> + * This function provides the 'initial_freq' for the devfreq framework
> + * statistics engine which supports only registered values. Thus, some alignment
> + * must be made.
> + */
> +unsigned long
> +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
> +                           unsigned long bootloader_init_freq)
> +{
> +       unsigned long aligned_freq;
> +       int idx;
> +
> +       idx = find_target_freq_idx(dmc, bootloader_init_freq);
> +       if (idx >= 0)
> +               aligned_freq = dmc->opp[idx].freq_hz;
> +       else
> +               aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
> +
> +       return aligned_freq;
> +}
> +
> +/**
> + * create_timings_aligned() - Create register values and align with standard
> + * @dmc:       device for which the frequency is going to be set
> + * @idx:       speed bin in the OPP table
> + * @clk_period_ps:     the period of the clock, known as tCK
> + *
> + * The function calculates timings and creates a register value ready for
> + * a frequency transition. The register contains a few timings. They are
> + * shifted by a known offset. The timing value is calculated based on memory
> + * specyfication: minimal time required and minimal cycles required.
> + */
> +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
> +                                 u32 *reg_timing_data, u32 *reg_timing_power,
> +                                 u32 clk_period_ps)
> +{
> +       u32 val;
> +       const struct timing_reg *reg;
> +
> +       if (clk_period_ps == 0)
> +               return -EINVAL;
> +
> +       *reg_timing_row = 0;
> +       *reg_timing_data = 0;
> +       *reg_timing_power = 0;
> +
> +       val = dmc->timings->tRFC / clk_period_ps;
> +       val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRFC);
> +       reg = &timing_row[0];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRRD / clk_period_ps;
> +       val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRRD);
> +       reg = &timing_row[1];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRPab / clk_period_ps;
> +       val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRPab);
> +       reg = &timing_row[2];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRCD / clk_period_ps;
> +       val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRCD);
> +       reg = &timing_row[3];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRC / clk_period_ps;
> +       val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRC);
> +       reg = &timing_row[4];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRAS / clk_period_ps;
> +       val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRAS);
> +       reg = &timing_row[5];
> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
> +
> +       /* data related timings */
> +       val = dmc->timings->tWTR / clk_period_ps;
> +       val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tWTR);
> +       reg = &timing_data[0];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tWR / clk_period_ps;
> +       val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tWR);
> +       reg = &timing_data[1];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRTP / clk_period_ps;
> +       val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRTP);
> +       reg = &timing_data[2];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tW2W_C2C / clk_period_ps;
> +       val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tW2W_C2C);
> +       reg = &timing_data[3];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tR2R_C2C / clk_period_ps;
> +       val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tR2R_C2C);
> +       reg = &timing_data[4];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tWL / clk_period_ps;
> +       val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tWL);
> +       reg = &timing_data[5];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tDQSCK / clk_period_ps;
> +       val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tDQSCK);
> +       reg = &timing_data[6];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tRL / clk_period_ps;
> +       val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tRL);
> +       reg = &timing_data[7];
> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
> +
> +       /* power related timings */
> +       val = dmc->timings->tFAW / clk_period_ps;
> +       val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tXP);
> +       reg = &timing_power[0];
> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tXSR / clk_period_ps;
> +       val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tXSR);
> +       reg = &timing_power[1];
> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tXP / clk_period_ps;
> +       val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tXP);
> +       reg = &timing_power[2];
> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tCKE / clk_period_ps;
> +       val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tCKE);
> +       reg = &timing_power[3];
> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
> +
> +       val = dmc->timings->tMRD / clk_period_ps;
> +       val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
> +       val = max(val, dmc->min_tck->tMRD);
> +       reg = &timing_power[4];
> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
> +
> +       return 0;
> +}
> +
> +/**
> + * of_get_dram_timings() - helper function for parsing DT settings for DRAM
> + * @dmc:        device for which the frequency is going to be set
> + *
> + * The function parses DT entries with DRAM information.
> + */
> +static int of_get_dram_timings(struct exynos5_dmc *dmc)
> +{
> +       int ret = 0;
> +       int idx;
> +       struct device_node *np_ddr;
> +       u32 freq_mhz, clk_period_ps;
> +
> +       np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
> +       if (!np_ddr) {
> +               dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
> +               return -EINVAL;
> +       }
> +
> +       dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
> +                                            sizeof(u32), GFP_KERNEL);
> +       if (!dmc->timing_row)
> +               return -ENOMEM;
> +
> +       dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
> +                                             sizeof(u32), GFP_KERNEL);
> +       if (!dmc->timing_data)
> +               return -ENOMEM;
> +
> +       dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
> +                                              sizeof(u32), GFP_KERNEL);
> +       if (!dmc->timing_power)
> +               return -ENOMEM;
> +
> +       dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
> +                                                DDR_TYPE_LPDDR3,
> +                                                &dmc->timings_arr_size);
> +       if (!dmc->timings) {
> +               of_node_put(np_ddr);
> +               dev_warn(dmc->dev, "could not get timings from DT\n");
> +               return -EINVAL;
> +       }
> +
> +       dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
> +       if (!dmc->min_tck) {
> +               of_node_put(np_ddr);
> +               dev_warn(dmc->dev, "could not get tck from DT\n");
> +               return -EINVAL;
> +       }
> +
> +       /* Sorted array of OPPs with frequency ascending */
> +       for (idx = 0; idx < dmc->opp_count; idx++) {
> +               freq_mhz = dmc->opp[idx].freq_hz / 1000000;
> +               clk_period_ps = 1000000 / freq_mhz;
> +
> +               ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
> +                                            &dmc->timing_data[idx],
> +                                            &dmc->timing_power[idx],
> +                                            clk_period_ps);
> +       }
> +
> +       of_node_put(np_ddr);
> +
> +       /* Take the highest frequency's timings as 'bypass' */
> +       dmc->bypass_timing_row = dmc->timing_row[idx - 1];
> +       dmc->bypass_timing_data = dmc->timing_data[idx - 1];
> +       dmc->bypass_timing_power = dmc->timing_power[idx - 1];
> +
> +       return ret;
> +}
> +
> +/**
> + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
> + * @dmc:       DMC structure containing needed fields
> + *
> + * Get the needed clocks defined in DT device, enable and set the right parents.
> + * Read current frequency and initialize the initial rate for governor.
> + */
> +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
> +{
> +       int ret;
> +       unsigned long target_volt = 0;
> +       unsigned long target_rate = 0;
> +
> +       dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
> +       if (IS_ERR(dmc->fout_spll))
> +               return PTR_ERR(dmc->fout_spll);
> +
> +       dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
> +       if (IS_ERR(dmc->fout_bpll))
> +               return PTR_ERR(dmc->fout_bpll);
> +
> +       dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
> +       if (IS_ERR(dmc->mout_mclk_cdrex))
> +               return PTR_ERR(dmc->mout_mclk_cdrex);

You are not enabling this clock. It is divider so it is fine for him
but what about its parents? How can you guarantee that parents are
enabled?

> +
> +       dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
> +       if (IS_ERR(dmc->mout_bpll))
> +               return PTR_ERR(dmc->mout_bpll);
> +
> +       dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
> +                                               "mout_mx_mspll_ccore");
> +       if (IS_ERR(dmc->mout_mx_mspll_ccore))
> +               return PTR_ERR(dmc->mout_mx_mspll_ccore);
> +
> +       dmc->dout_clk2x_phy0 = devm_clk_get(dmc->dev, "dout_clk2x_phy0");
> +       if (IS_ERR(dmc->dout_clk2x_phy0))
> +               return PTR_ERR(dmc->dout_clk2x_phy0);

This looks like not used.

> +
> +       dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
> +       if (IS_ERR(dmc->mout_spll)) {
> +               dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
> +               if (IS_ERR(dmc->mout_spll))
> +                       return PTR_ERR(dmc->mout_spll);
> +       }
> +
> +       /*
> +        * Convert frequency to KHz values and set it for the governor.
> +        */
> +       dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
> +       dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
> +       exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
> +
> +       ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
> +                                       &target_volt, 0);
> +       if (ret)
> +               return ret;
> +
> +       dmc->curr_volt = target_volt;
> +
> +       clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
> +
> +       dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
> +
> +       clk_prepare_enable(dmc->fout_bpll);
> +       clk_prepare_enable(dmc->mout_bpll);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_performance_counters_init() - Initializes performance DMC's counters
> + * @dmc:       DMC for which it does the setup
> + *
> + * Initialization of performance counters in DMC for estimating usage.
> + * The counter's values are used for calculation of a memory bandwidth and based
> + * on that the governor changes the frequency.
> + * The counters are not used when the governor is GOVERNOR_USERSPACE.
> + */
> +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
> +{
> +       int counters_size;
> +       int ret, i;
> +
> +       dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
> +       if (dmc->num_counters < 0) {
> +               dev_err(dmc->dev, "could not get devfreq-event counters\n");
> +               return dmc->num_counters;
> +       }
> +
> +       counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
> +       dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
> +       if (!dmc->counter)
> +               return -ENOMEM;
> +
> +       for (i = 0; i < dmc->num_counters; i++) {
> +               dmc->counter[i] =
> +                       devfreq_event_get_edev_by_phandle(dmc->dev, i);
> +               if (IS_ERR_OR_NULL(dmc->counter[i]))
> +                       return -EPROBE_DEFER;
> +       }
> +
> +       ret = exynos5_counters_enable_edev(dmc);
> +       if (ret < 0) {
> +               dev_err(dmc->dev, "could not enable event counter\n");
> +               return ret;
> +       }
> +
> +       ret = exynos5_counters_set_event(dmc);
> +       if (ret < 0) {
> +               dev_err(dmc->dev, "counld not set event counter\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
> + * @dmc:       device which is used for changing this feature
> + * @set:       a boolean state passing enable/disable request
> + *
> + * There is a need of pausing DREX DMC when divider or MUX in clock tree
> + * changes its configuration. In such situation access to the memory is blocked
> + * in DMC automatically. This feature is used when clock frequency change
> + * request appears and touches clock tree.
> + */
> +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
> +{
> +       unsigned int val;
> +       int ret;
> +
> +       ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
> +       if (ret)
> +               return ret;
> +
> +       val |= 1UL;
> +       regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
> +
> +       return 0;
> +}
> +
> +/**
> + * exynos5_dmc_probe() - Probe function for the DMC driver
> + * @pdev:      platform device for which the driver is going to be initialized
> + *
> + * Initialize basic components: clocks, regulators, performance counters, etc.
> + * Read out product version and based on the information setup
> + * internal structures for the controller (frequency and voltage) and for DRAM
> + * memory parameters: timings for each operating frequency.
> + * Register new devfreq device for controlling DVFS of the DMC.
> + */
> +static int exynos5_dmc_probe(struct platform_device *pdev)
> +{
> +       int ret = 0;
> +       struct exynos5_dmc *dmc;

A nit: put un-initialized variables close to each other, it brings some order.

> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct resource *res;
> +
> +       dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
> +       if (!dmc)
> +               return -ENOMEM;
> +
> +       mutex_init(&dmc->lock);
> +
> +       dmc->dev = dev;
> +       platform_set_drvdata(pdev, dmc);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       dmc->base_drexi0 = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dmc->base_drexi0))
> +               return PTR_ERR(dmc->base_drexi0);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +       dmc->base_drexi1 = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dmc->base_drexi1))
> +               return PTR_ERR(dmc->base_drexi1);
> +
> +       dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
> +                               "samsung,syscon-clk");
> +       if (IS_ERR(dmc->clk_regmap))
> +               return PTR_ERR(dmc->clk_regmap);
> +
> +       ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
> +       if (ret) {
> +               dev_warn(dev, "couldn't initialize frequency settings\n");
> +               return ret;
> +       }
> +
> +       dmc->vdd_mif = devm_regulator_get(dev, "vdd");
> +       if (IS_ERR(dmc->vdd_mif)) {
> +               ret = PTR_ERR(dmc->vdd_mif);
> +               return ret;
> +       }
> +
> +       ret = exynos5_dmc_init_clks(dmc);
> +       if (ret)
> +               return ret;
> +
> +       ret = of_get_dram_timings(dmc);
> +       if (ret) {
> +               dev_warn(dev, "couldn't initialize timings settings\n");
> +               return ret;
> +       }
> +
> +       ret = exynos5_performance_counters_init(dmc);
> +       if (ret) {
> +               dev_warn(dev, "couldn't probe performance counters\n");
> +               goto remove_clocks;
> +       }
> +
> +       ret = exynos5_dmc_set_pause_on_switching(dmc);
> +       if (ret) {
> +               dev_warn(dev, "couldn't get access to PAUSE register\n");
> +               goto remove_clocks;
> +       }
> +
> +       /*
> +        * Setup default thresholds for the devfreq governor.
> +        * The values are chosen based on experiments.
> +        */
> +       dmc->gov_data.upthreshold = 30;
> +       dmc->gov_data.downdifferential = 5;
> +
> +       dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
> +                                         DEVFREQ_GOV_USERSPACE,
> +                                         &dmc->gov_data);
> +
> +       if (IS_ERR(dmc->df)) {
> +               ret = PTR_ERR(dmc->df);
> +               goto err_devfreq_add;
> +       }
> +
> +       dev_info(dev, "DMC initialized\n");
> +
> +       return 0;
> +
> +err_devfreq_add:
> +       exynos5_counters_disable_edev(dmc);
> +remove_clocks:
> +       clk_disable_unprepare(dmc->mout_spll);
> +       clk_disable_unprepare(dmc->fout_spll);

This looks unbalanced. Where was the enable of fout_spll? This is
weird - some clocks are disabled in this error path but not in
remove(). Some the opposite - not disabled on error path.

Best regards,
Krzysztof

Re: [PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422

[Lukasz Luba]

Hi Krzysztof,

On 6/6/19 12:03 PM, Krzysztof Kozlowski wrote:
> On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> This patch adds driver for Exynos5422 Dynamic Memory Controller.
>> The driver provides support for dynamic frequency and voltage scaling for
>> DMC and DRAM. It supports changing timings of DRAM running with different
>> frequency. There is also an algorithm to calculate timigns based on
>> memory description provided in DT.
>> The patch also contains needed MAINTAINERS file update.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   MAINTAINERS                             |    8 +
>>   drivers/memory/samsung/Kconfig          |   17 +
>>   drivers/memory/samsung/Makefile         |    1 +
>>   drivers/memory/samsung/exynos5422-dmc.c | 1265 +++++++++++++++++++++++
>>   4 files changed, 1291 insertions(+)
>>   create mode 100644 drivers/memory/samsung/exynos5422-dmc.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index a6954776a37e..d57cf4be1e51 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3470,6 +3470,14 @@ S:       Maintained
>>   F:     drivers/devfreq/exynos-bus.c
>>   F:     Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
>> +M:     Lukasz Luba <l.luba@partner.samsung.com>
>> +L:     linux-pm@vger.kernel.org
>> +L:     linux-samsung-soc@vger.kernel.org
>> +S:     Maintained
>> +F:     drivers/memory/samsung/exynos5422-dmc.c
>> +F:     Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> +
>>   BUSLOGIC SCSI DRIVER
>>   M:     Khalid Aziz <khalid@gonehiking.org>
>>   L:     linux-scsi@vger.kernel.org
>> diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig
>> index 79ce7ea58903..c93baa029654 100644
>> --- a/drivers/memory/samsung/Kconfig
>> +++ b/drivers/memory/samsung/Kconfig
>> @@ -5,6 +5,23 @@ config SAMSUNG_MC
>>            Support for the Memory Controller (MC) devices found on
>>            Samsung Exynos SoCs.
>>
>> +config ARM_EXYNOS5422_DMC
>> +       tristate "ARM EXYNOS5422 Dynamic Memory Controller driver"
>> +       depends on ARCH_EXYNOS
>> +       select DDR
>> +       select PM_DEVFREQ
>> +       select DEVFREQ_GOV_SIMPLE_ONDEMAND
>> +       select DEVFREQ_GOV_USERSPACE
>> +       select PM_DEVFREQ_EVENT
>> +       select PM_OPP
>> +       help
>> +         This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
>> +         The driver provides support for Dynamic Voltage and Frequency Scaling in
>> +         DMC and DRAM. It also supports changing timings of DRAM running with
>> +         different frequency. The timings are calculated based on DT memory
>> +         information.
>> +
>> +
>>   if SAMSUNG_MC
>>
>>   config EXYNOS_SROM
>> diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile
>> index 00587be66211..4f6e4383bab7 100644
>> --- a/drivers/memory/samsung/Makefile
>> +++ b/drivers/memory/samsung/Makefile
>> @@ -1,2 +1,3 @@
>>   # SPDX-License-Identifier: GPL-2.0
>> +obj-$(CONFIG_ARM_EXYNOS5422_DMC)       += exynos5422-dmc.o
>>   obj-$(CONFIG_EXYNOS_SROM)      += exynos-srom.o
>> diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
>> new file mode 100644
>> index 000000000000..6fca9e4c45ff
>> --- /dev/null
>> +++ b/drivers/memory/samsung/exynos5422-dmc.c
>> @@ -0,0 +1,1265 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
>> + * Author: Lukasz Luba <l.luba@partner.samsung.com>
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/devfreq.h>
>> +#include <linux/devfreq-event.h>
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pm_opp.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/slab.h>
>> +#include <memory/jedec_ddr.h>
>> +#include "../of_memory.h"
>> +
>> +#define EXYNOS5_DREXI_TIMINGAREF               (0x0030)
>> +#define EXYNOS5_DREXI_TIMINGROW0               (0x0034)
>> +#define EXYNOS5_DREXI_TIMINGDATA0              (0x0038)
>> +#define EXYNOS5_DREXI_TIMINGPOWER0             (0x003C)
>> +#define EXYNOS5_DREXI_TIMINGROW1               (0x00E4)
>> +#define EXYNOS5_DREXI_TIMINGDATA1              (0x00E8)
>> +#define EXYNOS5_DREXI_TIMINGPOWER1             (0x00EC)
>> +#define CDREX_PAUSE                            (0x2091c)
>> +#define CDREX_LPDDR3PHY_CON3                   (0x20a20)
>> +#define EXYNOS5_TIMING_SET_SWI                  (1UL << 28)
> 
> You have mixed indentation here (spaces instead of tabs).
fixed
> 
>> +#define USE_MX_MSPLL_TIMINGS                   (1)
>> +#define USE_BPLL_TIMINGS                       (0)
>> +#define EXYNOS5_AREF_NORMAL                    (0x2e)
>> +
>> +/**
>> + * struct dmc_opp_table - Operating level desciption
>> + *
>> + * Covers frequency and voltage settings of the DMC operating mode.
>> + */
>> +struct dmc_opp_table {
>> +       u32 freq_hz;
>> +       u32 volt_uv;
>> +};
>> +
>> +/**
>> + * struct exynos5_dmc - main structure describing DMC device
>> + *
>> + * The main structure for the Dynamic Memory Controller which covers clocks,
>> + * memory regions, HW information, parameters and current operating mode.
>> + */
>> +struct exynos5_dmc {
>> +       struct device *dev;
>> +       struct devfreq *df;
>> +       struct devfreq_simple_ondemand_data gov_data;
>> +       void __iomem *base_drexi0;
>> +       void __iomem *base_drexi1;
>> +       struct regmap *clk_regmap;
>> +       struct mutex lock;
>> +       unsigned long curr_rate;
>> +       unsigned long curr_volt;
>> +       unsigned long bypass_rate;
>> +       struct dmc_opp_table *opp;
>> +       struct dmc_opp_table opp_bypass;
>> +       int opp_count;
>> +       u32 timings_arr_size;
>> +       u32 *timing_row;
>> +       u32 *timing_data;
>> +       u32 *timing_power;
>> +       const struct lpddr3_timings *timings;
>> +       const struct lpddr3_min_tck *min_tck;
>> +       u32 bypass_timing_row;
>> +       u32 bypass_timing_data;
>> +       u32 bypass_timing_power;
>> +       struct regulator *vdd_mif;
>> +       struct clk *fout_spll;
>> +       struct clk *fout_bpll;
>> +       struct clk *mout_spll;
>> +       struct clk *mout_bpll;
>> +       struct clk *mout_mclk_cdrex;
>> +       struct clk *dout_clk2x_phy0;
>> +       struct clk *mout_mx_mspll_ccore;
>> +       struct clk *mx_mspll_ccore_phy;
>> +       struct clk *mout_mx_mspll_ccore_phy;
>> +       struct devfreq_event_dev **counter;
>> +       int num_counters;
>> +};
>> +
>> +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
>> +       { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
>> +
>> +#define TIMING_VAL(timing_array, id, t_val)                    \
>> +({                                                             \
>> +               u32 __val;                              \
>> +               __val = t_val << timing_array[id].bit_beg;      \
>> +               __val;                                          \
>> +})
>> +
>> +#define TIMING_VAL2REG(timing, t_val)                  \
>> +({                                                             \
>> +               u32 __val;                              \
>> +               __val = t_val << timing->bit_beg;       \
>> +               __val;                                          \
>> +})
>> +
>> +#define TIMING_REG2VAL(reg, timing)                    \
>> +({                                                             \
>> +               u32 __val;                              \
>> +               reg <<= (31 - timing->bit_end);         \
>> +               reg >>= (31 - timing->bit_end);         \
>> +               __val = reg >> timing->bit_beg; \
>> +               __val;                                          \
>> +})
>> +
>> +struct timing_reg {
>> +       char *name;
>> +       int bit_beg;
>> +       int bit_end;
>> +       unsigned int val;
>> +};
>> +
>> +static const struct timing_reg timing_row[] = {
>> +       TIMING_FIELD("tRFC", 24, 31),
>> +       TIMING_FIELD("tRRD", 20, 23),
>> +       TIMING_FIELD("tRP", 16, 19),
>> +       TIMING_FIELD("tRCD", 12, 15),
>> +       TIMING_FIELD("tRC", 6, 11),
>> +       TIMING_FIELD("tRAS", 0, 5),
>> +};
>> +
>> +static const struct timing_reg timing_data[] = {
>> +       TIMING_FIELD("tWTR", 28, 31),
>> +       TIMING_FIELD("tWR", 24, 27),
>> +       TIMING_FIELD("tRTP", 20, 23),
>> +       TIMING_FIELD("tW2W-C2C", 14, 14),
>> +       TIMING_FIELD("tR2R-C2C", 12, 12),
>> +       TIMING_FIELD("WL", 8, 11),
>> +       TIMING_FIELD("tDQSCK", 4, 7),
>> +       TIMING_FIELD("RL", 0, 3),
>> +};
>> +
>> +static const struct timing_reg timing_power[] = {
>> +       TIMING_FIELD("tFAW", 26, 31),
>> +       TIMING_FIELD("tXSR", 16, 25),
>> +       TIMING_FIELD("tXP", 8, 15),
>> +       TIMING_FIELD("tCKE", 4, 7),
>> +       TIMING_FIELD("tMRD", 0, 3),
>> +};
>> +
>> +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
>> +                     ARRAY_SIZE(timing_power))
>> +
>> +static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
>> +{
>> +       int i, ret;
>> +
>> +       for (i = 0; i < dmc->num_counters; i++) {
>> +               if (!dmc->counter[i])
>> +                       continue;
>> +               ret = devfreq_event_set_event(dmc->counter[i]);
>> +               if (ret < 0)
>> +                       return ret;
>> +       }
>> +       return 0;
>> +}
>> +
>> +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
>> +{
>> +       int i, ret;
>> +
>> +       for (i = 0; i < dmc->num_counters; i++) {
>> +               if (!dmc->counter[i])
>> +                       continue;
>> +               ret = devfreq_event_enable_edev(dmc->counter[i]);
>> +               if (ret < 0)
>> +                       return ret;
>> +       }
>> +       return 0;
>> +}
>> +
>> +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
>> +{
>> +       int i, ret;
>> +
>> +       for (i = 0; i < dmc->num_counters; i++) {
>> +               if (!dmc->counter[i])
>> +                       continue;
>> +               ret = devfreq_event_disable_edev(dmc->counter[i]);
>> +               if (ret < 0)
>> +                       return ret;
>> +       }
>> +       return 0;
>> +}
>> +
>> +/**
>> + * find_target_freq_id() - Finds requested frequency in local DMC configuration
>> + * @dmc:       device for which the information is checked
>> + * @target_rate:       requested frequency in KHz
>> + *
>> + * Seeks in the local DMC driver structure for the requested frequency value
>> + * and returns index or error value.
>> + */
>> +static int find_target_freq_idx(struct exynos5_dmc *dmc,
>> +                               unsigned long target_rate)
>> +{
>> +       int i;
>> +
>> +       for (i = dmc->opp_count - 1; i >= 0; i--)
>> +               if (dmc->opp[i].freq_hz <= target_rate)
>> +                       return i;
>> +
>> +       return -EINVAL;
>> +}
>> +
>> +/**
>> + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
>> + * @dmc:       device for which the new settings is going to be applied
>> + * @set:       boolean variable passing set value
>> + *
>> + * Changes the register set, which holds timing parameters.
>> + * There is two register sets: 0 and 1. The register set 0
>> + * is used in normal operation when the clock is provided from main PLL.
>> + * The bank register set 1 is used when the main PLL frequency is going to be
>> + * changed and the clock is taken from alternative, stable source.
>> + * This function switches between these banks according to the
>> + * currently used clock source.
>> + */
>> +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
>> +{
>> +       unsigned int reg;
>> +       int ret;
>> +
>> +       ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, &reg);
>> +
>> +       if (set)
>> +               reg |= EXYNOS5_TIMING_SET_SWI;
>> +       else
>> +               reg &= ~EXYNOS5_TIMING_SET_SWI;
>> +
>> +       regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
>> +}
>> +
>> +/**
>> + * exynos5_init_freq_table() - Initialized PM OPP framework
>> + * @dmc:       DMC device for which the frequencies are used for OPP init
>> + * @profile:   devfreq device's profile
>> + *
>> + * Populate the devfreq device's OPP table based on current frequency, voltage.
>> + */
>> +static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
>> +                                  struct devfreq_dev_profile *profile)
>> +{
>> +       int i, ret;
>> +       int idx;
>> +       unsigned long freq;
>> +
>> +       ret = dev_pm_opp_of_add_table(dmc->dev);
>> +       if (ret < 0) {
>> +               dev_err(dmc->dev, "Failed to get OPP table\n");
>> +               return ret;
>> +       }
>> +
>> +       dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
>> +
>> +       dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
>> +                                     sizeof(struct dmc_opp_table), GFP_KERNEL);
>> +       if (!dmc->opp)
>> +               goto err_opp;
>> +
>> +       idx = dmc->opp_count - 1;
>> +       for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
>> +               struct dev_pm_opp *opp;
>> +
>> +               opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
>> +               if (IS_ERR(opp))
>> +                       goto err_free_tables;
>> +
>> +               dmc->opp[idx - i].freq_hz = freq;
>> +               dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
>> +
>> +               dev_pm_opp_put(opp);
>> +       }
>> +
>> +       return 0;
>> +
>> +err_free_tables:
>> +       kfree(dmc->opp);
>> +err_opp:
>> +       dev_pm_opp_of_remove_table(dmc->dev);
>> +
>> +       return -EINVAL;
>> +}
>> +
>> +/**
>> + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
>> + * @dmc:       device for which the new settings is going to be applied
>> + * @param:     DRAM parameters which passes timing data
>> + *
>> + * Low-level function for changing timings for DRAM memory clocking from
>> + * 'bypass' clock source (fixed frequency @400MHz).
>> + * It uses timing bank registers set 1.
>> + */
>> +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
>> +{
>> +       writel(EXYNOS5_AREF_NORMAL,
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
>> +
>> +       writel(dmc->bypass_timing_row,
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
>> +       writel(dmc->bypass_timing_row,
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
>> +       writel(dmc->bypass_timing_data,
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
>> +       writel(dmc->bypass_timing_data,
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
>> +       writel(dmc->bypass_timing_power,
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
>> +       writel(dmc->bypass_timing_power,
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
>> +}
>> +
>> +/**
>> + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
>> + * @dmc:       device for which the new settings is going to be applied
>> + * @target_rate:       target frequency of the DMC
>> + *
>> + * Low-level function for changing timings for DRAM memory operating from main
>> + * clock source (BPLL), which can have different frequencies. Thus, each
>> + * frequency must have corresponding timings register values in order to keep
>> + * the needed delays.
>> + * It uses timing bank registers set 0.
>> + */
>> +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
>> +                                      unsigned long target_rate)
>> +{
>> +       int idx;
>> +
>> +       for (idx = dmc->opp_count - 1; idx >= 0; idx--)
>> +               if (dmc->opp[idx].freq_hz <= target_rate)
>> +                       break;
>> +
>> +       if (idx < 0)
>> +               return -EINVAL;
>> +
>> +       writel(EXYNOS5_AREF_NORMAL,
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
>> +
>> +       writel(dmc->timing_row[idx],
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
>> +       writel(dmc->timing_row[idx],
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
>> +       writel(dmc->timing_data[idx],
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
>> +       writel(dmc->timing_data[idx],
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
>> +       writel(dmc->timing_power[idx],
>> +              dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
>> +       writel(dmc->timing_power[idx],
>> +              dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
>> + * @dmc:       device for which it is going to be set
>> + * @target_volt:       new voltage which is chosen to be final
>> + *
>> + * Function tries to align voltage to the safe level for 'normal' mode.
>> + * It checks the need of higher voltage and changes the value. The target
>> + * voltage might be lower that currently set and still the system will be
>> + * stable.
>> + */
>> +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
>> +                                           unsigned long target_volt)
>> +{
>> +       int ret = 0;
>> +
>> +       if (dmc->curr_volt > target_volt) {
> 
> A nit: I would prefer to use the same style as in
> exynos5_dmc_align_bypass_voltage(), so "return 0" after "if", to have
> consistent pattern easily understand which function bumps and which
> lowers the voltage.
Make sense, I will change it.
> 
> 
>> +               ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
>> +                                           target_volt);
>> +               if (!ret)
>> +                       dmc->curr_volt = target_volt;
>> +       }
>> +
>> +       return ret;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
>> + * @dmc:       device for which it is going to be set
>> + * @target_volt:       new voltage which is chosen to be final
>> + *
>> + * Function tries to align voltage to the safe level for the 'bypass' mode.
>> + * It checks the need of higher voltage and changes the value.
>> + * The target voltage must not be less than currently needed, because
>> + * for current frequency the device might become unstable.
>> + */
>> +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
>> +                                           unsigned long target_volt)
>> +{
>> +       int ret = 0;
>> +       unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
>> +
>> +       target_volt = max(bypass_volt, target_volt);
>> +
>> +       if (dmc->curr_volt >= target_volt)
>> +               return 0;
>> +
>> +       ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
>> +                                   target_volt);
>> +       if (!ret)
>> +               dmc->curr_volt = target_volt;
>> +
>> +       return ret;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
>> + * @dmc:       device for which it is going to be set
>> + * @target_rate:       new frequency which is chosen to be final
>> + *
>> + * Function changes the DRAM timings for the temporary 'bypass' mode.
>> + */
>> +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
>> +                                                unsigned long target_rate)
>> +{
>> +       int idx = find_target_freq_idx(dmc, target_rate);
>> +
>> +       if (idx < 0)
>> +               return -EINVAL;
>> +
>> +       exynos5_set_bypass_dram_timings(dmc);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
>> + * @dmc:       DMC device for which the switching is going to happen
>> + * @target_rate:       new frequency which is going to be set as a final
>> + * @target_volt:       new voltage which is going to be set as a final
>> + *
>> + * Function configures DMC and clocks for operating in temporary 'bypass' mode.
>> + * This mode is used only temporary but if required, changes voltage and timings
>> + * for DRAM chips. It switches the main clock to stable clock source for the
>> + * period of the main PLL reconfiguration.
>> + */
>> +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
>> +                                  unsigned long target_rate,
>> +                                  unsigned long target_volt)
>> +{
>> +       int ret;
>> +
>> +       /*
>> +        * Having higher voltage for a particular frequency does not harm
>> +        * the chip. Use it for the temporary frequency change when one
>> +        * voltage manipulation might be avoided.
>> +        */
>> +       ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /*
>> +        * Longer delays for DRAM does not cause crash, the opposite does.
>> +        */
>> +       ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /*
>> +        * Delays are long enough, so use them for the new coming clock.
>> +        */
>> +       exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
>> +
>> +       return ret;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
>> + * using safe procedure
>> + * @dmc:       device for which the frequency is going to be changed
>> + * @target_rate:       requested new frequency
>> + * @target_volt:       requested voltage which corresponds to the new frequency
>> + *
>> + * The DMC frequency change procedure requires a few steps.
>> + * The main requirement is to change the clock source in the clk mux
>> + * for the time of main clock PLL locking. The assumption is that the
>> + * alternative clock source set as parent is stable.
>> + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
>> + * clock. This requires alignment in DRAM timing parameters for the new
>> + * T-period. There is two bank sets for keeping DRAM
>> + * timings: set 0 and set 1. The set 0 is used when main clock source is
>> + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
>> + * the two bank sets is part of the process.
>> + * The voltage must also be aligned to the minimum required level. There is
>> + * this intermediate step with switching to 'bypass' parent clock source.
>> + * if the old voltage is lower, it requires an increase of the voltage level.
>> + * The complexity of the voltage manipulation is hidden in low level function.
>> + * In this function there is last alignment of the voltage level at the end.
>> + */
>> +static int
>> +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
>> +                                unsigned long target_rate,
>> +                                unsigned long target_volt)
>> +{
>> +       int ret;
>> +
>> +       ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
>> +                                                        target_volt);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /*
>> +        * Voltage is set at least to a level needed for this frequency,
>> +        * so switching clock source is safe now.
>> +        */
>> +       clk_prepare_enable(dmc->fout_spll);
>> +       clk_prepare_enable(dmc->mout_spll);
>> +       clk_prepare_enable(dmc->mout_mx_mspll_ccore);
>> +
>> +       ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
>> +       if (ret)
> 
> What about error path and disabling clocks?
Good point
> 
>> +               return ret;
>> +
>> +       /*
>> +        * We are safe to increase the timings for current bypass frequency.
>> +        * Thanks to this the settings we be ready for the upcoming clock source
>> +        * change.
>> +        */
>> +       exynos5_dram_change_timings(dmc, target_rate);
>> +
>> +       clk_set_rate(dmc->fout_bpll, target_rate);
>> +
>> +       exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
>> +
>> +       ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
>> +       if (ret)
> 
> Ditto.
There will be 'goto disable_clocks' in the next version.
> 
>> +               return ret;
>> +
>> +       clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
>> +       clk_disable_unprepare(dmc->mout_spll);
>> +       clk_disable_unprepare(dmc->fout_spll);
>> +
>> +       /*
>> +        * Make sure if the voltage is not from 'bypass' settings and align to
>> +        * the right level for power efficiency.
>> +        */
>> +       ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
>> +
>> +       return ret;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
>> + * table.
>> + * @dmc:       device for which the frequency is going to be changed
>> + * @freq:       requested frequency in KHz
>> + * @target_rate:       returned frequency which is the same or lower than
>> + *                     requested
>> + * @target_volt:       returned voltage which corresponds to the returned
>> + *                     frequency
>> + *
>> + * Function gets requested frequency and checks OPP framework for needed
>> + * frequency and voltage. It populates the values 'target_rate' and
>> + * 'target_volt' or returns error value when OPP framework fails.
>> + */
>> +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
>> +                                    unsigned long *freq,
>> +                                    unsigned long *target_rate,
>> +                                    unsigned long *target_volt, u32 flags)
>> +{
>> +       struct dev_pm_opp *opp;
>> +
>> +       opp = devfreq_recommended_opp(dmc->dev, freq, flags);
>> +       if (IS_ERR(opp))
>> +               return PTR_ERR(opp);
>> +
>> +       *target_rate = dev_pm_opp_get_freq(opp);
>> +       *target_volt = dev_pm_opp_get_voltage(opp);
>> +       dev_pm_opp_put(opp);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_target() - Function responsible for changing frequency of DMC
>> + * @dev:       device for which the frequency is going to be changed
>> + * @freq:      requested frequency in KHz
>> + * @flags:     flags provided for this frequency change request
>> + *
>> + * An entry function provided to the devfreq framework which provides frequency
>> + * change of the DMC. The function gets the possible rate from OPP table based
>> + * on requested frequency. It calls the next function responsible for the
>> + * frequency and voltage change. In case of failure, does not set 'curr_rate'
>> + * and returns error value to the framework.
>> + */
>> +static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
>> +                             u32 flags)
>> +{
>> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
>> +       unsigned long target_rate = 0;
>> +       unsigned long target_volt = 0;
>> +       int ret;
>> +
>> +       ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
>> +                                       flags);
>> +
>> +       if (ret)
>> +               return ret;
>> +
>> +       if (target_rate == dmc->curr_rate)
>> +               return 0;
>> +
>> +       mutex_lock(&dmc->lock);
>> +
>> +       ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
>> +
>> +       if (ret) {
>> +               mutex_unlock(&dmc->lock);
>> +               return ret;
>> +       }
>> +
>> +       dmc->curr_rate = target_rate;
>> +
>> +       mutex_unlock(&dmc->lock);
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_counters_get() - Gets the performance counters values.
>> + * @dmc:       device for which the counters are going to be checked
>> + * @load_count:        variable which is populated with counter value
>> + * @total_count:       variable which is used as 'wall clock' reference
>> + *
>> + * Function which provides performance counters values. It sums up counters for
>> + * two DMC channels. The 'total_count' is used as a reference and max value.
>> + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
>> + */
>> +static int exynos5_counters_get(struct exynos5_dmc *dmc,
>> +                               unsigned long *load_count,
>> +                               unsigned long *total_count)
>> +{
>> +       unsigned long total = 0;
>> +       struct devfreq_event_data event;
>> +       int ret, i;
>> +
>> +       *load_count = 0;
>> +
>> +       /* Take into account only read+write counters, but stop all */
>> +       for (i = 0; i < dmc->num_counters; i++) {
>> +               if (!dmc->counter[i])
>> +                       continue;
>> +
>> +               ret = devfreq_event_get_event(dmc->counter[i], &event);
>> +               if (ret < 0)
>> +                       return ret;
>> +
>> +               *load_count += event.load_count;
>> +
>> +               if (total < event.total_count)
>> +                       total = event.total_count;
>> +       }
>> +
>> +       *total_count = total;
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_get_status() - Read current DMC performance statistics.
>> + * @dev:       device for which the statistics are requested
>> + * @stat:      structure which has statistic fields
>> + *
>> + * Function reads the DMC performance counters and calculates 'busy_time'
>> + * and 'total_time'. To protect from overflow, the values are shifted right
>> + * by 10. After read out the counters are setup to count again.
>> + */
>> +static int exynos5_dmc_get_status(struct device *dev,
>> +                                 struct devfreq_dev_status *stat)
>> +{
>> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
>> +       unsigned long load, total;
>> +       int ret;
>> +
>> +       ret = exynos5_counters_get(dmc, &load, &total);
>> +       if (ret < 0)
>> +               return -EINVAL;
>> +
>> +       /* To protect from overflow in calculation ratios, divide by 1024 */
>> +       stat->busy_time = load >> 10;
>> +       stat->total_time = total >> 10;
>> +
>> +       ret = exynos5_counters_set_event(dmc);
>> +       if (ret < 0) {
>> +               dev_err(dev, "could not set event counter\n");
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
>> + * @dev:       device for which the framework checks operating frequency
>> + * @freq:      returned frequency value
>> + *
>> + * It returns the currently used frequency of the DMC. The real operating
>> + * frequency might be lower when the clock source value could not be divided
>> + * to the requested value.
>> + */
>> +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
>> +{
>> +       struct exynos5_dmc *dmc = dev_get_drvdata(dev);
>> +
>> +       mutex_lock(&dmc->lock);
>> +       *freq = dmc->curr_rate;
>> +       mutex_unlock(&dmc->lock);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_df_profile - Devfreq governor's profile structure
>> + *
>> + * It provides to the devfreq framework needed functions and polling period.
>> + */
>> +static struct devfreq_dev_profile exynos5_dmc_df_profile = {
>> +       .polling_ms = 500,
>> +       .target = exynos5_dmc_target,
>> +       .get_dev_status = exynos5_dmc_get_status,
>> +       .get_cur_freq = exynos5_dmc_get_cur_freq,
>> +};
>> +
>> +/**
>> + * exynos5_dmc_align_initial_frequency() - Align initial frequency value
>> + * @dmc:       device for which the frequency is going to be set
>> + * @bootloader_init_freq:      initial frequency set by the bootloader in KHz
>> + *
>> + * The initial bootloader frequency, which is present during boot, might be
>> + * different that supported frequency values in the driver. It is possible
>> + * due to different PLL settings or used PLL as a source.
>> + * This function provides the 'initial_freq' for the devfreq framework
>> + * statistics engine which supports only registered values. Thus, some alignment
>> + * must be made.
>> + */
>> +unsigned long
>> +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
>> +                           unsigned long bootloader_init_freq)
>> +{
>> +       unsigned long aligned_freq;
>> +       int idx;
>> +
>> +       idx = find_target_freq_idx(dmc, bootloader_init_freq);
>> +       if (idx >= 0)
>> +               aligned_freq = dmc->opp[idx].freq_hz;
>> +       else
>> +               aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
>> +
>> +       return aligned_freq;
>> +}
>> +
>> +/**
>> + * create_timings_aligned() - Create register values and align with standard
>> + * @dmc:       device for which the frequency is going to be set
>> + * @idx:       speed bin in the OPP table
>> + * @clk_period_ps:     the period of the clock, known as tCK
>> + *
>> + * The function calculates timings and creates a register value ready for
>> + * a frequency transition. The register contains a few timings. They are
>> + * shifted by a known offset. The timing value is calculated based on memory
>> + * specyfication: minimal time required and minimal cycles required.
>> + */
>> +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
>> +                                 u32 *reg_timing_data, u32 *reg_timing_power,
>> +                                 u32 clk_period_ps)
>> +{
>> +       u32 val;
>> +       const struct timing_reg *reg;
>> +
>> +       if (clk_period_ps == 0)
>> +               return -EINVAL;
>> +
>> +       *reg_timing_row = 0;
>> +       *reg_timing_data = 0;
>> +       *reg_timing_power = 0;
>> +
>> +       val = dmc->timings->tRFC / clk_period_ps;
>> +       val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRFC);
>> +       reg = &timing_row[0];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRRD / clk_period_ps;
>> +       val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRRD);
>> +       reg = &timing_row[1];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRPab / clk_period_ps;
>> +       val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRPab);
>> +       reg = &timing_row[2];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRCD / clk_period_ps;
>> +       val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRCD);
>> +       reg = &timing_row[3];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRC / clk_period_ps;
>> +       val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRC);
>> +       reg = &timing_row[4];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRAS / clk_period_ps;
>> +       val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRAS);
>> +       reg = &timing_row[5];
>> +       *reg_timing_row |= TIMING_VAL2REG(reg, val);
>> +
>> +       /* data related timings */
>> +       val = dmc->timings->tWTR / clk_period_ps;
>> +       val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tWTR);
>> +       reg = &timing_data[0];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tWR / clk_period_ps;
>> +       val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tWR);
>> +       reg = &timing_data[1];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRTP / clk_period_ps;
>> +       val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRTP);
>> +       reg = &timing_data[2];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tW2W_C2C / clk_period_ps;
>> +       val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tW2W_C2C);
>> +       reg = &timing_data[3];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tR2R_C2C / clk_period_ps;
>> +       val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tR2R_C2C);
>> +       reg = &timing_data[4];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tWL / clk_period_ps;
>> +       val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tWL);
>> +       reg = &timing_data[5];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tDQSCK / clk_period_ps;
>> +       val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tDQSCK);
>> +       reg = &timing_data[6];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tRL / clk_period_ps;
>> +       val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tRL);
>> +       reg = &timing_data[7];
>> +       *reg_timing_data |= TIMING_VAL2REG(reg, val);
>> +
>> +       /* power related timings */
>> +       val = dmc->timings->tFAW / clk_period_ps;
>> +       val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tXP);
>> +       reg = &timing_power[0];
>> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tXSR / clk_period_ps;
>> +       val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tXSR);
>> +       reg = &timing_power[1];
>> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tXP / clk_period_ps;
>> +       val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tXP);
>> +       reg = &timing_power[2];
>> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tCKE / clk_period_ps;
>> +       val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tCKE);
>> +       reg = &timing_power[3];
>> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
>> +
>> +       val = dmc->timings->tMRD / clk_period_ps;
>> +       val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
>> +       val = max(val, dmc->min_tck->tMRD);
>> +       reg = &timing_power[4];
>> +       *reg_timing_power |= TIMING_VAL2REG(reg, val);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * of_get_dram_timings() - helper function for parsing DT settings for DRAM
>> + * @dmc:        device for which the frequency is going to be set
>> + *
>> + * The function parses DT entries with DRAM information.
>> + */
>> +static int of_get_dram_timings(struct exynos5_dmc *dmc)
>> +{
>> +       int ret = 0;
>> +       int idx;
>> +       struct device_node *np_ddr;
>> +       u32 freq_mhz, clk_period_ps;
>> +
>> +       np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
>> +       if (!np_ddr) {
>> +               dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
>> +                                            sizeof(u32), GFP_KERNEL);
>> +       if (!dmc->timing_row)
>> +               return -ENOMEM;
>> +
>> +       dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
>> +                                             sizeof(u32), GFP_KERNEL);
>> +       if (!dmc->timing_data)
>> +               return -ENOMEM;
>> +
>> +       dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
>> +                                              sizeof(u32), GFP_KERNEL);
>> +       if (!dmc->timing_power)
>> +               return -ENOMEM;
>> +
>> +       dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
>> +                                                DDR_TYPE_LPDDR3,
>> +                                                &dmc->timings_arr_size);
>> +       if (!dmc->timings) {
>> +               of_node_put(np_ddr);
>> +               dev_warn(dmc->dev, "could not get timings from DT\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
>> +       if (!dmc->min_tck) {
>> +               of_node_put(np_ddr);
>> +               dev_warn(dmc->dev, "could not get tck from DT\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       /* Sorted array of OPPs with frequency ascending */
>> +       for (idx = 0; idx < dmc->opp_count; idx++) {
>> +               freq_mhz = dmc->opp[idx].freq_hz / 1000000;
>> +               clk_period_ps = 1000000 / freq_mhz;
>> +
>> +               ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
>> +                                            &dmc->timing_data[idx],
>> +                                            &dmc->timing_power[idx],
>> +                                            clk_period_ps);
>> +       }
>> +
>> +       of_node_put(np_ddr);
>> +
>> +       /* Take the highest frequency's timings as 'bypass' */
>> +       dmc->bypass_timing_row = dmc->timing_row[idx - 1];
>> +       dmc->bypass_timing_data = dmc->timing_data[idx - 1];
>> +       dmc->bypass_timing_power = dmc->timing_power[idx - 1];
>> +
>> +       return ret;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
>> + * @dmc:       DMC structure containing needed fields
>> + *
>> + * Get the needed clocks defined in DT device, enable and set the right parents.
>> + * Read current frequency and initialize the initial rate for governor.
>> + */
>> +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
>> +{
>> +       int ret;
>> +       unsigned long target_volt = 0;
>> +       unsigned long target_rate = 0;
>> +
>> +       dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
>> +       if (IS_ERR(dmc->fout_spll))
>> +               return PTR_ERR(dmc->fout_spll);
>> +
>> +       dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
>> +       if (IS_ERR(dmc->fout_bpll))
>> +               return PTR_ERR(dmc->fout_bpll);
>> +
>> +       dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
>> +       if (IS_ERR(dmc->mout_mclk_cdrex))
>> +               return PTR_ERR(dmc->mout_mclk_cdrex);
> 
> You are not enabling this clock. It is divider so it is fine for him
> but what about its parents? How can you guarantee that parents are
> enabled?
It uses two parents in this configuration:
1. 'mout_bpll' which is set by the bootloader and is a default mode
2. 'mout_mx_mspll_ccore' which is used temporary as a 'bypass clock
source' only for the time when BPLL is changing it's settings

Do you suggest to put a call:

to make sure the parent is up and running?
OR just move the lines from the end of this function:
	clk_prepare_enable(dmc->fout_bpll);
	clk_prepare_enable(dmc->mout_bpll);
and add:
	ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
then call the clk_get_rate on 'mout_mclk_cdrex'

> 
>> +
>> +       dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
>> +       if (IS_ERR(dmc->mout_bpll))
>> +               return PTR_ERR(dmc->mout_bpll);
>> +
>> +       dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
>> +                                               "mout_mx_mspll_ccore");
>> +       if (IS_ERR(dmc->mout_mx_mspll_ccore))
>> +               return PTR_ERR(dmc->mout_mx_mspll_ccore);
>> +
>> +       dmc->dout_clk2x_phy0 = devm_clk_get(dmc->dev, "dout_clk2x_phy0");
>> +       if (IS_ERR(dmc->dout_clk2x_phy0))
>> +               return PTR_ERR(dmc->dout_clk2x_phy0);
> 
> This looks like not used.
Right, I forgot to remove it when I was cleaning the optional stuff.
> 
>> +
>> +       dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
>> +       if (IS_ERR(dmc->mout_spll)) {
>> +               dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
>> +               if (IS_ERR(dmc->mout_spll))
>> +                       return PTR_ERR(dmc->mout_spll);
>> +       }
>> +
>> +       /*
>> +        * Convert frequency to KHz values and set it for the governor.
>> +        */
>> +       dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
>> +       dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
>> +       exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
>> +
>> +       ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
>> +                                       &target_volt, 0);
>> +       if (ret)
>> +               return ret;
>> +
>> +       dmc->curr_volt = target_volt;
>> +
>> +       clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
>> +
>> +       dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
>> +
>> +       clk_prepare_enable(dmc->fout_bpll);
>> +       clk_prepare_enable(dmc->mout_bpll);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_performance_counters_init() - Initializes performance DMC's counters
>> + * @dmc:       DMC for which it does the setup
>> + *
>> + * Initialization of performance counters in DMC for estimating usage.
>> + * The counter's values are used for calculation of a memory bandwidth and based
>> + * on that the governor changes the frequency.
>> + * The counters are not used when the governor is GOVERNOR_USERSPACE.
>> + */
>> +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
>> +{
>> +       int counters_size;
>> +       int ret, i;
>> +
>> +       dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
>> +       if (dmc->num_counters < 0) {
>> +               dev_err(dmc->dev, "could not get devfreq-event counters\n");
>> +               return dmc->num_counters;
>> +       }
>> +
>> +       counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
>> +       dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
>> +       if (!dmc->counter)
>> +               return -ENOMEM;
>> +
>> +       for (i = 0; i < dmc->num_counters; i++) {
>> +               dmc->counter[i] =
>> +                       devfreq_event_get_edev_by_phandle(dmc->dev, i);
>> +               if (IS_ERR_OR_NULL(dmc->counter[i]))
>> +                       return -EPROBE_DEFER;
>> +       }
>> +
>> +       ret = exynos5_counters_enable_edev(dmc);
>> +       if (ret < 0) {
>> +               dev_err(dmc->dev, "could not enable event counter\n");
>> +               return ret;
>> +       }
>> +
>> +       ret = exynos5_counters_set_event(dmc);
>> +       if (ret < 0) {
>> +               dev_err(dmc->dev, "counld not set event counter\n");
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
>> + * @dmc:       device which is used for changing this feature
>> + * @set:       a boolean state passing enable/disable request
>> + *
>> + * There is a need of pausing DREX DMC when divider or MUX in clock tree
>> + * changes its configuration. In such situation access to the memory is blocked
>> + * in DMC automatically. This feature is used when clock frequency change
>> + * request appears and touches clock tree.
>> + */
>> +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
>> +{
>> +       unsigned int val;
>> +       int ret;
>> +
>> +       ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
>> +       if (ret)
>> +               return ret;
>> +
>> +       val |= 1UL;
>> +       regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
>> +
>> +       return 0;
>> +}
>> +
>> +/**
>> + * exynos5_dmc_probe() - Probe function for the DMC driver
>> + * @pdev:      platform device for which the driver is going to be initialized
>> + *
>> + * Initialize basic components: clocks, regulators, performance counters, etc.
>> + * Read out product version and based on the information setup
>> + * internal structures for the controller (frequency and voltage) and for DRAM
>> + * memory parameters: timings for each operating frequency.
>> + * Register new devfreq device for controlling DVFS of the DMC.
>> + */
>> +static int exynos5_dmc_probe(struct platform_device *pdev)
>> +{
>> +       int ret = 0;
>> +       struct exynos5_dmc *dmc;
> 
> A nit: put un-initialized variables close to each other, it brings some order.
OK
> 
>> +       struct device *dev = &pdev->dev;
>> +       struct device_node *np = dev->of_node;
>> +       struct resource *res;
>> +
>> +       dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
>> +       if (!dmc)
>> +               return -ENOMEM;
>> +
>> +       mutex_init(&dmc->lock);
>> +
>> +       dmc->dev = dev;
>> +       platform_set_drvdata(pdev, dmc);
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       dmc->base_drexi0 = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(dmc->base_drexi0))
>> +               return PTR_ERR(dmc->base_drexi0);
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +       dmc->base_drexi1 = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(dmc->base_drexi1))
>> +               return PTR_ERR(dmc->base_drexi1);
>> +
>> +       dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
>> +                               "samsung,syscon-clk");
>> +       if (IS_ERR(dmc->clk_regmap))
>> +               return PTR_ERR(dmc->clk_regmap);
>> +
>> +       ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
>> +       if (ret) {
>> +               dev_warn(dev, "couldn't initialize frequency settings\n");
>> +               return ret;
>> +       }
>> +
>> +       dmc->vdd_mif = devm_regulator_get(dev, "vdd");
>> +       if (IS_ERR(dmc->vdd_mif)) {
>> +               ret = PTR_ERR(dmc->vdd_mif);
>> +               return ret;
>> +       }
>> +
>> +       ret = exynos5_dmc_init_clks(dmc);
>> +       if (ret)
>> +               return ret;
>> +
>> +       ret = of_get_dram_timings(dmc);
>> +       if (ret) {
>> +               dev_warn(dev, "couldn't initialize timings settings\n");
>> +               return ret;
>> +       }
>> +
>> +       ret = exynos5_performance_counters_init(dmc);
>> +       if (ret) {
>> +               dev_warn(dev, "couldn't probe performance counters\n");
>> +               goto remove_clocks;
>> +       }
>> +
>> +       ret = exynos5_dmc_set_pause_on_switching(dmc);
>> +       if (ret) {
>> +               dev_warn(dev, "couldn't get access to PAUSE register\n");
>> +               goto remove_clocks;
>> +       }
>> +
>> +       /*
>> +        * Setup default thresholds for the devfreq governor.
>> +        * The values are chosen based on experiments.
>> +        */
>> +       dmc->gov_data.upthreshold = 30;
>> +       dmc->gov_data.downdifferential = 5;
>> +
>> +       dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
>> +                                         DEVFREQ_GOV_USERSPACE,
>> +                                         &dmc->gov_data);
>> +
>> +       if (IS_ERR(dmc->df)) {
>> +               ret = PTR_ERR(dmc->df);
>> +               goto err_devfreq_add;
>> +       }
>> +
>> +       dev_info(dev, "DMC initialized\n");
>> +
>> +       return 0;
>> +
>> +err_devfreq_add:
>> +       exynos5_counters_disable_edev(dmc);
>> +remove_clocks:
>> +       clk_disable_unprepare(dmc->mout_spll);
>> +       clk_disable_unprepare(dmc->fout_spll);
> 
> This looks unbalanced. Where was the enable of fout_spll? This is
> weird - some clocks are disabled in this error path but not in
> remove(). Some the opposite - not disabled on error path.
It should be 'mout_bpll' and 'fout_bpll'.

Thank you for the review.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

Re: [PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422

[Krzysztof Kozlowski]

On Thu, 6 Jun 2019 at 12:38, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> Hi Krzysztof,
> >> +/**
> >> + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
> >> + * @dmc:       DMC structure containing needed fields
> >> + *
> >> + * Get the needed clocks defined in DT device, enable and set the right parents.
> >> + * Read current frequency and initialize the initial rate for governor.
> >> + */
> >> +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
> >> +{
> >> +       int ret;
> >> +       unsigned long target_volt = 0;
> >> +       unsigned long target_rate = 0;
> >> +
> >> +       dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
> >> +       if (IS_ERR(dmc->fout_spll))
> >> +               return PTR_ERR(dmc->fout_spll);
> >> +
> >> +       dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
> >> +       if (IS_ERR(dmc->fout_bpll))
> >> +               return PTR_ERR(dmc->fout_bpll);
> >> +
> >> +       dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
> >> +       if (IS_ERR(dmc->mout_mclk_cdrex))
> >> +               return PTR_ERR(dmc->mout_mclk_cdrex);
> >
> > You are not enabling this clock. It is divider so it is fine for him
> > but what about its parents? How can you guarantee that parents are
> > enabled?
> It uses two parents in this configuration:
> 1. 'mout_bpll' which is set by the bootloader and is a default mode
> 2. 'mout_mx_mspll_ccore' which is used temporary as a 'bypass clock
> source' only for the time when BPLL is changing it's settings
>
> Do you suggest to put a call:
>
> to make sure the parent is up and running?
> OR just move the lines from the end of this function:
>         clk_prepare_enable(dmc->fout_bpll);
>         clk_prepare_enable(dmc->mout_bpll);
> and add:
>         ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
> then call the clk_get_rate on 'mout_mclk_cdrex'
>

Ah, It's my mistake. I missed that later you enable its new parent. It's fine.

Best regards,
Krzysztof

Re: [PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422

[Lukasz Luba]

On 6/6/19 1:45 PM, Krzysztof Kozlowski wrote:
> On Thu, 6 Jun 2019 at 12:38, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>> Hi Krzysztof,
>>>> +/**
>>>> + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
>>>> + * @dmc:       DMC structure containing needed fields
>>>> + *
>>>> + * Get the needed clocks defined in DT device, enable and set the right parents.
>>>> + * Read current frequency and initialize the initial rate for governor.
>>>> + */
>>>> +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
>>>> +{
>>>> +       int ret;
>>>> +       unsigned long target_volt = 0;
>>>> +       unsigned long target_rate = 0;
>>>> +
>>>> +       dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
>>>> +       if (IS_ERR(dmc->fout_spll))
>>>> +               return PTR_ERR(dmc->fout_spll);
>>>> +
>>>> +       dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
>>>> +       if (IS_ERR(dmc->fout_bpll))
>>>> +               return PTR_ERR(dmc->fout_bpll);
>>>> +
>>>> +       dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
>>>> +       if (IS_ERR(dmc->mout_mclk_cdrex))
>>>> +               return PTR_ERR(dmc->mout_mclk_cdrex);
>>>
>>> You are not enabling this clock. It is divider so it is fine for him
>>> but what about its parents? How can you guarantee that parents are
>>> enabled?
>> It uses two parents in this configuration:
>> 1. 'mout_bpll' which is set by the bootloader and is a default mode
>> 2. 'mout_mx_mspll_ccore' which is used temporary as a 'bypass clock
>> source' only for the time when BPLL is changing it's settings
>>
>> Do you suggest to put a call:
>>
>> to make sure the parent is up and running?
>> OR just move the lines from the end of this function:
>>          clk_prepare_enable(dmc->fout_bpll);
>>          clk_prepare_enable(dmc->mout_bpll);
>> and add:
>>          ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
>> then call the clk_get_rate on 'mout_mclk_cdrex'
>>
> 
> Ah, It's my mistake. I missed that later you enable its new parent. It's fine.
OK, so I will leave it as is and just fix the other stuff that you've
mentioned.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

[PATCH v8 09/13] drivers: devfreq: events: add Exynos PPMU new events

[Lukasz Luba]

Define new performance events supported by Exynos5422 SoC counters.
The counters are built-in in Dynamic Memory Controller and provide
information regarding memory utilization.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/devfreq/event/exynos-ppmu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c
index c2ea94957501..ce658c262c27 100644
--- a/drivers/devfreq/event/exynos-ppmu.c
+++ b/drivers/devfreq/event/exynos-ppmu.c
@@ -89,6 +89,12 @@ static struct __exynos_ppmu_events {
 	PPMU_EVENT(d1-cpu),
 	PPMU_EVENT(d1-general),
 	PPMU_EVENT(d1-rt),
+
+	/* For Exynos5422 SoC */
+	PPMU_EVENT(dmc0_0),
+	PPMU_EVENT(dmc0_1),
+	PPMU_EVENT(dmc1_0),
+	PPMU_EVENT(dmc1_1),
 };
 
 static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev)
-- 
2.17.1

[PATCH v8 10/13] ARM: dts: exynos: add chipid label and syscon compatible

[Lukasz Luba]

Add the chipid label which allows to use it in phandle from other device.
Use syscon in compatible to get the regmap of the device register set.
The chipid is used in DMC during initialization to compare compatibility.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 67f9b4504a42..4801ca759feb 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -35,8 +35,8 @@
 		#size-cells = <1>;
 		ranges;
 
-		chipid@10000000 {
-			compatible = "samsung,exynos4210-chipid";
+		chipid: chipid@10000000 {
+			compatible = "samsung,exynos4210-chipid", "syscon";
 			reg = <0x10000000 0x100>;
 		};
 
-- 
2.17.1

[PATCH v8 11/13] ARM: dts: exynos: add syscon to clock compatible

[Lukasz Luba]

In order to get the clock by phandle and use it with regmap it needs to be
compatible with syscon. The DMC driver uses two registers from clock
register set and needs the regmap of them.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 2 +-
 arch/arm/boot/dts/exynos5800.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..d153617ff1a3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -173,7 +173,7 @@
 		};
 
 		clock: clock-controller@10010000 {
-			compatible = "samsung,exynos5420-clock";
+			compatible = "samsung,exynos5420-clock", "syscon";
 			reg = <0x10010000 0x30000>;
 			#clock-cells = <1>;
 		};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319fd65..0a2b3287ed92 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,7 +17,7 @@
 };
 
 &clock {
-	compatible = "samsung,exynos5800-clock";
+	compatible = "samsung,exynos5800-clock", "syscon";
 };
 
 &cluster_a15_opp_table {
-- 
2.17.1

[PATCH v8 12/13] ARM: dts: exynos: add DMC device for exynos5422

[Lukasz Luba]

Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
There is a definition of the memory chip, which is then used during
calculation of timings for each OPP.
The algorithm in the driver needs these two sets to bound the timings.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi             |  79 ++++++++++++
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++
 2 files changed, 195 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index d153617ff1a3..a18b225c983e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -235,6 +235,37 @@
 			status = "disabled";
 		};
 
+		dmc: memory-controller@10c20000 {
+			compatible = "samsung,exynos5422-dmc";
+			reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
+			clocks = <&clock CLK_FOUT_SPLL>,
+				 <&clock CLK_MOUT_SCLK_SPLL>,
+				 <&clock CLK_FF_DOUT_SPLL2>,
+				 <&clock CLK_FOUT_BPLL>,
+				 <&clock CLK_MOUT_BPLL>,
+				 <&clock CLK_SCLK_BPLL>,
+				 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+				 <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+				 <&clock CLK_MOUT_MCLK_CDREX>,
+				 <&clock CLK_DOUT_CLK2X_PHY0>,
+				 <&clock CLK_CLKM_PHY0>,
+				 <&clock CLK_CLKM_PHY1>;
+			clock-names = "fout_spll",
+				      "mout_sclk_spll",
+				      "ff_dout_spll2",
+				      "fout_bpll",
+				      "mout_bpll",
+				      "sclk_bpll",
+				      "mout_mx_mspll_ccore",
+				      "mout_mx_mspll_ccore_phy",
+				      "mout_mclk_cdrex",
+				      "dout_clk2x_phy0",
+				      "clkm_phy0",
+				      "clkm_phy1";
+			samsung,syscon-clk = <&clock>;
+			status = "disabled";
+		};
+
 		nocp_mem0_0: nocp@10ca1000 {
 			compatible = "samsung,exynos5420-nocp";
 			reg = <0x10CA1000 0x200>;
@@ -271,6 +302,54 @@
 			status = "disabled";
 		};
 
+		ppmu_dmc0_0: ppmu@10d00000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d00000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+					event-name = "ppmu-event3-dmc0_0";
+				};
+			};
+		};
+
+		ppmu_dmc0_1: ppmu@10d10000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d10000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+					event-name = "ppmu-event3-dmc0_1";
+				};
+			};
+		};
+
+		ppmu_dmc1_0: ppmu@10d60000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d60000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+					event-name = "ppmu-event3-dmc1_0";
+				};
+			};
+		};
+
+		ppmu_dmc1_1: ppmu@10d70000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d70000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+					event-name = "ppmu-event3-dmc1_1";
+				};
+			};
+		};
+
 		gsc_pd: power-domain@10044000 {
 			compatible = "samsung,exynos4210-pd";
 			reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..30e569c13ee7 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -34,6 +34,97 @@
 			clock-frequency = <24000000>;
 		};
 	};
+
+	dmc_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <165000000>;
+			opp-microvolt = <875000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <206000000>;
+			opp-microvolt = <875000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <275000000>;
+			opp-microvolt = <875000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <413000000>;
+			opp-microvolt = <887500>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <543000000>;
+			opp-microvolt = <937500>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <633000000>;
+			opp-microvolt = <1012500>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <728000000>;
+			opp-microvolt = <1037500>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <825000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	samsung_K3QF2F20DB: lpddr3 {
+		compatible	= "samsung,K3QF2F20DB", "jedec,lpddr3";
+		density		= <16384>;
+		io-width	= <32>;
+		#address-cells  = <1>;
+		#size-cells     = <0>;
+
+		tRFC-min-tck		= <17>;
+		tRRD-min-tck		= <2>;
+		tRPab-min-tck		= <2>;
+		tRPpb-min-tck		= <2>;
+		tRCD-min-tck		= <3>;
+		tRC-min-tck		= <6>;
+		tRAS-min-tck		= <5>;
+		tWTR-min-tck		= <2>;
+		tWR-min-tck		= <7>;
+		tRTP-min-tck		= <2>;
+		tW2W-C2C-min-tck	= <0>;
+		tR2R-C2C-min-tck	= <0>;
+		tWL-min-tck		= <8>;
+		tDQSCK-min-tck		= <5>;
+		tRL-min-tck		= <14>;
+		tFAW-min-tck		= <5>;
+		tXSR-min-tck		= <12>;
+		tXP-min-tck		= <2>;
+		tCKE-min-tck		= <2>;
+		tCKESR-min-tck		= <2>;
+		tMRD-min-tck		= <5>;
+
+		timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+			compatible	= "jedec,lpddr3-timings";
+			reg		= <800000000>; /* workaround: it shows max-freq */
+			min-freq	= <100000000>;
+			tRFC		= <65000>;
+			tRRD		= <6000>;
+			tRPab		= <12000>;
+			tRPpb		= <12000>;
+			tRCD		= <10000>;
+			tRC		= <33750>;
+			tRAS		= <23000>;
+			tWTR		= <3750>;
+			tWR		= <7500>;
+			tRTP		= <3750>;
+			tW2W-C2C	= <0>;
+			tR2R-C2C	= <0>;
+			tFAW		= <25000>;
+			tXSR		= <70000>;
+			tXP		= <3750>;
+			tCKE		= <3750>;
+			tCKESR		= <3750>;
+			tMRD		= <7000>;
+		};
+	};
 };
 
 &adc {
@@ -132,6 +223,15 @@
 	cpu-supply = <&buck2_reg>;
 };
 
+&dmc {
+	devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,
+			<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+	device-handle = <&samsung_K3QF2F20DB>;
+	operating-points-v2 = <&dmc_opp_table>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
 &hsi2c_4 {
 	status = "okay";
 
@@ -540,6 +640,22 @@
 	};
 };
 
+&ppmu_dmc0_0 {
+	status = "okay";
+};
+
+&ppmu_dmc0_1 {
+	status = "okay";
+};
+
+&ppmu_dmc1_0 {
+	status = "okay";
+};
+
+&ppmu_dmc1_1 {
+	status = "okay";
+};
+
 &tmu_cpu0 {
 	vtmu-supply = <&ldo7_reg>;
 };
-- 
2.17.1

[PATCH v8 13/13] ARM: exynos_defconfig: enable DMC driver

[Lukasz Luba]

Enable driver for Exynos5422 Dynamic Memory Controller supporting
dynamic frequency and voltage scaling in Exynos5422 SoCs.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/configs/exynos_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index c95c54284da2..0cd16c924941 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -290,6 +290,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y
 CONFIG_DEVFREQ_GOV_POWERSAVE=y
 CONFIG_DEVFREQ_GOV_USERSPACE=y
 CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
+CONFIG_ARM_EXYNOS5422_DMC=y
 CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y
 CONFIG_EXYNOS_IOMMU=y
 CONFIG_EXTCON=y
-- 
2.17.1

Re: [PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver

[Sylwester Nawrocki]

On 6/5/19 18:53, Lukasz Luba wrote:
> Lukasz Luba (13):
>   clk: samsung: add needed IDs for DMC clocks in Exynos5420
>   clk: samsung: add new clocks for DMC for Exynos5422 SoC
>   clk: samsung: add BPLL rate table for Exynos 5422 SoC
>   dt-bindings: ddr: rename lpddr2 directory
>   dt-bindings: ddr: add LPDDR3 memories
>   drivers: memory: extend of_memory by LPDDR3 support
>   dt-bindings: memory-controllers: add Exynos5422 DMC device description
>   drivers: memory: add DMC driver for Exynos5422
>   drivers: devfreq: events: add Exynos PPMU new events
>   ARM: dts: exynos: add chipid label and syscon compatible
>   ARM: dts: exynos: add syscon to clock compatible
>   ARM: dts: exynos: add DMC device for exynos5422
>   ARM: exynos_defconfig: enable DMC driver


I have applied first 3 patches from this series to clk/samsung tree.

But can you please also send this series to linux-clk@vger.kernel.org 
ML, adding the clk maintainers (Stephen, Michael) at Cc?

Please make sure if future any clk patches are also sent to 
linux-clk@vger.kernel.org mailing list.

-- 
Thanks,
Sylwester

Re: [PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver

[Lukasz Luba]

Hi Sylwester,

On 6/6/19 3:57 PM, Sylwester Nawrocki wrote:
> On 6/5/19 18:53, Lukasz Luba wrote:
>> Lukasz Luba (13):
>>    clk: samsung: add needed IDs for DMC clocks in Exynos5420
>>    clk: samsung: add new clocks for DMC for Exynos5422 SoC
>>    clk: samsung: add BPLL rate table for Exynos 5422 SoC
>>    dt-bindings: ddr: rename lpddr2 directory
>>    dt-bindings: ddr: add LPDDR3 memories
>>    drivers: memory: extend of_memory by LPDDR3 support
>>    dt-bindings: memory-controllers: add Exynos5422 DMC device description
>>    drivers: memory: add DMC driver for Exynos5422
>>    drivers: devfreq: events: add Exynos PPMU new events
>>    ARM: dts: exynos: add chipid label and syscon compatible
>>    ARM: dts: exynos: add syscon to clock compatible
>>    ARM: dts: exynos: add DMC device for exynos5422
>>    ARM: exynos_defconfig: enable DMC driver
> 
> 
> I have applied first 3 patches from this series to clk/samsung tree.
Thank you
> 
> But can you please also send this series to linux-clk@vger.kernel.org
> ML, adding the clk maintainers (Stephen, Michael) at Cc?
I will. There are some minor clean-ups in patch 8/13 pointed by
Krzysztof, I am going to sent v9, so I will add them on CC.
> 
> Please make sure if future any clk patches are also sent to
> linux-clk@vger.kernel.org mailing list.
OK
> 

Regards,
Lukasz