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From: Oleksij Rempel <o.rempel@pengutronix.de>
To: Daniel Baluta <daniel.baluta@gmail.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
	jassisinghbrar@gmail.com, Aisheng Dong <aisheng.dong@nxp.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3] mailbox: imx: add support for imx v1 mu
Date: Fri, 2 Aug 2019 06:29:40 +0200	[thread overview]
Message-ID: <20190802042940.5rhmrwr3dxona4kr@pengutronix.de> (raw)
In-Reply-To: <CAEnQRZBJTCMYXwBz9pDVGD+7-gE_Jba-5kwXYC8qOPkEBiVT=g@mail.gmail.com>

On Fri, Aug 02, 2019 at 06:54:27AM +0300, Daniel Baluta wrote:
> One more thing. See below:
> 
> On Wed, Jul 31, 2019 at 12:14 PM Richard Zhu <hongxing.zhu@nxp.com> wrote:
> 
> <snip>
> 
> > -/* Control Register */
> > -#define IMX_MU_xCR             0x24
> >  /* General Purpose Interrupt Enable */
> >  #define IMX_MU_xCR_GIEn(x)     BIT(28 + (3 - (x)))
> >  /* Receive Interrupt Enable */
> > @@ -44,6 +36,13 @@ enum imx_mu_chan_type {
> >         IMX_MU_TYPE_RXDB,       /* Rx doorbell */
> >  };
> >
> > +struct imx_mu_dcfg {
> 
> Can you rename this into imx_mu_regs ?

I decided not blame this part. Otherwise adding other type of quirks
will lead to more refactoring work.

> > +       u32     xTR[4];         /* Transmit Registers */
> > +       u32     xRR[4];         /* Receive Registers */
> > +       u32     xSR;            /* Status Register */
> > +       u32     xCR;            /* Control Register */
> > +};
> 

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  reply	other threads:[~2019-08-02  4:29 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31  8:51 Richard Zhu
2019-08-01 14:47 ` Daniel Baluta
2019-08-02  3:24   ` [EXT] " Richard Zhu
2019-08-02  3:54 ` Daniel Baluta
2019-08-02  4:29   ` Oleksij Rempel [this message]
  -- strict thread matches above, loose matches on Subject: below --
2019-07-30  5:12 Richard Zhu
2019-07-30  5:12 ` Richard Zhu

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